case 'u':
macro_read_relocs (&args, r);
gas_assert (ep != NULL
- && (ep->X_op == O_constant
- || (ep->X_op == O_symbol
- && (*r == BFD_RELOC_MIPS_HIGHEST
- || *r == BFD_RELOC_HI16_S
- || *r == BFD_RELOC_HI16
- || *r == BFD_RELOC_GPREL16
- || *r == BFD_RELOC_MIPS_GOT_HI16
- || *r == BFD_RELOC_MIPS_CALL_HI16))));
+ && (ep->X_op == O_constant
+ || (ep->X_op == O_symbol
+ && (*r == BFD_RELOC_MIPS_HIGHEST
+ || *r == BFD_RELOC_HI16_S
+ || *r == BFD_RELOC_HI16
+ || *r == BFD_RELOC_GPREL16
+ || *r == BFD_RELOC_MIPS_GOT_HI16
+ || *r == BFD_RELOC_MIPS_CALL_HI16))));
continue;
case 'p':
break;
default:
macro_build (NULL, "balign", "t,s,2", treg, sreg,
- (int)imm_expr.X_add_number);
+ (int) imm_expr.X_add_number);
break;
}
break;
case M_BGTL_I:
likely = 1;
case M_BGT_I:
- /* check for > max integer */
+ /* Check for > max integer. */
maxnum = 0x7fffffff;
if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
{
&& (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
{
do_false:
- /* result is always false */
+ /* Result is always false. */
if (! likely)
macro_build (NULL, "nop", "", 0);
else
unsigned long pos;
unsigned long size;
- if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
+ if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
{
as_bad (_("Unsupported large constant"));
pos = size = 1;
as_bad (_("Improper position (%lu)"), pos);
pos = 1;
}
- if (size == 0 || size > 64
- || (pos + size - 1) > 63)
+ if (size == 0 || size > 64 || (pos + size - 1) > 63)
{
as_bad (_("Improper extract size (%lu, position %lu)"),
size, pos);
unsigned long pos;
unsigned long size;
- if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
+ if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
{
as_bad (_("Unsupported large constant"));
pos = size = 1;
as_bad (_("Improper position (%lu)"), pos);
pos = 1;
}
- if (size == 0 || size > 64
- || (pos + size - 1) > 63)
+ if (size == 0 || size > 64 || (pos + size - 1) > 63)
{
as_bad (_("Improper insert size (%lu, position %lu)"),
size, pos);
if (dbl && HAVE_32BIT_GPRS)
as_warn (_("dla used to load 32-bit register"));
- if (! dbl && HAVE_64BIT_OBJECTS)
+ if (!dbl && HAVE_64BIT_OBJECTS)
as_warn (_("la used to load 64-bit address"));
if (offset_expr.X_op == O_constant
as_warn (_("No .cprestore pseudo-op used in PIC code"));
else
{
- if (! mips_frame_reg_valid)
+ if (!mips_frame_reg_valid)
{
as_warn (_("No .frame pseudo-op used in PIC code"));
/* Quiet this warning. */
mips_frame_reg_valid = 1;
}
- if (! mips_cprestore_valid)
+ if (!mips_cprestore_valid)
{
as_warn (_("No .cprestore pseudo-op used in PIC code"));
/* Quiet this warning. */
GOT_DISP. */
if (HAVE_NEWABI)
{
- if (! mips_big_got)
+ if (!mips_big_got)
{
relax_start (offset_expr.X_add_symbol);
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
else
{
relax_start (offset_expr.X_add_symbol);
- if (! mips_big_got)
+ if (!mips_big_got)
{
macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
as_warn (_("No .cprestore pseudo-op used in PIC code"));
else
{
- if (! mips_frame_reg_valid)
+ if (!mips_frame_reg_valid)
{
as_warn (_("No .frame pseudo-op used in PIC code"));
/* Quiet this warning. */
mips_frame_reg_valid = 1;
}
- if (! mips_cprestore_valid)
+ if (!mips_cprestore_valid)
{
as_warn (_("No .cprestore pseudo-op used in PIC code"));
/* Quiet this warning. */
else
{
gas_assert (offset_expr.X_op == O_symbol
- && strcmp (segment_name (S_GET_SEGMENT
- (offset_expr.X_add_symbol)),
- ".lit4") == 0
- && offset_expr.X_add_number == 0);
+ && strcmp (segment_name (S_GET_SEGMENT
+ (offset_expr.X_add_symbol)),
+ ".lit4") == 0
+ && offset_expr.X_add_number == 0);
macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
break;
}
gas_assert (offset_expr.X_op == O_symbol
- && offset_expr.X_add_number == 0);
+ && offset_expr.X_add_number == 0);
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
to adjust when loading from memory. We set coproc if we must
load $fn+1 first. */
/* Itbl support may require additional care here. */
- if (! target_big_endian)
+ if (!target_big_endian)
coproc = 0;
- if (mips_pic == NO_PIC
- || offset_expr.X_op == O_constant)
+ if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
{
/* If this is a reference to a GP relative symbol, we want
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
used_at = 1;
if (offset_expr.X_add_number >= 0x7fff)
as_bad (_("operand overflow"));
- if (! target_big_endian)
+ if (!target_big_endian)
++offset_expr.X_add_number;
macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
--offset_expr.X_add_number;
else
++offset_expr.X_add_number;
used_at = 1;
tempreg = AT;
}
- if (! target_big_endian)
+ if (!target_big_endian)
offset_expr.X_add_number += off;
macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
offset_expr.X_add_number -= off;
else
offset_expr.X_add_number += off;
macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
- /* If necessary, move the result in tempreg the final destination. */
+ /* If necessary, move the result in tempreg to the final destination. */
if (treg == tempreg)
break;
/* Protect second load's delay slot. */
load_address (AT, &offset_expr, &used_at);
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = off;
else
expr1.X_add_number = 0;
macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = off;
usw:
if (offset_expr.X_add_number >= 0x8000 - off)
as_bad (_("operand overflow"));
- if (! target_big_endian)
+ if (!target_big_endian)
offset_expr.X_add_number += off;
macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
offset_expr.X_add_number -= off;
else
offset_expr.X_add_number += off;
load_address (AT, &offset_expr, &used_at);
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = off;
else
expr1.X_add_number = 0;
macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = off;
load_address (AT, &offset_expr, &used_at);
if (breg != 0)
macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = 0;
macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = 1;
else
expr1.X_add_number = 0;
macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
- if (! target_big_endian)
+ if (!target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = 1;
return;
break;
- case '2': /* dsp 2-bit unsigned immediate in bit 11 */
+ case '2': /* DSP 2-bit unsigned immediate in bit 11. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number != 1
s = expr_end;
continue;
- case '3': /* dsp 3-bit unsigned immediate in bit 21 */
+ case '3': /* DSP 3-bit unsigned immediate in bit 21. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA3)
s = expr_end;
continue;
- case '4': /* dsp 4-bit unsigned immediate in bit 21 */
+ case '4': /* DSP 4-bit unsigned immediate in bit 21. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_SA4)
s = expr_end;
continue;
- case '5': /* dsp 8-bit unsigned immediate in bit 16 */
+ case '5': /* DSP 8-bit unsigned immediate in bit 16. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_IMM8)
s = expr_end;
continue;
- case '6': /* dsp 5-bit unsigned immediate in bit 21 */
+ case '6': /* DSP 5-bit unsigned immediate in bit 21. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RS)
s = expr_end;
continue;
- case '7': /* four dsp accumulators in bits 11,12 */
+ case '7': /* Four DSP accumulators in bits 11,12. */
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
as_bad (_("Invalid dsp acc register"));
break;
- case '8': /* dsp 6-bit unsigned immediate in bit 11 */
+ case '8': /* DSP 6-bit unsigned immediate in bit 11. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
s = expr_end;
continue;
- case '9': /* four dsp accumulators in bits 21,22 */
+ case '9': /* Four DSP accumulators in bits 21,22. */
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
as_bad (_("Invalid dsp acc register"));
break;
- case '0': /* dsp 6-bit signed immediate in bit 20 */
+ case '0': /* DSP 6-bit signed immediate in bit 20. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_DSPSFT + 1) >> 1);
s = expr_end;
continue;
- case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
+ case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
s = expr_end;
continue;
- case ':': /* dsp 7-bit signed immediate in bit 19 */
+ case ':': /* DSP 7-bit signed immediate in bit 19. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
s = expr_end;
continue;
- case '@': /* dsp 10-bit signed immediate in bit 16 */
+ case '@': /* DSP 10-bit signed immediate in bit 16. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
min_range = -((OP_MASK_IMM10 + 1) >> 1);
s = expr_end;
continue;
- case '*': /* four dsp accumulators in bits 18,19 */
+ case '*': /* Four DSP accumulators in bits 18,19. */
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
as_bad (_("Invalid dsp/smartmips acc register"));
break;
- case '&': /* four dsp accumulators in bits 13,14 */
+ case '&': /* Four DSP accumulators in bits 13,14. */
if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
s[3] >= '0' && s[3] <= '3')
{
if (*s == '\0')
return;
- case ')': /* these must match exactly */
+ case ')': /* These must match exactly. */
case '[':
case ']':
if (*s++ == *args)
imm->desc ? imm->desc : ip->insn_mo->name,
(unsigned long) imm_expr.X_add_number,
(unsigned long) imm_expr.X_add_number);
- imm_expr.X_add_number &= imm->mask;
+ imm_expr.X_add_number &= imm->mask;
}
ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
<< imm->shift);
s = expr_end;
}
continue;
-
+
case 'A': /* ins/ext position, becomes LSB. */
limlo = 0;
limhi = 31;
limlo = 32;
limhi = 63;
goto do_lsb;
-do_lsb:
+ do_lsb:
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number < limlo
limlo = 33;
limhi = 64;
goto do_msb;
-do_msb:
+ do_msb:
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
/* Check for negative input so that small negative numbers
limlo = 33;
limhi = 64;
goto do_msbd;
-do_msbd:
+ do_msbd:
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
/* Check for negative input so that small negative numbers
continue;
default:
- as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
- *args, insn->name, insn->args);
+ as_bad (_("Internal: bad mips opcode "
+ "(unknown extension operand type `+%c'): %s %s"),
+ *args, insn->name, insn->args);
/* Further processing is fruitless. */
return;
}
s = expr_end;
continue;
- case 'k': /* cache code */
- case 'h': /* prefx code */
- case '1': /* sync type */
+ case 'k': /* CACHE code. */
+ case 'h': /* PREFX code. */
+ case '1': /* SYNC type. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > 31)
s = expr_end;
continue;
- case 'c': /* break code */
+ case 'c': /* BREAK code. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
s = expr_end;
continue;
- case 'q': /* lower break code */
+ case 'q': /* Lower BREAK code. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
s = expr_end;
continue;
- case 'B': /* 20-bit syscall/break code. */
+ case 'B': /* 20-bit SYSCALL/BREAK code. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
s = expr_end;
continue;
- case 'C': /* Coprocessor code */
+ case 'C': /* Coprocessor code. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
s = expr_end;
continue;
- case 'J': /* 19-bit wait code. */
+ case 'J': /* 19-bit WAIT code. */
my_getExpression (&imm_expr, s);
check_absolute_expr (ip, &imm_expr);
if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
else
break;
- case 'b': /* base register */
- case 'd': /* destination register */
- case 's': /* source register */
- case 't': /* target register */
- case 'r': /* both target and source */
- case 'v': /* both dest and source */
- case 'w': /* both dest and target */
- case 'E': /* coprocessor target register */
- case 'K': /* 'rdhwr' destination register */
- case 'x': /* ignore register name */
- case 'z': /* must be zero register */
- case 'U': /* destination register (clo/clz). */
- case 'g': /* coprocessor destination register */
- s_reset = s;
+ case 'b': /* Base register. */
+ case 'd': /* Destination register. */
+ case 's': /* Source register. */
+ case 't': /* Target register. */
+ case 'r': /* Both target and source. */
+ case 'v': /* Both dest and source. */
+ case 'w': /* Both dest and target. */
+ case 'E': /* Coprocessor target register. */
+ case 'K': /* RDHWR destination register. */
+ case 'x': /* Ignore register name. */
+ case 'z': /* Must be zero register. */
+ case 'U': /* Destination register (CLO/CLZ). */
+ case 'g': /* Coprocessor destination register. */
+ s_reset = s;
if (*args == 'E' || *args == 'K')
ok = reg_lookup (&s, RTYPE_NUM, ®no);
else
if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
{
if (regno == lastregno)
- {
- insn_error = _("source and destination must be different");
+ {
+ insn_error
+ = _("source and destination must be different");
continue;
- }
+ }
if (regno == 31 && lastregno == 0xffffffff)
- {
- insn_error = _("a destination register must be supplied");
+ {
+ insn_error
+ = _("a destination register must be supplied");
continue;
- }
+ }
}
- /* Now that we have assembled one operand, we use the args string
- * to figure out where it goes in the instruction. */
+ /* Now that we have assembled one operand, we use the args
+ string to figure out where it goes in the instruction. */
switch (c)
{
case 'r':
case 'Y': /* MDMX source register. */
case 'Z': /* MDMX target register. */
is_mdmx = 1;
- case 'D': /* floating point destination register */
- case 'S': /* floating point source register */
- case 'T': /* floating point target register */
- case 'R': /* floating point source register */
+ case 'D': /* Floating point destination register. */
+ case 'S': /* Floating point source register. */
+ case 'T': /* Floating point target register. */
+ case 'R': /* Floating point source register. */
case 'V':
case 'W':
rtype = RTYPE_FPU;
{
if ((regno & 1) != 0
&& HAVE_32BIT_FPRS
- && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
+ && !mips_oddfpreg_ok (ip->insn_mo, argnum))
as_warn (_("Float register should be even, was %d"),
regno);
ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
OP_SH_VSEL);
}
- /* Fall through */
+ /* Fall through. */
case 'W':
case 'T':
case 'Z':
|| (temp[2] == 0 && temp[3] == 0))))
{
imm_expr.X_op = O_constant;
- if (! target_big_endian)
+ if (!target_big_endian)
imm_expr.X_add_number = bfd_getl32 (temp);
else
imm_expr.X_add_number = bfd_getb32 (temp);
}
else if (length > 4
- && ! mips_disable_float_construction
+ && !mips_disable_float_construction
/* Constants can only be constructed in GPRs and
copied to FPRs if the GPRs are at least as wide
as the FPRs. Force the constant into memory if
we are using 64-bit FPRs but the GPRs are only
32 bits wide. */
&& (using_gprs
- || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
+ || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
&& ((temp[0] == 0 && temp[1] == 0)
|| (temp[2] == 0 && temp[3] == 0))
&& ((temp[4] == 0 && temp[5] == 0)
|| (temp[6] == 0 && temp[7] == 0)))
{
/* The value is simple enough to load with a couple of
- instructions. If using 32-bit registers, set
- imm_expr to the high order 32 bits and offset_expr to
- the low order 32 bits. Otherwise, set imm_expr to
- the entire 64 bit constant. */
+ instructions. If using 32-bit registers, set
+ imm_expr to the high order 32 bits and offset_expr to
+ the low order 32 bits. Otherwise, set imm_expr to
+ the entire 64 bit constant. */
if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
- if (! target_big_endian)
+ if (!target_big_endian)
{
imm_expr.X_add_number = bfd_getl32 (temp + 4);
offset_expr.X_add_number = bfd_getl32 (temp);
else if (sizeof (imm_expr.X_add_number) > 4)
{
imm_expr.X_op = O_constant;
- if (! target_big_endian)
+ if (!target_big_endian)
imm_expr.X_add_number = bfd_getl64 (temp);
else
imm_expr.X_add_number = bfd_getb64 (temp);
{
imm_expr.X_op = O_big;
imm_expr.X_add_number = 4;
- if (! target_big_endian)
+ if (!target_big_endian)
{
generic_bignum[0] = bfd_getl16 (temp);
generic_bignum[1] = bfd_getl16 (temp + 2);
}
continue;
- case 'i': /* 16 bit unsigned immediate */
- case 'j': /* 16 bit signed immediate */
+ case 'i': /* 16-bit unsigned immediate. */
+ case 'j': /* 16-bit signed immediate. */
*imm_reloc = BFD_RELOC_LO16;
if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
{
s = expr_end;
continue;
- case 'o': /* 16 bit offset */
+ case 'o': /* 16-bit offset. */
offset_reloc[0] = BFD_RELOC_LO16;
offset_reloc[1] = BFD_RELOC_UNUSED;
offset_reloc[2] = BFD_RELOC_UNUSED;
s = expr_end;
continue;
- case 'p': /* pc relative offset */
+ case 'p': /* PC-relative offset. */
*offset_reloc = BFD_RELOC_16_PCREL_S2;
my_getExpression (&offset_expr, s);
s = expr_end;
continue;
- case 'u': /* upper 16 bits */
+ case 'u': /* Upper 16 bits. */
if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
&& imm_expr.X_op == O_constant
&& (imm_expr.X_add_number < 0
s = expr_end;
continue;
- case 'a': /* 26 bit address */
+ case 'a': /* 26-bit address. */
my_getExpression (&offset_expr, s);
s = expr_end;
*offset_reloc = BFD_RELOC_MIPS_JMP;
continue;
- case 'N': /* 3 bit branch condition code */
- case 'M': /* 3 bit compare condition code */
+ case 'N': /* 3-bit branch condition code. */
+ case 'M': /* 3-bit compare condition code. */
rtype = RTYPE_CCC;
- if (ip->insn_mo->pinfo & (FP_D| FP_S))
+ if (ip->insn_mo->pinfo & (FP_D | FP_S))
rtype |= RTYPE_FCC;
if (!reg_lookup (&s, rtype, ®no))
break;
- if ((strcmp(str + strlen(str) - 3, ".ps") == 0
- || strcmp(str + strlen(str) - 5, "any2f") == 0
- || strcmp(str + strlen(str) - 5, "any2t") == 0)
+ if ((strcmp (str + strlen (str) - 3, ".ps") == 0
+ || strcmp (str + strlen (str) - 5, "any2f") == 0
+ || strcmp (str + strlen (str) - 5, "any2t") == 0)
&& (regno & 1) != 0)
- as_warn (_("Condition code register should be even for %s, was %d"),
+ as_warn (_("Condition code register should be even for %s, "
+ "was %d"),
str, regno);
- if ((strcmp(str + strlen(str) - 5, "any4f") == 0
- || strcmp(str + strlen(str) - 5, "any4t") == 0)
+ if ((strcmp (str + strlen (str) - 5, "any4f") == 0
+ || strcmp (str + strlen (str) - 5, "any4t") == 0)
&& (regno & 3) != 0)
- as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
+ as_warn (_("Condition code register should be 0 or 4 for %s, "
+ "was %d"),
str, regno);
if (*args == 'N')
INSERT_OPERAND (BCC, *ip, regno);
return;
gas_assert (fixP->fx_size == 4
- || fixP->fx_r_type == BFD_RELOC_16
- || fixP->fx_r_type == BFD_RELOC_64
- || fixP->fx_r_type == BFD_RELOC_CTOR
- || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
- || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
- || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
+ || fixP->fx_r_type == BFD_RELOC_16
+ || fixP->fx_r_type == BFD_RELOC_64
+ || fixP->fx_r_type == BFD_RELOC_CTOR
+ || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+ || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
projects / external / binutils.git / commitdiff