case AMDGPU::SI_SPILL_S96_RESTORE:
case AMDGPU::SI_SPILL_V96_SAVE:
case AMDGPU::SI_SPILL_V96_RESTORE:
+ case AMDGPU::SI_SPILL_A96_SAVE:
+ case AMDGPU::SI_SPILL_A96_RESTORE:
return 3;
case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S64_RESTORE:
case AMDGPU::SI_SPILL_A1024_SAVE:
case AMDGPU::SI_SPILL_A512_SAVE:
case AMDGPU::SI_SPILL_A128_SAVE:
+ case AMDGPU::SI_SPILL_A96_SAVE:
case AMDGPU::SI_SPILL_A64_SAVE:
case AMDGPU::SI_SPILL_A32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
case AMDGPU::SI_SPILL_V1024_RESTORE:
case AMDGPU::SI_SPILL_A32_RESTORE:
case AMDGPU::SI_SPILL_A64_RESTORE:
+ case AMDGPU::SI_SPILL_A96_RESTORE:
case AMDGPU::SI_SPILL_A128_RESTORE:
case AMDGPU::SI_SPILL_A512_RESTORE:
case AMDGPU::SI_SPILL_A1024_RESTORE: {
S_NOP 0, implicit undef $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255
S_NOP 0, implicit %0
...
+
+---
+name: spill_restore_agpr96
+tracksRegLiveness: true
+machineFunctionInfo:
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
+ stackPtrOffsetReg: $sgpr32
+body: |
+ ; SPILLED-LABEL: name: spill_restore_agpr96
+ ; SPILLED: bb.0:
+ ; SPILLED: successors: %bb.1(0x80000000)
+ ; SPILLED: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2
+ ; SPILLED: SI_SPILL_A96_SAVE killed $agpr0_agpr1_agpr2, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 12 into %stack.0, align 4, addrspace 5)
+ ; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ ; SPILLED: bb.1:
+ ; SPILLED: successors: %bb.2(0x80000000)
+ ; SPILLED: S_NOP 1
+ ; SPILLED: bb.2:
+ ; SPILLED: $agpr0_agpr1_agpr2 = SI_SPILL_A96_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 12 from %stack.0, align 4, addrspace 5)
+ ; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
+ ; EXPANDED-LABEL: name: spill_restore_agpr96
+ ; EXPANDED: bb.0:
+ ; EXPANDED: successors: %bb.1(0x80000000)
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr1 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr2 = V_ACCVGPR_READ_B32 killed $agpr2, implicit $exec, implicit killed $agpr0_agpr1_agpr2
+ ; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ ; EXPANDED: bb.1:
+ ; EXPANDED: successors: %bb.2(0x80000000)
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: S_NOP 1
+ ; EXPANDED: bb.2:
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: $agpr2 = V_ACCVGPR_WRITE_B32 $vgpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
+ bb.0:
+ S_NOP 0, implicit-def %0:areg_96
+ S_CBRANCH_SCC1 implicit undef $scc, %bb.1
+
+ bb.1:
+ S_NOP 1
+
+ bb.2:
+ S_NOP 0, implicit %0
+...