ppc4xx: Add output for bootrom location to 405EZ ports

Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 2d8740c..8e6bc84 100644 (file)
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -125,6 +125,7 @@ int i2c_bootrom_enabled(void)
        return (val & SDR0_SDCS_SDD);
 #endif
 }
+#endif
 
 #if defined(CONFIG_440GX)
 #define SDR0_PINSTP_SHIFT      29
@@ -178,16 +179,37 @@ static char *bootstrap_str[] = {
 };
 #endif
 
+#if defined(CONFIG_405EZ)
+#define SDR0_PINSTP_SHIFT      28
+static char *bootstrap_str[] = {
+       "EBC (8 bits)",
+       "SPI (fast)",
+       "NAND (512 page, 4 addr cycle)",
+       "I2C (Addr 0x50)",
+       "EBC (32 bits)",
+       "I2C (Addr 0x50)",
+       "NAND (2K page, 5 addr cycle)",
+       "I2C (Addr 0x50)",
+       "EBC (16 bits)",
+       "Reserved",
+       "NAND (2K page, 4 addr cycle)",
+       "I2C (Addr 0x50)",
+       "NAND (512 page, 3 addr cycle)",
+       "I2C (Addr 0x50)",
+       "SPI (slow)",
+       "I2C (Addr 0x50)",
+};
+#endif
+
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
 {
        unsigned long val;
 
-       mfsdr(sdr_pinstp, val);
-       return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+       mfsdr(SDR_PINSTP, val);
+       return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 }
 #endif /* SDR0_PINSTP_SHIFT */
-#endif
 
 
 #if defined(CONFIG_440)
@@ -403,11 +425,11 @@ int checkcpu (void)
 
 #if defined(I2C_BOOTROM)
        printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#endif /* I2C_BOOTROM */
 #if defined(SDR0_PINSTP_SHIFT)
        printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
        printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
 #endif /* SDR0_PINSTP_SHIFT */
-#endif /* I2C_BOOTROM */
 
 #if defined(CONFIG_PCI)
        printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");

diff --git a/include/ppc405.h b/include/ppc405.h
index 08f10d2..a2503a9 100644 (file)
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -570,6 +570,8 @@
 #define SDR_ICTX0_STAT 0x40000000
 #define SDR_ICTX1_STAT 0x20000000
 
+#define SDR_PINSTP     0x40
+
 /******************************************************************************
  * Control
  ******************************************************************************/

diff --git a/include/ppc440.h b/include/ppc440.h
index 51e6b9b..bc1d7aa 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -148,7 +148,7 @@
 #define sdrcfgd                (SDR_DCR_BASE+0x1)
 #define sdr_sdstp0     0x0020      /* */
 #define sdr_sdstp1     0x0021      /* */
-#define sdr_pinstp     0x0040
+#define SDR_PINSTP     0x0040
 #define sdr_sdcs       0x0060
 #define sdr_ecid0      0x0080
 #define sdr_ecid1      0x0081