[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...

Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD,
G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors.

Fixes https://github.com/llvm/llvm-project/issues/58156.

Differential Revision: https://reviews.llvm.org/D143517

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 38a14d0..ab99c5c 100644 (file)
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -126,6 +126,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .legalFor({v2s64})
       .widenScalarToNextPow2(0)
       .clampScalar(0, s32, s64)
+      .clampMaxNumElements(0, s8, 16)
+      .clampMaxNumElements(0, s16, 8)
       .clampNumElements(0, v2s32, v4s32)
       .clampNumElements(0, v2s64, v2s64)
       .minScalarOrEltIf(

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 20deef9..02f96cb 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -165,6 +165,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_add_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_add_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[ADD]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[ADD1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_ADD %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_add_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_add_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[ADD1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_ADD %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            test_vector_add_nonpow2
 body:             |
   bb.0.entry:

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index f902de3..0f3dc2b 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -161,6 +161,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_and_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_and_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_AND %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_and_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_and_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_AND %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            and_v2s1
 tracksRegLiveness: true
 body:             |

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index d593d70..f988c6f 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -458,6 +458,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_mul_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_mul_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[MUL]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[MUL1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_MUL %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_mul_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_mul_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[MUL1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_MUL %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            mul_v2s1
 tracksRegLiveness: true
 body:             |

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index a55748e..2ba8e76 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -101,6 +101,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_or_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_or_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[OR]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[OR1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_OR %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_or_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_or_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[OR1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_OR %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            or_v2s1
 tracksRegLiveness: true
 body:             |

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 54183f9..3de25d9 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -81,6 +81,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_sub_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_sub_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[SUB]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[SUB1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_SUB %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_sub_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_sub_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[SUB]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[SUB1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_SUB %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            sub_v2s1
 tracksRegLiveness: true
 body:             |

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index f4cdd90..1263562 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -148,6 +148,46 @@ body:             |
 
 ...
 ---
+name:            test_vector_xor_v16s16
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_xor_v16s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[XOR]](<8 x s16>)
+    ; CHECK-NEXT: $q1 = COPY [[XOR1]](<8 x s16>)
+    %1:_(<8 x s16>) = COPY $q0
+    %2:_(<8 x s16>) = COPY $q1
+    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
+    %3:_(<16 x s16>) = G_XOR %0, %0
+    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
+    $q0 = COPY %4(<8 x s16>)
+    $q1 = COPY %5(<8 x s16>)
+
+...
+---
+name:            test_vector_xor_v32s8
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: test_vector_xor_v32s8
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
+    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY]], [[COPY]]
+    ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY1]], [[COPY1]]
+    ; CHECK-NEXT: $q0 = COPY [[XOR]](<16 x s8>)
+    ; CHECK-NEXT: $q1 = COPY [[XOR1]](<16 x s8>)
+    %0:_(<16 x s8>) = COPY $q0
+    %1:_(<16 x s8>) = COPY $q1
+    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
+    %3:_(<32 x s8>) = G_XOR %2, %2
+    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+    $q0 = COPY %7(<16 x s8>)
+    $q1 = COPY %8(<16 x s8>)
+
+...
+---
 name:            xor_v2s1
 tracksRegLiveness: true
 body:             |