}
/* set fence to a non valid value */
- pkt->fence = UINT_MAX;
+ pkt->fence = cpu_to_le32(UINT_MAX);
rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id, len, pkt_dma_addr);
if (rc) {
pkt->length = cpu_to_le32(CPUCP_NUM_OF_MSI_TYPES);
- hdev->asic_funcs->get_msi_info((u32 *)&pkt->data);
+ memset((void *) &pkt->data, 0xFF, data_size);
+ hdev->asic_funcs->get_msi_info(pkt->data);
pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_MSI_INFO_SET <<
CPUCP_PKT_CTL_OPCODE_SHIFT);
/* Wait for expected status */
rc = hl_poll_timeout(
hdev,
- fw_loader->cpu_cmd_status_to_host_reg,
+ le32_to_cpu(fw_loader->cpu_cmd_status_to_host_reg),
status,
FIELD_GET(COMMS_STATUS_STATUS_MASK, status) == expected_status,
10000,
#define CPU_BOOT_ERR0_PLL_FAIL (1 << 12)
#define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << 13)
#define CPU_BOOT_ERR0_ENABLED (1 << 31)
+#define CPU_BOOT_ERR1_ENABLED (1 << 31)
/*
* BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
#define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << 17)
#define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << 19)
#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31)
+#define CPU_BOOT_DEV_STS1_ENABLED (1 << 31)
enum cpu_boot_status {
CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */
/* communication registers mapping - consider ABI when changing */
struct cpu_dyn_regs {
- uint32_t cpu_pq_base_addr_low;
- uint32_t cpu_pq_base_addr_high;
- uint32_t cpu_pq_length;
- uint32_t cpu_pq_init_status;
- uint32_t cpu_eq_base_addr_low;
- uint32_t cpu_eq_base_addr_high;
- uint32_t cpu_eq_length;
- uint32_t cpu_eq_ci;
- uint32_t cpu_cq_base_addr_low;
- uint32_t cpu_cq_base_addr_high;
- uint32_t cpu_cq_length;
- uint32_t cpu_pf_pq_pi;
- uint32_t cpu_boot_dev_sts0;
- uint32_t cpu_boot_dev_sts1;
- uint32_t cpu_boot_err0;
- uint32_t cpu_boot_err1;
- uint32_t cpu_boot_status;
- uint32_t fw_upd_sts;
- uint32_t fw_upd_cmd;
- uint32_t fw_upd_pending_sts;
- uint32_t fuse_ver_offset;
- uint32_t preboot_ver_offset;
- uint32_t uboot_ver_offset;
- uint32_t hw_state;
- uint32_t kmd_msg_to_cpu;
- uint32_t cpu_cmd_status_to_host;
- uint32_t reserved1[32]; /* reserve for future use */
+ __le32 cpu_pq_base_addr_low;
+ __le32 cpu_pq_base_addr_high;
+ __le32 cpu_pq_length;
+ __le32 cpu_pq_init_status;
+ __le32 cpu_eq_base_addr_low;
+ __le32 cpu_eq_base_addr_high;
+ __le32 cpu_eq_length;
+ __le32 cpu_eq_ci;
+ __le32 cpu_cq_base_addr_low;
+ __le32 cpu_cq_base_addr_high;
+ __le32 cpu_cq_length;
+ __le32 cpu_pf_pq_pi;
+ __le32 cpu_boot_dev_sts0;
+ __le32 cpu_boot_dev_sts1;
+ __le32 cpu_boot_err0;
+ __le32 cpu_boot_err1;
+ __le32 cpu_boot_status;
+ __le32 fw_upd_sts;
+ __le32 fw_upd_cmd;
+ __le32 fw_upd_pending_sts;
+ __le32 fuse_ver_offset;
+ __le32 preboot_ver_offset;
+ __le32 uboot_ver_offset;
+ __le32 hw_state;
+ __le32 kmd_msg_to_cpu;
+ __le32 cpu_cmd_status_to_host;
+ __le32 reserved1[32]; /* reserve for future use */
};
/* HCDM - Habana Communications Descriptor Magic */
/* this is the comms descriptor header - meta data */
struct comms_desc_header {
- uint32_t magic; /* magic for validation */
- uint32_t crc32; /* CRC32 of the descriptor w/o header */
- uint16_t size; /* size of the descriptor w/o header */
- uint8_t version; /* descriptor version */
- uint8_t reserved[5]; /* pad to 64 bit */
+ __le32 magic; /* magic for validation */
+ __le32 crc32; /* CRC32 of the descriptor w/o header */
+ __le16 size; /* size of the descriptor w/o header */
+ __u8 version; /* descriptor version */
+ __u8 reserved[5]; /* pad to 64 bit */
};
/* this is the main FW descriptor - consider ABI when changing */
char cur_fw_ver[VERSION_MAX_LEN];
/* can be used for 1 more version w/o ABI change */
char reserved0[VERSION_MAX_LEN];
- uint64_t img_addr; /* address for next FW component load */
+ __le64 img_addr; /* address for next FW component load */
};
/*
struct comms_command {
union { /* bit fields are only for FW use */
struct {
- unsigned int size :25; /* 32MB max. */
- unsigned int reserved :2;
+ u32 size :25; /* 32MB max. */
+ u32 reserved :2;
enum comms_cmd cmd :5; /* 32 commands */
};
- unsigned int val;
+ __le32 val;
};
};
struct comms_status {
union { /* bit fields are only for FW use */
struct {
- unsigned int offset :26;
- unsigned int ram_type :2;
+ u32 offset :26;
+ enum comms_ram_types ram_type :2;
enum comms_sts status :4; /* 16 statuses */
};
- unsigned int val;
+ __le32 val;
};
};
TXE,
QPC_RESP,
NON_AXI_ERR,
+ TMR,
};
/*
__u8 pad[6];
};
+/*
+ * struct gaudi_nic_status - describes the status of a NIC port.
+ * @port: NIC port index.
+ * @bad_format_cnt: e.g. CRC.
+ * @responder_out_of_sequence_psn_cnt: e.g NAK.
+ * @high_ber_reinit_cnt: link reinit due to high BER.
+ * @correctable_err_cnt: e.g. bit-flip.
+ * @uncorrectable_err_cnt: e.g. MAC errors.
+ * @retraining_cnt: re-training counter.
+ * @up: is port up.
+ * @pcs_link: has PCS link.
+ * @phy_ready: is PHY ready.
+ * @auto_neg: is Autoneg enabled.
+ */
+struct gaudi_nic_status {
+ __u32 port;
+ __u32 bad_format_cnt;
+ __u32 responder_out_of_sequence_psn_cnt;
+ __u32 high_ber_reinit;
+ __u32 correctable_err_cnt;
+ __u32 uncorrectable_err_cnt;
+ __u32 retraining_cnt;
+ __u8 up;
+ __u8 pcs_link;
+ __u8 phy_ready;
+ __u8 auto_neg;
+};
+
+struct gaudi_flops_2_data {
+ union {
+ struct {
+ __u32 spsram_init_done : 1;
+ __u32 reserved : 31;
+ };
+ __u32 data;
+ };
+};
+
#define GAUDI_PLL_FREQ_LOW 200000000 /* 200 MHz */
#endif /* GAUDI_FW_IF_H */