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perf/x86/msr: Add Rocket Lake CPU support
author
Kan Liang
<kan.liang@linux.intel.com>
Mon, 19 Oct 2020 15:35:27 +0000
(08:35 -0700)
committer
Peter Zijlstra
<peterz@infradead.org>
Thu, 29 Oct 2020 10:00:40 +0000
(11:00 +0100)
Like Ice Lake and Tiger Lake, PPERF and SMI_COUNT MSRs are also
supported by Rocket Lake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link:
https://lkml.kernel.org/r/20201019153528.13850-3-kan.liang@linux.intel.com
arch/x86/events/msr.c
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diff --git
a/arch/x86/events/msr.c
b/arch/x86/events/msr.c
index
4be8f9c
..
680404c
100644
(file)
--- a/
arch/x86/events/msr.c
+++ b/
arch/x86/events/msr.c
@@
-99,6
+99,7
@@
static bool test_intel(int idx, void *data)
case INTEL_FAM6_ICELAKE_D:
case INTEL_FAM6_TIGERLAKE_L:
case INTEL_FAM6_TIGERLAKE:
+ case INTEL_FAM6_ROCKETLAKE:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;