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net: lan743x: Add support to SGMII register dump for PCI11010/PCI11414 chips
authorRaju Lakkaraju <Raju.Lakkaraju@microchip.com>
Mon, 7 Nov 2022 08:56:50 +0000 (14:26 +0530)
committerJakub Kicinski <kuba@kernel.org>
Thu, 10 Nov 2022 03:20:13 +0000 (19:20 -0800)
Add support to SGMII register dump

Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microchip.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/microchip/lan743x_ethtool.c patch | blob | history
drivers/net/ethernet/microchip/lan743x_ethtool.h patch | blob | history
drivers/net/ethernet/microchip/lan743x_main.c patch | blob | history
drivers/net/ethernet/microchip/lan743x_main.h patch | blob | history

diff --git a/drivers/net/ethernet/microchip/lan743x_ethtool.c b/drivers/net/ethernet/microchip/lan743x_ethtool.c
index aa1d79a..2db5949 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_ethtool.c
+++ b/drivers/net/ethernet/microchip/lan743x_ethtool.c
@@ -1195,7 +1195,7 @@ static void lan743x_common_regs(struct net_device *dev, void *p)
        struct lan743x_adapter *adapter = netdev_priv(dev);
        u32 *rb = p;
 
-       memset(p, 0, (MAX_LAN743X_ETH_REGS * sizeof(u32)));
+       memset(p, 0, (MAX_LAN743X_ETH_COMMON_REGS * sizeof(u32)));
 
        rb[ETH_PRIV_FLAGS] = adapter->flags;
        rb[ETH_ID_REV]     = lan743x_csr_read(adapter, ID_REV);
@@ -1218,17 +1218,120 @@ static void lan743x_common_regs(struct net_device *dev, void *p)
        rb[ETH_WK_SRC]     = lan743x_csr_read(adapter, MAC_WK_SRC);
 }
 
+static void lan743x_sgmii_regs(struct net_device *dev, void *p)
+{
+       struct lan743x_adapter *adp = netdev_priv(dev);
+       u32 *rb = p;
+       u16 idx;
+       int val;
+       struct {
+               u8 id;
+               u8 dev;
+               u16 addr;
+       } regs[] = {
+               { ETH_SR_VSMMD_DEV_ID1,                MDIO_MMD_VEND1, 0x0002},
+               { ETH_SR_VSMMD_DEV_ID2,                MDIO_MMD_VEND1, 0x0003},
+               { ETH_SR_VSMMD_PCS_ID1,                MDIO_MMD_VEND1, 0x0004},
+               { ETH_SR_VSMMD_PCS_ID2,                MDIO_MMD_VEND1, 0x0005},
+               { ETH_SR_VSMMD_STS,                    MDIO_MMD_VEND1, 0x0008},
+               { ETH_SR_VSMMD_CTRL,                   MDIO_MMD_VEND1, 0x0009},
+               { ETH_SR_MII_CTRL,                     MDIO_MMD_VEND2, 0x0000},
+               { ETH_SR_MII_STS,                      MDIO_MMD_VEND2, 0x0001},
+               { ETH_SR_MII_DEV_ID1,                  MDIO_MMD_VEND2, 0x0002},
+               { ETH_SR_MII_DEV_ID2,                  MDIO_MMD_VEND2, 0x0003},
+               { ETH_SR_MII_AN_ADV,                   MDIO_MMD_VEND2, 0x0004},
+               { ETH_SR_MII_LP_BABL,                  MDIO_MMD_VEND2, 0x0005},
+               { ETH_SR_MII_EXPN,                     MDIO_MMD_VEND2, 0x0006},
+               { ETH_SR_MII_EXT_STS,                  MDIO_MMD_VEND2, 0x000F},
+               { ETH_SR_MII_TIME_SYNC_ABL,            MDIO_MMD_VEND2, 0x0708},
+               { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709},
+               { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_UPR, MDIO_MMD_VEND2, 0x070A},
+               { ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_LWR, MDIO_MMD_VEND2, 0x070B},
+               { ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_UPR, MDIO_MMD_VEND2, 0x070C},
+               { ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x070D},
+               { ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_UPR, MDIO_MMD_VEND2, 0x070E},
+               { ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_LWR, MDIO_MMD_VEND2, 0x070F},
+               { ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_UPR, MDIO_MMD_VEND2, 0x0710},
+               { ETH_VR_MII_DIG_CTRL1,                MDIO_MMD_VEND2, 0x8000},
+               { ETH_VR_MII_AN_CTRL,                  MDIO_MMD_VEND2, 0x8001},
+               { ETH_VR_MII_AN_INTR_STS,              MDIO_MMD_VEND2, 0x8002},
+               { ETH_VR_MII_TC,                       MDIO_MMD_VEND2, 0x8003},
+               { ETH_VR_MII_DBG_CTRL,                 MDIO_MMD_VEND2, 0x8005},
+               { ETH_VR_MII_EEE_MCTRL0,               MDIO_MMD_VEND2, 0x8006},
+               { ETH_VR_MII_EEE_TXTIMER,              MDIO_MMD_VEND2, 0x8008},
+               { ETH_VR_MII_EEE_RXTIMER,              MDIO_MMD_VEND2, 0x8009},
+               { ETH_VR_MII_LINK_TIMER_CTRL,          MDIO_MMD_VEND2, 0x800A},
+               { ETH_VR_MII_EEE_MCTRL1,               MDIO_MMD_VEND2, 0x800B},
+               { ETH_VR_MII_DIG_STS,                  MDIO_MMD_VEND2, 0x8010},
+               { ETH_VR_MII_ICG_ERRCNT1,              MDIO_MMD_VEND2, 0x8011},
+               { ETH_VR_MII_GPIO,                     MDIO_MMD_VEND2, 0x8015},
+               { ETH_VR_MII_EEE_LPI_STATUS,           MDIO_MMD_VEND2, 0x8016},
+               { ETH_VR_MII_EEE_WKERR,                MDIO_MMD_VEND2, 0x8017},
+               { ETH_VR_MII_MISC_STS,                 MDIO_MMD_VEND2, 0x8018},
+               { ETH_VR_MII_RX_LSTS,                  MDIO_MMD_VEND2, 0x8020},
+               { ETH_VR_MII_GEN2_GEN4_TX_BSTCTRL0,    MDIO_MMD_VEND2, 0x8038},
+               { ETH_VR_MII_GEN2_GEN4_TX_LVLCTRL0,    MDIO_MMD_VEND2, 0x803A},
+               { ETH_VR_MII_GEN2_GEN4_TXGENCTRL0,     MDIO_MMD_VEND2, 0x803C},
+               { ETH_VR_MII_GEN2_GEN4_TXGENCTRL1,     MDIO_MMD_VEND2, 0x803D},
+               { ETH_VR_MII_GEN4_TXGENCTRL2,          MDIO_MMD_VEND2, 0x803E},
+               { ETH_VR_MII_GEN2_GEN4_TX_STS,         MDIO_MMD_VEND2, 0x8048},
+               { ETH_VR_MII_GEN2_GEN4_RXGENCTRL0,     MDIO_MMD_VEND2, 0x8058},
+               { ETH_VR_MII_GEN2_GEN4_RXGENCTRL1,     MDIO_MMD_VEND2, 0x8059},
+               { ETH_VR_MII_GEN4_RXEQ_CTRL,           MDIO_MMD_VEND2, 0x805B},
+               { ETH_VR_MII_GEN4_RXLOS_CTRL0,         MDIO_MMD_VEND2, 0x805D},
+               { ETH_VR_MII_GEN2_GEN4_MPLL_CTRL0,     MDIO_MMD_VEND2, 0x8078},
+               { ETH_VR_MII_GEN2_GEN4_MPLL_CTRL1,     MDIO_MMD_VEND2, 0x8079},
+               { ETH_VR_MII_GEN2_GEN4_MPLL_STS,       MDIO_MMD_VEND2, 0x8088},
+               { ETH_VR_MII_GEN2_GEN4_LVL_CTRL,       MDIO_MMD_VEND2, 0x8090},
+               { ETH_VR_MII_GEN4_MISC_CTRL2,          MDIO_MMD_VEND2, 0x8093},
+               { ETH_VR_MII_GEN2_GEN4_MISC_CTRL0,     MDIO_MMD_VEND2, 0x8099},
+               { ETH_VR_MII_GEN2_GEN4_MISC_CTRL1,     MDIO_MMD_VEND2, 0x809A},
+               { ETH_VR_MII_SNPS_CR_CTRL,             MDIO_MMD_VEND2, 0x80A0},
+               { ETH_VR_MII_SNPS_CR_ADDR,             MDIO_MMD_VEND2, 0x80A1},
+               { ETH_VR_MII_SNPS_CR_DATA,             MDIO_MMD_VEND2, 0x80A2},
+               { ETH_VR_MII_DIG_CTRL2,                MDIO_MMD_VEND2, 0x80E1},
+               { ETH_VR_MII_DIG_ERRCNT,               MDIO_MMD_VEND2, 0x80E2},
+       };
+
+       for (idx = 0; idx < ARRAY_SIZE(regs); idx++) {
+               val = lan743x_sgmii_read(adp, regs[idx].dev, regs[idx].addr);
+               if (val < 0)
+                       rb[regs[idx].id] = 0xFFFF;
+               else
+                       rb[regs[idx].id] = val;
+       }
+}
+
 static int lan743x_get_regs_len(struct net_device *dev)
 {
-       return MAX_LAN743X_ETH_REGS * sizeof(u32);
+       struct lan743x_adapter *adapter = netdev_priv(dev);
+       u32 num_regs = MAX_LAN743X_ETH_COMMON_REGS;
+
+       if (adapter->is_sgmii_en)
+               num_regs += MAX_LAN743X_ETH_SGMII_REGS;
+
+       return num_regs * sizeof(u32);
 }
 
 static void lan743x_get_regs(struct net_device *dev,
                             struct ethtool_regs *regs, void *p)
 {
+       struct lan743x_adapter *adapter = netdev_priv(dev);
+       int regs_len;
+
+       regs_len = lan743x_get_regs_len(dev);
+       memset(p, 0, regs_len);
+
        regs->version = LAN743X_ETH_REG_VERSION;
+       regs->len = regs_len;
 
        lan743x_common_regs(dev, p);
+       p = (u32 *)p + MAX_LAN743X_ETH_COMMON_REGS;
+
+       if (adapter->is_sgmii_en) {
+               lan743x_sgmii_regs(dev, p);
+               p = (u32 *)p + MAX_LAN743X_ETH_SGMII_REGS;
+       }
 }
 
 static void lan743x_get_pauseparam(struct net_device *dev,
diff --git a/drivers/net/ethernet/microchip/lan743x_ethtool.h b/drivers/net/ethernet/microchip/lan743x_ethtool.h
index 7f5996a..267d503 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_ethtool.h
+++ b/drivers/net/ethernet/microchip/lan743x_ethtool.h
@@ -29,7 +29,76 @@ enum {
        ETH_WK_SRC,
 
        /* Add new registers above */
-       MAX_LAN743X_ETH_REGS
+       MAX_LAN743X_ETH_COMMON_REGS
+};
+
+enum {
+       /* SGMII Register */
+       ETH_SR_VSMMD_DEV_ID1,
+       ETH_SR_VSMMD_DEV_ID2,
+       ETH_SR_VSMMD_PCS_ID1,
+       ETH_SR_VSMMD_PCS_ID2,
+       ETH_SR_VSMMD_STS,
+       ETH_SR_VSMMD_CTRL,
+       ETH_SR_MII_CTRL,
+       ETH_SR_MII_STS,
+       ETH_SR_MII_DEV_ID1,
+       ETH_SR_MII_DEV_ID2,
+       ETH_SR_MII_AN_ADV,
+       ETH_SR_MII_LP_BABL,
+       ETH_SR_MII_EXPN,
+       ETH_SR_MII_EXT_STS,
+       ETH_SR_MII_TIME_SYNC_ABL,
+       ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR,
+       ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_UPR,
+       ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_LWR,
+       ETH_SR_MII_TIME_SYNC_TX_MIN_DLY_UPR,
+       ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_LWR,
+       ETH_SR_MII_TIME_SYNC_RX_MAX_DLY_UPR,
+       ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_LWR,
+       ETH_SR_MII_TIME_SYNC_RX_MIN_DLY_UPR,
+       ETH_VR_MII_DIG_CTRL1,
+       ETH_VR_MII_AN_CTRL,
+       ETH_VR_MII_AN_INTR_STS,
+       ETH_VR_MII_TC,
+       ETH_VR_MII_DBG_CTRL,
+       ETH_VR_MII_EEE_MCTRL0,
+       ETH_VR_MII_EEE_TXTIMER,
+       ETH_VR_MII_EEE_RXTIMER,
+       ETH_VR_MII_LINK_TIMER_CTRL,
+       ETH_VR_MII_EEE_MCTRL1,
+       ETH_VR_MII_DIG_STS,
+       ETH_VR_MII_ICG_ERRCNT1,
+       ETH_VR_MII_GPIO,
+       ETH_VR_MII_EEE_LPI_STATUS,
+       ETH_VR_MII_EEE_WKERR,
+       ETH_VR_MII_MISC_STS,
+       ETH_VR_MII_RX_LSTS,
+       ETH_VR_MII_GEN2_GEN4_TX_BSTCTRL0,
+       ETH_VR_MII_GEN2_GEN4_TX_LVLCTRL0,
+       ETH_VR_MII_GEN2_GEN4_TXGENCTRL0,
+       ETH_VR_MII_GEN2_GEN4_TXGENCTRL1,
+       ETH_VR_MII_GEN4_TXGENCTRL2,
+       ETH_VR_MII_GEN2_GEN4_TX_STS,
+       ETH_VR_MII_GEN2_GEN4_RXGENCTRL0,
+       ETH_VR_MII_GEN2_GEN4_RXGENCTRL1,
+       ETH_VR_MII_GEN4_RXEQ_CTRL,
+       ETH_VR_MII_GEN4_RXLOS_CTRL0,
+       ETH_VR_MII_GEN2_GEN4_MPLL_CTRL0,
+       ETH_VR_MII_GEN2_GEN4_MPLL_CTRL1,
+       ETH_VR_MII_GEN2_GEN4_MPLL_STS,
+       ETH_VR_MII_GEN2_GEN4_LVL_CTRL,
+       ETH_VR_MII_GEN4_MISC_CTRL2,
+       ETH_VR_MII_GEN2_GEN4_MISC_CTRL0,
+       ETH_VR_MII_GEN2_GEN4_MISC_CTRL1,
+       ETH_VR_MII_SNPS_CR_CTRL,
+       ETH_VR_MII_SNPS_CR_ADDR,
+       ETH_VR_MII_SNPS_CR_DATA,
+       ETH_VR_MII_DIG_CTRL2,
+       ETH_VR_MII_DIG_ERRCNT,
+
+       /* Add new registers above */
+       MAX_LAN743X_ETH_SGMII_REGS
 };
 
 extern const struct ethtool_ops lan743x_ethtool_ops;
diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c
index c0f8ba6..534840f 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_main.c
+++ b/drivers/net/ethernet/microchip/lan743x_main.c
@@ -939,7 +939,7 @@ static int lan743x_sgmii_wait_till_not_busy(struct lan743x_adapter *adapter)
        return ret;
 }
 
-static int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr)
+int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr)
 {
        u32 mmd_access;
        int ret;
diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h
index bc5eea4..8438c3d 100644 (file)
--- a/drivers/net/ethernet/microchip/lan743x_main.h
+++ b/drivers/net/ethernet/microchip/lan743x_main.h
@@ -1161,5 +1161,6 @@ int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout);
 void lan743x_hs_syslock_release(struct lan743x_adapter *adapter);
 void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,
                                       bool tx_enable, bool rx_enable);
+int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr);
 
 #endif /* _LAN743X_H */
Domain: System / Kernel;