These implementations both match the TargetLoweringBase.isZExtFree implementation
return Src == MVT::i32 && Dest == MVT::i64;
}
-bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
- return isZExtFree(Val.getValueType(), VT2);
-}
-
bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
// There aren't really 64-bit registers, but pairs of 32-bit ones and only a
// limited number of native 64-bit operations. Shrinking an operation to fit
bool isZExtFree(Type *Src, Type *Dest) const override;
bool isZExtFree(EVT Src, EVT Dest) const override;
- bool isZExtFree(SDValue Val, EVT VT2) const override;
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
bool LegalOperations, bool ForCodeSize,
return false && VT1 == MVT::i8 && VT2 == MVT::i16;
}
-bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
- return isZExtFree(Val.getValueType(), VT2);
-}
-
//===----------------------------------------------------------------------===//
// Other Lowering Code
//===----------------------------------------------------------------------===//
/// out to 16 bits.
bool isZExtFree(Type *Ty1, Type *Ty2) const override;
bool isZExtFree(EVT VT1, EVT VT2) const override;
- bool isZExtFree(SDValue Val, EVT VT2) const override;
bool isLegalICmpImmediate(int64_t) const override;
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;