static inline bool any_irq_channel_enabled(
const irq_ID_t ID);
-static inline irq_ID_t virq_get_irq_id(
- const virq_id_t irq_ID,
- unsigned int *channel_ID);
+static inline irq_ID_t virq_get_irq_id(const enum virq_id irq_ID,
+ unsigned int *channel_ID);
#ifndef __INLINE_IRQ__
#include "irq_private.h"
IRQ_END_OFFSET
};
-static virq_id_t IRQ_NESTING_ID[N_IRQ_ID] = {
+static enum virq_id IRQ_NESTING_ID[N_IRQ_ID] = {
N_virq_id,
virq_ifmt,
virq_isys,
return;
}
-void irq_controller_get_state(
- const irq_ID_t ID,
- irq_controller_state_t *state)
+void irq_controller_get_state(const irq_ID_t ID,
+ struct irq_controller_state *state)
{
assert(ID < N_IRQ_ID);
assert(state);
}
void cnd_virq_enable_channel(
- const virq_id_t irq_ID,
+ const enum virq_id irq_ID,
const bool en)
{
irq_ID_t i;
return;
}
-enum hrt_isp_css_irq_status virq_get_channel_signals(
- virq_info_t *irq_info)
+enum hrt_isp_css_irq_status
+virq_get_channel_signals(struct virq_info *irq_info)
{
enum hrt_isp_css_irq_status irq_status = hrt_isp_css_irq_status_error;
irq_ID_t ID;
return irq_status;
}
-void virq_clear_info(
- virq_info_t *irq_info)
+void virq_clear_info(struct virq_info *irq_info)
{
irq_ID_t ID;
}
enum hrt_isp_css_irq_status virq_get_channel_id(
- virq_id_t *irq_id)
+ enum virq_id *irq_id)
{
unsigned int irq_status = irq_reg_load(IRQ0_ID,
_HRT_IRQ_CONTROLLER_STATUS_REG_IDX);
/* Check whether we have an IRQ on one of the nested devices */
for (ID = N_IRQ_ID - 1 ; ID > (irq_ID_t)0; ID--) {
- if (IRQ_NESTING_ID[ID] == (virq_id_t)idx) {
+ if (IRQ_NESTING_ID[ID] == (enum virq_id)idx) {
break;
}
}
idx += IRQ_N_ID_OFFSET[ID];
if (irq_id)
- *irq_id = (virq_id_t)idx;
+ *irq_id = (enum virq_id)idx;
return status;
}
}
static inline irq_ID_t virq_get_irq_id(
- const virq_id_t irq_ID,
+ const enum virq_id irq_ID,
unsigned int *channel_ID)
{
irq_ID_t ID;
#define IRQ2_ID_N_CHANNEL HIVE_ISYS_IRQ_NUM_BITS
#define IRQ3_ID_N_CHANNEL HIVE_ISEL_IRQ_NUM_IRQS
-typedef struct virq_info_s virq_info_t;
-typedef struct irq_controller_state_s irq_controller_state_t;
-
-typedef enum {
+enum virq_id {
virq_gpio_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID,
virq_gpio_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID,
virq_gpio_pin_2 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID,
virq_sp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID,
virq_isp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID,
virq_mod_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID,
-#if defined(IS_ISP_2400_MAMOIADA_SYSTEM)
virq_isp_pmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID,
-#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM)
- virq_isys_2401 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID,
-#else
-#error "irq_local.h: 2400_SYSTEM must be one of {2400, 2401 }"
-#endif
virq_isp_bamem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID,
virq_isp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID,
virq_sp_icache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID,
virq_isel_eol = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID,
N_virq_id = IRQ_END_OFFSET
-} virq_id_t;
+};
-struct virq_info_s {
+struct virq_info {
hrt_data irq_status_reg[N_IRQ_ID];
};
-struct irq_controller_state_s {
+struct irq_controller_state {
unsigned int irq_edge;
unsigned int irq_mask;
unsigned int irq_status;
\return none, state = IRQ[ID].state
*/
-void irq_controller_get_state(
- const irq_ID_t ID,
- irq_controller_state_t *state);
+void irq_controller_get_state(const irq_ID_t ID,
+ struct irq_controller_state *state);
/*! Write to a control register of IRQ[ID]
\return none, VIRQ.channel[irq_ID].enable = en
*/
void cnd_virq_enable_channel(
- const virq_id_t irq_ID,
+ const enum virq_id irq_ID,
const bool en);
/*! Clear the state of all IRQ channels of the virtual super IRQ
\return none
*/
-void virq_clear_info(
- virq_info_t *irq_info);
+void virq_clear_info(struct virq_info *irq_info);
/*! Return the ID of a signalling IRQ channel of the virtual super IRQ
\return state(IRQ[...])
*/
enum hrt_isp_css_irq_status virq_get_channel_id(
- virq_id_t *irq_id);
+ enum virq_id *irq_id);
/*! Return the IDs of all signaling IRQ channels of the virtual super IRQ
\return (error(state(IRQ[...]))
*/
-enum hrt_isp_css_irq_status virq_get_channel_signals(
- virq_info_t *irq_info);
+enum hrt_isp_css_irq_status
+virq_get_channel_signals(struct virq_info *irq_info);
#endif /* __IRQ_PUBLIC_H_INCLUDED__ */
ia_css_debug_dump_isys_state();
{
- irq_controller_state_t state;
+ struct irq_controller_state state;
irq_controller_get_state(IRQ2_ID, &state);
/* Enable SW interrupt 0, this is used to signal ISYS events */
cnd_virq_enable_channel(
- (virq_id_t)(IRQ_SW_CHANNEL0_ID + IRQ_SW_CHANNEL_OFFSET),
+ (enum virq_id)(IRQ_SW_CHANNEL0_ID + IRQ_SW_CHANNEL_OFFSET),
true);
/* Enable SW interrupt 1, this is used to signal PSYS events */
cnd_virq_enable_channel(
- (virq_id_t)(IRQ_SW_CHANNEL1_ID + IRQ_SW_CHANNEL_OFFSET),
+ (enum virq_id)(IRQ_SW_CHANNEL1_ID + IRQ_SW_CHANNEL_OFFSET),
true);
#if !defined(HAS_IRQ_MAP_VERSION_2)
/* IRQ_SW_CHANNEL2_ID does not exist on 240x systems */
cnd_virq_enable_channel(
- (virq_id_t)(IRQ_SW_CHANNEL2_ID + IRQ_SW_CHANNEL_OFFSET),
+ (enum virq_id)(IRQ_SW_CHANNEL2_ID + IRQ_SW_CHANNEL_OFFSET),
true);
virq_clear_all();
#endif
int ia_css_irq_translate(
unsigned int *irq_infos)
{
- virq_id_t irq;
+ enum virq_id irq;
enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_more_irqs;
unsigned int infos = 0;
enum ia_css_irq_info info,
bool enable)
{
- virq_id_t irq = N_virq_id;
+ enum virq_id irq = N_virq_id;
IA_CSS_ENTER("info=%d, enable=%d", info, enable);