+2006-12-06 H.J. Lu <hjl@gnu.org>
+
+ * config/tc-i386.h: Change the prefix order to SEG_PREFIX,
+ ADDR_PREFIX, DATA_PREFIX, LOCKREP_PREFIX.
+
2006-12-02 Jakub Jelinek <jakub@redhat.com>
PR gas/3607
/* Prefixes will be emitted in the order defined below.
WAIT_PREFIX must be the first prefix since FWAIT is really is an
- instruction, and so must come before any prefixes. */
+ instruction, and so must come before any prefixes.
+ The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
+ LOCKREP_PREFIX. */
#define WAIT_PREFIX 0
-#define LOCKREP_PREFIX 1
+#define SEG_PREFIX 1
#define ADDR_PREFIX 2
#define DATA_PREFIX 3
-#define SEG_PREFIX 4
+#define LOCKREP_PREFIX 4
#define REX_PREFIX 5 /* must come last. */
#define MAX_PREFIXES 6 /* max prefixes per opcode */
+2006-12-06 H.J. Lu <hjl@gnu.org>
+
+ * gas/i386/amdfam10.d: Updated for operand/address-size override
+ prefix position change.
+ * gas/i386/naked.d: Likewise.
+ * gas/i386/rep-suffix.d: Likewise.
+ * gas/i386/rep.d: Likewise.
+ * gas/i386/white.l: Likewise.
+ * gas/i386/x86-64-amdfam10.d: Likewise.
+ * gas/i386/x86-64-rep-suffix.d: Likewise.
+ * gas/i386/x86-64-rep.d: Likewise.
+ * gas/i386/x86_64.d: Likewise.
+
2006-12-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/opcode-intel.d: Fix wrong expectation. Make white space
0+000 <foo>:
0: f3 0f bd 19[ ]+lzcnt \(%ecx\),%ebx
- 4: f3 66 0f bd 19[ ]+lzcnt \(%ecx\),%bx
+ 4: 66 f3 0f bd 19[ ]+lzcnt \(%ecx\),%bx
9: f3 0f bd d9[ ]+lzcnt %ecx,%ebx
- d: f3 66 0f bd d9[ ]+lzcnt %cx,%bx
+ d: 66 f3 0f bd d9[ ]+lzcnt %cx,%bx
12: f3 0f b8 19[ ]+popcnt \(%ecx\),%ebx
- 16: f3 66 0f b8 19[ ]+popcnt \(%ecx\),%bx
+ 16: 66 f3 0f b8 19[ ]+popcnt \(%ecx\),%bx
1b: f3 0f b8 d9[ ]+popcnt %ecx,%ebx
- 1f: f3 66 0f b8 d9[ ]+popcnt %cx,%bx
+ 1f: 66 f3 0f b8 d9[ ]+popcnt %cx,%bx
24: 66 0f 79 ca[ ]+extrq %xmm2,%xmm1
28: 66 0f 78 c1 02 04[ ]*extrq \$0x4,\$0x2,%xmm1
2e: f2 0f 79 ca[ ]+insertq %xmm2,%xmm1
Disassembly of section .text:
0+000 <foo>:
- 0: 66 26 ff 23 [ ]*jmpw \*%es:\(%ebx\)
+ 0: 26 66 ff 23 [ ]*jmpw \*%es:\(%ebx\)
4: 8a 25 50 00 00 00 [ ]*mov 0x50,%ah
a: b2 20 [ ]*mov \$0x20,%dl
c: bb 00 00 00 00 [ ]*mov \$0x0,%ebx d: (R_386_)?(dir)?32 .text
1b: 8c 2c ed 00 00 00 00 [ ]*mov %gs,0x0\(,%ebp,8\)
22: 26 88 25 00 00 00 00 [ ]*mov %ah,%es:0x0
29: 2e 8b 74 14 80 [ ]*mov %cs:0xffffff80\(%esp,%edx,1\),%esi
- 2e: f3 65 a5 [ ]*rep movsl %gs:\(%esi\),%es:\(%edi\)
+ 2e: 65 f3 a5 [ ]*rep movsl %gs:\(%esi\),%es:\(%edi\)
31: ec [ ]*in \(%dx\),%al
32: 66 ef [ ]*out %ax,\(%dx\)
34: 67 d2 14 [ ]*addr16 rclb %cl,\(%si\)
Disassembly of section .text:
0+000 <foo>:
- 0: 9b 67 26 d9 3c [ ]*addr16 fstcw %es:\(%si\)
+ 0: 9b 26 67 d9 3c [ ]*addr16 fstcw %es:\(%si\)
5: 9b df e0 [ ]*fstsw %ax
8: 9b df e0 [ ]*fstsw %ax
b: 9b df e0 [ ]*fstsw %ax
e: 9b 67 df e0 [ ]*addr16 fstsw %ax
- 12: f3 67 66 36 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
+ 12: 36 67 66 f3 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
#pass
0+000 <_start>:
0: f3 ac[ ]+rep lodsb %ds:\(%esi\),%al
2: f3 aa[ ]+rep stosb %al,%es:\(%edi\)
- 4: f3 66 ad[ ]+rep lodsw %ds:\(%esi\),%ax
- 7: f3 66 ab[ ]+rep stosw %ax,%es:\(%edi\)
+ 4: 66 f3 ad[ ]+rep lodsw %ds:\(%esi\),%ax
+ 7: 66 f3 ab[ ]+rep stosw %ax,%es:\(%edi\)
a: f3 ad[ ]+rep lodsl %ds:\(%esi\),%eax
c: f3 ab[ ]+rep stosl %eax,%es:\(%edi\)
#pass
8: f3 aa[ ]+rep stos %al,%es:\(%edi\)
a: f3 a6[ ]+repz cmpsb %es:\(%edi\),%ds:\(%esi\)
c: f3 ae[ ]+repz scas %es:\(%edi\),%al
- e: f3 66 6d[ ]+rep insw \(%dx\),%es:\(%edi\)
- 11: f3 66 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\)
- 14: f3 66 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\)
- 17: f3 66 ad[ ]+rep lods %ds:\(%esi\),%ax
- 1a: f3 66 ab[ ]+rep stos %ax,%es:\(%edi\)
- 1d: f3 66 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\)
- 20: f3 66 af[ ]+repz scas %es:\(%edi\),%ax
+ e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%edi\)
+ 11: 66 f3 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\)
+ 14: 66 f3 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\)
+ 17: 66 f3 ad[ ]+rep lods %ds:\(%esi\),%ax
+ 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%edi\)
+ 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\)
+ 20: 66 f3 af[ ]+repz scas %es:\(%edi\),%ax
23: f3 6d[ ]+rep insl \(%dx\),%es:\(%edi\)
25: f3 6f[ ]+rep outsl %ds:\(%esi\),\(%dx\)
27: f3 a5[ ]+rep movsl %ds:\(%esi\),%es:\(%edi\)
2b: f3 ab[ ]+rep stos %eax,%es:\(%edi\)
2d: f3 a7[ ]+repz cmpsl %es:\(%edi\),%ds:\(%esi\)
2f: f3 af[ ]+repz scas %es:\(%edi\),%eax
- 31: f3 67 6c[ ]+rep addr16 insb \(%dx\),%es:\(%di\)
- 34: f3 67 6e[ ]+rep addr16 outsb %ds:\(%si\),\(%dx\)
- 37: f3 67 a4[ ]+rep addr16 movsb %ds:\(%si\),%es:\(%di\)
- 3a: f3 67 ac[ ]+rep addr16 lods %ds:\(%si\),%al
- 3d: f3 67 aa[ ]+rep addr16 stos %al,%es:\(%di\)
- 40: f3 67 a6[ ]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\)
- 43: f3 67 ae[ ]+repz addr16 scas %es:\(%di\),%al
- 46: f3 67 66 6d[ ]+rep addr16 insw \(%dx\),%es:\(%di\)
- 4a: f3 67 66 6f[ ]+rep addr16 outsw %ds:\(%si\),\(%dx\)
- 4e: f3 67 66 a5[ ]+rep addr16 movsw %ds:\(%si\),%es:\(%di\)
- 52: f3 67 66 ad[ ]+rep addr16 lods %ds:\(%si\),%ax
- 56: f3 67 66 ab[ ]+rep addr16 stos %ax,%es:\(%di\)
- 5a: f3 67 66 a7[ ]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\)
- 5e: f3 67 66 af[ ]+repz addr16 scas %es:\(%di\),%ax
- 62: f3 67 6d[ ]+rep addr16 insl \(%dx\),%es:\(%di\)
- 65: f3 67 6f[ ]+rep addr16 outsl %ds:\(%si\),\(%dx\)
- 68: f3 67 a5[ ]+rep addr16 movsl %ds:\(%si\),%es:\(%di\)
- 6b: f3 67 ad[ ]+rep addr16 lods %ds:\(%si\),%eax
- 6e: f3 67 ab[ ]+rep addr16 stos %eax,%es:\(%di\)
- 71: f3 67 a7[ ]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\)
- 74: f3 67 af[ ]+repz addr16 scas %es:\(%di\),%eax
+ 31: 67 f3 6c[ ]+rep addr16 insb \(%dx\),%es:\(%di\)
+ 34: 67 f3 6e[ ]+rep addr16 outsb %ds:\(%si\),\(%dx\)
+ 37: 67 f3 a4[ ]+rep addr16 movsb %ds:\(%si\),%es:\(%di\)
+ 3a: 67 f3 ac[ ]+rep addr16 lods %ds:\(%si\),%al
+ 3d: 67 f3 aa[ ]+rep addr16 stos %al,%es:\(%di\)
+ 40: 67 f3 a6[ ]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\)
+ 43: 67 f3 ae[ ]+repz addr16 scas %es:\(%di\),%al
+ 46: 67 66 f3 6d[ ]+rep addr16 insw \(%dx\),%es:\(%di\)
+ 4a: 67 66 f3 6f[ ]+rep addr16 outsw %ds:\(%si\),\(%dx\)
+ 4e: 67 66 f3 a5[ ]+rep addr16 movsw %ds:\(%si\),%es:\(%di\)
+ 52: 67 66 f3 ad[ ]+rep addr16 lods %ds:\(%si\),%ax
+ 56: 67 66 f3 ab[ ]+rep addr16 stos %ax,%es:\(%di\)
+ 5a: 67 66 f3 a7[ ]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\)
+ 5e: 67 66 f3 af[ ]+repz addr16 scas %es:\(%di\),%ax
+ 62: 67 f3 6d[ ]+rep addr16 insl \(%dx\),%es:\(%di\)
+ 65: 67 f3 6f[ ]+rep addr16 outsl %ds:\(%si\),\(%dx\)
+ 68: 67 f3 a5[ ]+rep addr16 movsl %ds:\(%si\),%es:\(%di\)
+ 6b: 67 f3 ad[ ]+rep addr16 lods %ds:\(%si\),%eax
+ 6e: 67 f3 ab[ ]+rep addr16 stos %eax,%es:\(%di\)
+ 71: 67 f3 a7[ ]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\)
+ 74: 67 f3 af[ ]+repz addr16 scas %es:\(%di\),%eax
...
5 0003 C705D711 00007B00 0000 mOvl \$ 123 , 4567
6 000d 678A787B ADDr16 mov 123 \( % bx , % si , 1 \) , % bh
7 0011 FFE0 jmp \* % eax
- 8 0013 6626FF23 foo: jmpw % es : \* \( % ebx \)
+ 8 0013 2666FF23 foo: jmpw % es : \* \( % ebx \)
9
10 0017 A0500000 00 mov \( 0x8 \* 0Xa \) , % al
11 001c B020 mov \$ \( 8 \* 4 \) , % al
0+000 <foo>:
0: f3 48 0f bd 19[ ]+lzcnt \(%rcx\),%rbx
5: f3 0f bd 19[ ]+lzcnt \(%rcx\),%ebx
- 9: f3 66 0f bd 19[ ]+lzcnt \(%rcx\),%bx
+ 9: 66 f3 0f bd 19[ ]+lzcnt \(%rcx\),%bx
e: f3 48 0f bd d9[ ]+lzcnt %rcx,%rbx
13: f3 0f bd d9[ ]+lzcnt %ecx,%ebx
- 17: f3 66 0f bd d9[ ]+lzcnt %cx,%bx
+ 17: 66 f3 0f bd d9[ ]+lzcnt %cx,%bx
1c: f3 48 0f b8 19[ ]+popcnt \(%rcx\),%rbx
21: f3 0f b8 19[ ]+popcnt \(%rcx\),%ebx
- 25: f3 66 0f b8 19[ ]+popcnt \(%rcx\),%bx
+ 25: 66 f3 0f b8 19[ ]+popcnt \(%rcx\),%bx
2a: f3 48 0f b8 d9[ ]+popcnt %rcx,%rbx
2f: f3 0f b8 d9[ ]+popcnt %ecx,%ebx
- 33: f3 66 0f b8 d9[ ]+popcnt %cx,%bx
+ 33: 66 f3 0f b8 d9[ ]+popcnt %cx,%bx
38: 66 0f 79 ca[ ]+extrq %xmm2,%xmm1
3c: 66 0f 78 c1 02 04[ ]+extrq \$0x4,\$0x2,%xmm1
42: f2 0f 79 ca[ ]+insertq %xmm2,%xmm1
0+000 <_start>:
0: f3 ac[ ]+rep lodsb %ds:\(%rsi\),%al
2: f3 aa[ ]+rep stosb %al,%es:\(%rdi\)
- 4: f3 66 ad[ ]+rep lodsw %ds:\(%rsi\),%ax
- 7: f3 66 ab[ ]+rep stosw %ax,%es:\(%rdi\)
+ 4: 66 f3 ad[ ]+rep lodsw %ds:\(%rsi\),%ax
+ 7: 66 f3 ab[ ]+rep stosw %ax,%es:\(%rdi\)
a: f3 ad[ ]+rep lodsl %ds:\(%rsi\),%eax
c: f3 ab[ ]+rep stosl %eax,%es:\(%rdi\)
e: f3 48 ad[ ]+rep lodsq %ds:\(%rsi\),%rax
8: f3 aa[ ]+rep stos %al,%es:\(%rdi\)
a: f3 a6[ ]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\)
c: f3 ae[ ]+repz scas %es:\(%rdi\),%al
- e: f3 66 6d[ ]+rep insw \(%dx\),%es:\(%rdi\)
- 11: f3 66 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\)
- 14: f3 66 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
- 17: f3 66 ad[ ]+rep lods %ds:\(%rsi\),%ax
- 1a: f3 66 ab[ ]+rep stos %ax,%es:\(%rdi\)
- 1d: f3 66 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\)
- 20: f3 66 af[ ]+repz scas %es:\(%rdi\),%ax
+ e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%rdi\)
+ 11: 66 f3 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\)
+ 14: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+ 17: 66 f3 ad[ ]+rep lods %ds:\(%rsi\),%ax
+ 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%rdi\)
+ 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\)
+ 20: 66 f3 af[ ]+repz scas %es:\(%rdi\),%ax
23: f3 6d[ ]+rep insl \(%dx\),%es:\(%rdi\)
25: f3 6f[ ]+rep outsl %ds:\(%rsi\),\(%dx\)
27: f3 a5[ ]+rep movsl %ds:\(%rsi\),%es:\(%rdi\)
37: f3 48 ab[ ]+rep stos %rax,%es:\(%rdi\)
3a: f3 48 a7[ ]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\)
3d: f3 48 af[ ]+repz scas %es:\(%rdi\),%rax
- 40: f3 67 6c[ ]+rep addr32 insb \(%dx\),%es:\(%edi\)
- 43: f3 67 6e[ ]+rep addr32 outsb %ds:\(%esi\),\(%dx\)
- 46: f3 67 a4[ ]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\)
- 49: f3 67 ac[ ]+rep addr32 lods %ds:\(%esi\),%al
- 4c: f3 67 aa[ ]+rep addr32 stos %al,%es:\(%edi\)
- 4f: f3 67 a6[ ]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\)
- 52: f3 67 ae[ ]+repz addr32 scas %es:\(%edi\),%al
- 55: f3 67 66 6d[ ]+rep addr32 insw \(%dx\),%es:\(%edi\)
- 59: f3 67 66 6f[ ]+rep addr32 outsw %ds:\(%esi\),\(%dx\)
- 5d: f3 67 66 a5[ ]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\)
- 61: f3 67 66 ad[ ]+rep addr32 lods %ds:\(%esi\),%ax
- 65: f3 67 66 ab[ ]+rep addr32 stos %ax,%es:\(%edi\)
- 69: f3 67 66 a7[ ]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\)
- 6d: f3 67 66 af[ ]+repz addr32 scas %es:\(%edi\),%ax
- 71: f3 67 6d[ ]+rep addr32 insl \(%dx\),%es:\(%edi\)
- 74: f3 67 6f[ ]+rep addr32 outsl %ds:\(%esi\),\(%dx\)
- 77: f3 67 a5[ ]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\)
- 7a: f3 67 ad[ ]+rep addr32 lods %ds:\(%esi\),%eax
- 7d: f3 67 ab[ ]+rep addr32 stos %eax,%es:\(%edi\)
- 80: f3 67 a7[ ]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\)
- 83: f3 67 af[ ]+repz addr32 scas %es:\(%edi\),%eax
- 86: f3 67 48 a5[ ]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\)
- 8a: f3 67 48 ad[ ]+rep addr32 lods %ds:\(%esi\),%rax
- 8e: f3 67 48 ab[ ]+rep addr32 stos %rax,%es:\(%edi\)
- 92: f3 67 48 a7[ ]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\)
- 96: f3 67 48 af[ ]+repz addr32 scas %es:\(%edi\),%rax
+ 40: 67 f3 6c[ ]+rep addr32 insb \(%dx\),%es:\(%edi\)
+ 43: 67 f3 6e[ ]+rep addr32 outsb %ds:\(%esi\),\(%dx\)
+ 46: 67 f3 a4[ ]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\)
+ 49: 67 f3 ac[ ]+rep addr32 lods %ds:\(%esi\),%al
+ 4c: 67 f3 aa[ ]+rep addr32 stos %al,%es:\(%edi\)
+ 4f: 67 f3 a6[ ]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\)
+ 52: 67 f3 ae[ ]+repz addr32 scas %es:\(%edi\),%al
+ 55: 67 66 f3 6d[ ]+rep addr32 insw \(%dx\),%es:\(%edi\)
+ 59: 67 66 f3 6f[ ]+rep addr32 outsw %ds:\(%esi\),\(%dx\)
+ 5d: 67 66 f3 a5[ ]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\)
+ 61: 67 66 f3 ad[ ]+rep addr32 lods %ds:\(%esi\),%ax
+ 65: 67 66 f3 ab[ ]+rep addr32 stos %ax,%es:\(%edi\)
+ 69: 67 66 f3 a7[ ]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\)
+ 6d: 67 66 f3 af[ ]+repz addr32 scas %es:\(%edi\),%ax
+ 71: 67 f3 6d[ ]+rep addr32 insl \(%dx\),%es:\(%edi\)
+ 74: 67 f3 6f[ ]+rep addr32 outsl %ds:\(%esi\),\(%dx\)
+ 77: 67 f3 a5[ ]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\)
+ 7a: 67 f3 ad[ ]+rep addr32 lods %ds:\(%esi\),%eax
+ 7d: 67 f3 ab[ ]+rep addr32 stos %eax,%es:\(%edi\)
+ 80: 67 f3 a7[ ]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\)
+ 83: 67 f3 af[ ]+repz addr32 scas %es:\(%edi\),%eax
+ 86: 67 f3 48 a5[ ]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\)
+ 8a: 67 f3 48 ad[ ]+rep addr32 lods %ds:\(%esi\),%rax
+ 8e: 67 f3 48 ab[ ]+rep addr32 stos %rax,%es:\(%edi\)
+ 92: 67 f3 48 a7[ ]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\)
+ 96: 67 f3 48 af[ ]+repz addr32 scas %es:\(%edi\),%rax
#pass
[ ]+5a: 44 0f 20 c0[ ]+mov[ ]+%cr8,%rax
[ ]+5e: 44 0f 22 c0[ ]+mov[ ]+%rax,%cr8
[ ]+62: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
-[ ]+65: f3 66 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+[ ]+65: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
[ ]+68: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
[ ]+6b: b0 11[ ]+mov[ ]+\$0x11,%al
[ ]+6d: b4 11[ ]+mov[ ]+\$0x11,%ah
projects / platform / upstream / binutils.git / commitdiff