static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
{
- unsigned long timeout = jiffies + HZ;
- unsigned int offset;
- u32 mask, val;
+ u32 mask, val, offset, reg_offset;
+ void __iomem *addr;
+ int err;
if (i2c_dev->hw->has_mst_fifo) {
mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
val |= mask;
i2c_writel(i2c_dev, val, offset);
- while (i2c_readl(i2c_dev, offset) & mask) {
- if (time_after(jiffies, timeout)) {
- dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
- return -ETIMEDOUT;
- }
- usleep_range(1000, 2000);
+ reg_offset = tegra_i2c_reg_addr(i2c_dev, offset);
+ addr = i2c_dev->base + reg_offset;
+
+ if (i2c_dev->is_curr_atomic_xfer)
+ err = readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
+ 1000, 1000000);
+ else
+ err = readl_relaxed_poll_timeout(addr, val, !(val & mask),
+ 1000, 1000000);
+
+ if (err) {
+ dev_err(i2c_dev->dev, "failed to flush FIFO\n");
+ return err;
}
return 0;
}