2001-10-17 Chris Demetriou <cgd@broadcom.com>

       * mips.h: Sort coprocessor instruction argument characters
       in comment, add a few more words of description for "H".

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index cb547e3..8bcb7fc 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,5 +1,10 @@
 2001-10-17  Chris Demetriou  <cgd@broadcom.com>
 
+       * mips.h: Sort coprocessor instruction argument characters
+       in comment, add a few more words of description for "H".
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
        * mips.h (INSN_SB1): New cpu-specific instruction bit.
        (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
        if cpu is CPU_SB1.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index b7a0fed..8c24c85 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -209,8 +209,8 @@ struct mips_opcode
    Coprocessor instructions:
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
+   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
-   "H" 3 bit sel field (OP_*_SEL)
 
    Macro instructions:
    "A" General 32 bit expression