#include <plat/omap_device.h>
#include <linux/pm_runtime.h>
-#include "control.h"
-
/*
* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
-/* McBSP1 internal signal muxing function for OMAP2/3 */
-static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
- const char *src)
-{
- u32 v;
-
- v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-
- if (!strcmp(signal, "clkr")) {
- if (!strcmp(src, "clkr"))
- v &= ~OMAP2_MCBSP1_CLKR_MASK;
- else if (!strcmp(src, "clkx"))
- v |= OMAP2_MCBSP1_CLKR_MASK;
- else
- return -EINVAL;
- } else if (!strcmp(signal, "fsr")) {
- if (!strcmp(src, "fsr"))
- v &= ~OMAP2_MCBSP1_FSR_MASK;
- else if (!strcmp(src, "fsx"))
- v |= OMAP2_MCBSP1_FSR_MASK;
- else
- return -EINVAL;
- } else {
- return -EINVAL;
- }
-
- omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-
- return 0;
-}
-
-/* McBSP4 internal signal muxing function for OMAP4 */
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
-#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
-static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
- const char *src)
-{
- u32 v;
-
- /*
- * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
- * mux) is used */
- v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
- if (!strcmp(signal, "clkr")) {
- if (!strcmp(src, "clkr"))
- v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
- else if (!strcmp(src, "clkx"))
- v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
- else
- return -EINVAL;
- } else if (!strcmp(signal, "fsr")) {
- if (!strcmp(src, "fsr"))
- v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
- else if (!strcmp(src, "fsx"))
- v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
- else
- return -EINVAL;
- } else {
- return -EINVAL;
- }
-
- omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
-
- return 0;
-}
-
static int omap3_enable_st_clock(unsigned int id, bool enable)
{
unsigned int w;
pdata->has_ccr = true;
}
- /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
- if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
- pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
-
- /* On OMAP4 the McBSP4 port has 6 pin configuration */
- if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
- pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
-
if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
/* The FIFO has 128 locations */
pdata->buffer_size = 0x80;
return -EBUSY;
}
- if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
- clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
- clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
- clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
- clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
- mcbsp->in_freq = freq;
- regs->srgr2 &= ~CLKSM;
- regs->pcr0 &= ~SCLKME;
- } else if (cpu_class_is_omap1()) {
- /*
- * McBSP CLKR/FSR signal muxing functions are only available on
- * OMAP2 or newer versions
- */
- return -EINVAL;
- }
+ mcbsp->in_freq = freq;
+ regs->srgr2 &= ~CLKSM;
+ regs->pcr0 &= ~SCLKME;
switch (clk_id) {
case OMAP_MCBSP_SYSCLK_CLK:
case OMAP_MCBSP_SYSCLK_CLKR_EXT:
regs->pcr0 |= SCLKME;
break;
-
-
- case OMAP_MCBSP_CLKR_SRC_CLKR:
- err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
- break;
- case OMAP_MCBSP_CLKR_SRC_CLKX:
- err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
- break;
- case OMAP_MCBSP_FSR_SRC_FSR:
- err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
- break;
- case OMAP_MCBSP_FSR_SRC_FSX:
- err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
- break;
default:
err = -ENODEV;
}