dt-bindings: clk: axg-clkc: expose all clock ids

Due to a policy change in clock ID bindings handling, expose
all the "private" clock IDs to the public clock dt-bindings
to move out of the previous maintenance scheme.

This refers to a discussion at [1] & [2] with Krzysztof about
the issue with the current maintenance.

It was decided to move every axg-clkc ID to the public clock
dt-bindings headers to be merged in a single tree so we
can safely add new clocks without having merge issues.

[1] https://lore.kernel.org/all/c088e01c-0714-82be-8347-6140daf56640@linaro.org/
[2] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 39f9e2d..ed15753 100644 (file)
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -102,64 +102,6 @@
 #define HHI_DPLL_TOP_I                 0x318
 #define HHI_DPLL_TOP2_I                        0x31C
 
-/*
- * CLKID index values
- *
- * These indices are entirely contrived and do not map onto the hardware.
- * It has now been decided to expose everything by default in the DT header:
- * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
- * to expose, such as the internal muxes and dividers of composite clocks,
- * will remain defined here.
- */
-#define CLKID_MPEG_SEL                         8
-#define CLKID_MPEG_DIV                         9
-#define CLKID_SD_EMMC_B_CLK0_SEL               61
-#define CLKID_SD_EMMC_B_CLK0_DIV               62
-#define CLKID_SD_EMMC_C_CLK0_SEL               63
-#define CLKID_SD_EMMC_C_CLK0_DIV               64
-#define CLKID_MPLL0_DIV                                65
-#define CLKID_MPLL1_DIV                                66
-#define CLKID_MPLL2_DIV                                67
-#define CLKID_MPLL3_DIV                                68
-#define CLKID_MPLL_PREDIV                      70
-#define CLKID_FCLK_DIV2_DIV                    71
-#define CLKID_FCLK_DIV3_DIV                    72
-#define CLKID_FCLK_DIV4_DIV                    73
-#define CLKID_FCLK_DIV5_DIV                    74
-#define CLKID_FCLK_DIV7_DIV                    75
-#define CLKID_PCIE_PLL                         76
-#define CLKID_PCIE_MUX                         77
-#define CLKID_PCIE_REF                         78
-#define CLKID_GEN_CLK_SEL                      82
-#define CLKID_GEN_CLK_DIV                      83
-#define CLKID_SYS_PLL_DCO                      85
-#define CLKID_FIXED_PLL_DCO                    86
-#define CLKID_GP0_PLL_DCO                      87
-#define CLKID_HIFI_PLL_DCO                     88
-#define CLKID_PCIE_PLL_DCO                     89
-#define CLKID_PCIE_PLL_OD                      90
-#define CLKID_VPU_0_DIV                                91
-#define CLKID_VPU_1_DIV                                94
-#define CLKID_VAPB_0_DIV                       98
-#define CLKID_VAPB_1_DIV                       101
-#define CLKID_VCLK_SEL                         108
-#define CLKID_VCLK2_SEL                                109
-#define CLKID_VCLK_INPUT                       110
-#define CLKID_VCLK2_INPUT                      111
-#define CLKID_VCLK_DIV                         112
-#define CLKID_VCLK2_DIV                                113
-#define CLKID_VCLK_DIV2_EN                     114
-#define CLKID_VCLK_DIV4_EN                     115
-#define CLKID_VCLK_DIV6_EN                     116
-#define CLKID_VCLK_DIV12_EN                    117
-#define CLKID_VCLK2_DIV2_EN                    118
-#define CLKID_VCLK2_DIV4_EN                    119
-#define CLKID_VCLK2_DIV6_EN                    120
-#define CLKID_VCLK2_DIV12_EN                   121
-#define CLKID_CTS_ENCL_SEL                     132
-#define CLKID_VDIN_MEAS_SEL                    134
-#define CLKID_VDIN_MEAS_DIV                    135
-
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/axg-clkc.h>
 

diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 93752ea..4421628 100644 (file)
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -16,6 +16,8 @@
 #define CLKID_FCLK_DIV5                                5
 #define CLKID_FCLK_DIV7                                6
 #define CLKID_GP0_PLL                          7
+#define CLKID_MPEG_SEL                         8
+#define CLKID_MPEG_DIV                         9
 #define CLKID_CLK81                            10
 #define CLKID_MPLL0                            11
 #define CLKID_MPLL1                            12
@@ -67,23 +69,66 @@
 #define CLKID_AO_I2C                           58
 #define CLKID_SD_EMMC_B_CLK0                   59
 #define CLKID_SD_EMMC_C_CLK0                   60
+#define CLKID_SD_EMMC_B_CLK0_SEL               61
+#define CLKID_SD_EMMC_B_CLK0_DIV               62
+#define CLKID_SD_EMMC_C_CLK0_SEL               63
+#define CLKID_SD_EMMC_C_CLK0_DIV               64
+#define CLKID_MPLL0_DIV                                65
+#define CLKID_MPLL1_DIV                                66
+#define CLKID_MPLL2_DIV                                67
+#define CLKID_MPLL3_DIV                                68
 #define CLKID_HIFI_PLL                         69
+#define CLKID_MPLL_PREDIV                      70
+#define CLKID_FCLK_DIV2_DIV                    71
+#define CLKID_FCLK_DIV3_DIV                    72
+#define CLKID_FCLK_DIV4_DIV                    73
+#define CLKID_FCLK_DIV5_DIV                    74
+#define CLKID_FCLK_DIV7_DIV                    75
+#define CLKID_PCIE_PLL                         76
+#define CLKID_PCIE_MUX                         77
+#define CLKID_PCIE_REF                         78
 #define CLKID_PCIE_CML_EN0                     79
 #define CLKID_PCIE_CML_EN1                     80
+#define CLKID_GEN_CLK_SEL                      82
+#define CLKID_GEN_CLK_DIV                      83
 #define CLKID_GEN_CLK                          84
+#define CLKID_SYS_PLL_DCO                      85
+#define CLKID_FIXED_PLL_DCO                    86
+#define CLKID_GP0_PLL_DCO                      87
+#define CLKID_HIFI_PLL_DCO                     88
+#define CLKID_PCIE_PLL_DCO                     89
+#define CLKID_PCIE_PLL_OD                      90
+#define CLKID_VPU_0_DIV                                91
 #define CLKID_VPU_0_SEL                                92
 #define CLKID_VPU_0                            93
+#define CLKID_VPU_1_DIV                                94
 #define CLKID_VPU_1_SEL                                95
 #define CLKID_VPU_1                            96
 #define CLKID_VPU                              97
+#define CLKID_VAPB_0_DIV                       98
 #define CLKID_VAPB_0_SEL                       99
 #define CLKID_VAPB_0                           100
+#define CLKID_VAPB_1_DIV                       101
 #define CLKID_VAPB_1_SEL                       102
 #define CLKID_VAPB_1                           103
 #define CLKID_VAPB_SEL                         104
 #define CLKID_VAPB                             105
 #define CLKID_VCLK                             106
 #define CLKID_VCLK2                            107
+#define CLKID_VCLK_SEL                         108
+#define CLKID_VCLK2_SEL                                109
+#define CLKID_VCLK_INPUT                       110
+#define CLKID_VCLK2_INPUT                      111
+#define CLKID_VCLK_DIV                         112
+#define CLKID_VCLK2_DIV                                113
+#define CLKID_VCLK_DIV2_EN                     114
+#define CLKID_VCLK_DIV4_EN                     115
+#define CLKID_VCLK_DIV6_EN                     116
+#define CLKID_VCLK_DIV12_EN                    117
+#define CLKID_VCLK2_DIV2_EN                    118
+#define CLKID_VCLK2_DIV4_EN                    119
+#define CLKID_VCLK2_DIV6_EN                    120
+#define CLKID_VCLK2_DIV12_EN                   121
 #define CLKID_VCLK_DIV1                                122
 #define CLKID_VCLK_DIV2                                123
 #define CLKID_VCLK_DIV4                                124
@@ -94,7 +139,10 @@
 #define CLKID_VCLK2_DIV4                       129
 #define CLKID_VCLK2_DIV6                       130
 #define CLKID_VCLK2_DIV12                      131
+#define CLKID_CTS_ENCL_SEL                     132
 #define CLKID_CTS_ENCL                         133
+#define CLKID_VDIN_MEAS_SEL                    134
+#define CLKID_VDIN_MEAS_DIV                    135
 #define CLKID_VDIN_MEAS                                136
 
 #endif /* __AXG_CLKC_H */