}
; PR8469
-define <2 x i1> @test49(<2 x i32> %tmp3) {
+define <2 x i1> @test49(<2 x i32> %i3) {
; CHECK-LABEL: @test49(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
;
entry:
- %tmp11 = and <2 x i32> %tmp3, <i32 3, i32 3>
- %cmp = icmp ult <2 x i32> %tmp11, <i32 4, i32 4>
+ %i11 = and <2 x i32> %i3, <i32 3, i32 3>
+ %cmp = icmp ult <2 x i32> %i11, <i32 4, i32 4>
ret <2 x i1> %cmp
}
;
%conv = and i32 %x1, 255
%cmp = icmp eq i32 %conv, 127
- %tmp2 = lshr i32 %x1, 16
- %tmp3 = trunc i32 %tmp2 to i8
- %cmp15 = icmp eq i8 %tmp3, 76
+ %i2 = lshr i32 %x1, 16
+ %i3 = trunc i32 %i2 to i8
+ %cmp15 = icmp eq i8 %i3, 76
%A = and i1 %cmp, %cmp15
ret i1 %A
;
%conv = and i128 %x1, 255
%cmp = icmp eq i128 %conv, 127
- %tmp2 = lshr i128 %x1, 16
- %tmp3 = trunc i128 %tmp2 to i8
- %cmp15 = icmp eq i8 %tmp3, 76
+ %i2 = lshr i128 %x1, 16
+ %i3 = trunc i128 %i2 to i8
+ %cmp15 = icmp eq i8 %i3, 76
%A = and i1 %cmp, %cmp15
ret i1 %A
define i32 @f7(i32 %a, i32 %b) {
; CHECK-LABEL: @f7(
-; CHECK-NEXT: [[CMP_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT: [[CMP_MASK:%.*]] = and i32 [[CMP_UNSHIFTED]], 511
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CMP_MASK]], 0
-; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], i32 0, i32 10000
+; CHECK-NEXT: [[CMP_NOT_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: [[CMP_NOT_MASK:%.*]] = and i32 [[CMP_NOT_UNSHIFTED]], 511
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[CMP_NOT_MASK]], 0
+; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP_NOT]], i32 0, i32 10000
; CHECK-NEXT: ret i32 [[S]]
;
%sext = shl i32 %a, 23
; The sub and shl here could be nuw, but this is harder to handle.
define i64 @test_inbounds_nuw_two_gep([0 x i32]* %base, i64 %idx, i64 %idx2) {
; CHECK-LABEL: @test_inbounds_nuw_two_gep(
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[IDX2:%.*]], [[IDX:%.*]]
-; CHECK-NEXT: [[DIFF_NEG:%.*]] = shl i64 [[TMP1]], 2
-; CHECK-NEXT: ret i64 [[DIFF_NEG]]
+; CHECK-NEXT: [[P1_IDX1_NEG:%.*]] = sub i64 [[IDX2:%.*]], [[IDX:%.*]]
+; CHECK-NEXT: [[DOTNEG:%.*]] = shl i64 [[P1_IDX1_NEG]], 2
+; CHECK-NEXT: ret i64 [[DOTNEG]]
;
%p1 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx
%p2 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx2
; CHECK-LABEL: @test18(
; CHECK-NEXT: ret i64 0
;
- %tmp.4 = shl i64 %Y, 2
- %tmp.12 = shl i64 %Y, 2
- %tmp.8 = sub i64 %tmp.4, %tmp.12
- ret i64 %tmp.8
+ %i.4 = shl i64 %Y, 2
+ %i.12 = shl i64 %Y, 2
+ %i.8 = sub i64 %i.4, %i.12
+ ret i64 %i.8
}
define i1 @test20(i32 %g, i32 %h) {
; CHECK-LABEL: @test20(
-; CHECK-NEXT: [[TMP_4:%.*]] = icmp ne i32 [[H:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP_4]]
+; CHECK-NEXT: [[I_4:%.*]] = icmp ne i32 [[H:%.*]], 0
+; CHECK-NEXT: ret i1 [[I_4]]
;
- %tmp.2 = sub i32 %g, %h
- %tmp.4 = icmp ne i32 %tmp.2, %g
- ret i1 %tmp.4
+ %i.2 = sub i32 %g, %h
+ %i.4 = icmp ne i32 %i.2, %g
+ ret i1 %i.4
}
define i1 @test21(i32 %g, i32 %h) {
; CHECK-LABEL: @test21(
-; CHECK-NEXT: [[TMP_4:%.*]] = icmp ne i32 [[H:%.*]], 0
-; CHECK-NEXT: ret i1 [[TMP_4]]
+; CHECK-NEXT: [[I_4:%.*]] = icmp ne i32 [[H:%.*]], 0
+; CHECK-NEXT: ret i1 [[I_4]]
;
- %tmp.2 = sub i32 %g, %h
- %tmp.4 = icmp ne i32 %tmp.2, %g
- ret i1 %tmp.4
+ %i.2 = sub i32 %g, %h
+ %i.4 = icmp ne i32 %i.2, %g
+ ret i1 %i.4
}
; PR2298
define zeroext i1 @test22(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: @test22(
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: ret i1 [[TMP5]]
+; CHECK-NEXT: [[I5:%.*]] = icmp eq i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT: ret i1 [[I5]]
;
- %tmp2 = sub i32 0, %a
- %tmp4 = sub i32 0, %b
- %tmp5 = icmp eq i32 %tmp2, %tmp4
- ret i1 %tmp5
+ %i2 = sub i32 0, %a
+ %i4 = sub i32 0, %b
+ %i5 = icmp eq i32 %i2, %i4
+ ret i1 %i5
}
; rdar://7362831