drm/amd/display: Only limit VSR downscaling when actually downscaling

Signed-off-by: Xingyue Tao <xingyue.tao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 2da1389..46a35c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -145,18 +145,17 @@ bool dpp_get_optimal_number_of_taps(
        else
                pixel_width = scl_data->viewport.width;
 
+       /* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
        if (scl_data->viewport.width  != scl_data->h_active &&
-               scl_data->viewport.height != scl_data->v_active) {
-
-               /* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
-               if (dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
-                       scl_data->format == PIXEL_FORMAT_FP16)
-                       return false;
-
-               if (dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
-                       scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
-                       return false;
-       }
+               scl_data->viewport.height != scl_data->v_active &&
+               dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
+               scl_data->format == PIXEL_FORMAT_FP16)
+               return false;
+
+       if (scl_data->viewport.width > scl_data->h_active &&
+               dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
+               scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
+               return false;
 
        /* TODO: add lb check */