intel: Track the current packet location in the decode context.

This is the start of plumbing the context through the decode
callchain instead of the current 4 arguments.

diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 81ef712..61797e1 100644 (file)
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -39,13 +39,20 @@ struct drm_intel_decode {
        /** PCI device ID. */
        uint32_t devid;
 
-       /** GPU address of the start of the batchbuffer data. */
+       /** GPU address of the start of the current packet. */
        uint32_t hw_offset;
-       /** CPU Virtual address of the start of the batchbuffer data. */
+       /** CPU virtual address of the start of the current packet. */
        uint32_t *data;
-       /** Number of DWORDs of batchbuffer data. */
+       /** DWORDs of remaining batchbuffer data starting from the packet. */
        uint32_t count;
 
+       /** GPU address of the start of the batchbuffer data. */
+       uint32_t base_hw_offset;
+       /** CPU Virtual address of the start of the batchbuffer data. */
+       uint32_t *base_data;
+       /** Number of DWORDs of batchbuffer data. */
+       uint32_t base_count;
+
        /** @{
         * GPU head and tail pointers, which will be noted in the dump, or ~0.
         */
@@ -3583,9 +3590,9 @@ void
 drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
                                   void *data, uint32_t hw_offset, int count)
 {
-       ctx->data = data;
-       ctx->hw_offset = hw_offset;
-       ctx->count = count;
+       ctx->base_data = data;
+       ctx->base_hw_offset = hw_offset;
+       ctx->base_count = count;
 }
 
 void
@@ -3616,16 +3623,15 @@ drm_intel_decode(struct drm_intel_decode *ctx)
        int ret;
        unsigned int index = 0;
        int failures = 0;
-       uint32_t *data;
-       uint32_t count, hw_offset;
        uint32_t devid;
 
        if (!ctx)
                return;
 
-       data = ctx->data;
-       count = ctx->count;
-       hw_offset = ctx->hw_offset;
+       ctx->data = ctx->base_data;
+       ctx->hw_offset = ctx->base_hw_offset;
+       ctx->count = ctx->base_count;
+
        devid = ctx->devid;
        head_offset = ctx->head;
        tail_offset = ctx->tail;
@@ -3634,11 +3640,13 @@ drm_intel_decode(struct drm_intel_decode *ctx)
        saved_s2_set = 0;
        saved_s4_set = 1;
 
-       while (index < count) {
-               switch ((data[index] & 0xe0000000) >> 29) {
+       while (ctx->count > 0) {
+               index = 0;
+
+               switch ((ctx->data[index] & 0xe0000000) >> 29) {
                case 0x0:
-                       ret = decode_mi(data + index, count - index,
-                                       hw_offset + index * 4, &failures);
+                       ret = decode_mi(ctx->data, ctx->count,
+                                       ctx->hw_offset, &failures);
 
                        /* If MI_BATCHBUFFER_END happened, then dump
                         * the rest of the output in case we some day
@@ -3650,9 +3658,10 @@ drm_intel_decode(struct drm_intel_decode *ctx)
                                if (ctx->dump_past_end) {
                                        index++;
                                } else {
-                                       for (index = index + 1; index < count;
+                                       for (index = index + 1; index < ctx->count;
                                             index++) {
-                                               instr_out(data, hw_offset,
+                                               instr_out(ctx->data,
+                                                         ctx->hw_offset,
                                                          index, "\n");
                                        }
                                }
@@ -3660,32 +3669,40 @@ drm_intel_decode(struct drm_intel_decode *ctx)
                                index += ret;
                        break;
                case 0x2:
-                       index += decode_2d(data + index, count - index,
-                                          hw_offset + index * 4, &failures);
+                       index += decode_2d(ctx->data, ctx->count,
+                                          ctx->hw_offset, &failures);
                        break;
                case 0x3:
                        if (IS_9XX(devid) && !IS_GEN3(devid)) {
                                index +=
-                                   decode_3d_965(data + index, count - index,
-                                                 hw_offset + index * 4, devid,
+                                   decode_3d_965(ctx->data, ctx->count,
+                                                 ctx->hw_offset, devid,
                                                  &failures);
                        } else if (IS_GEN3(devid)) {
-                               index += decode_3d(data + index, count - index,
-                                                  hw_offset + index * 4,
+                               index += decode_3d(ctx->data, ctx->count,
+                                                  ctx->hw_offset,
                                                   devid, &failures);
                        } else {
                                index +=
-                                   decode_3d_i830(data + index, count - index,
-                                                  hw_offset + index * 4, devid,
+                                   decode_3d_i830(ctx->data, ctx->count,
+                                                  ctx->hw_offset, devid,
                                                   &failures);
                        }
                        break;
                default:
-                       instr_out(data, hw_offset, index, "UNKNOWN\n");
+                       instr_out(ctx->data, ctx->hw_offset, index,
+                                 "UNKNOWN\n");
                        failures++;
                        index++;
                        break;
                }
                fflush(out);
+
+               if (ctx->count < index)
+                       break;
+
+               ctx->count -= index;
+               ctx->data += index;
+               ctx->hw_offset += 4 * index;
        }
 }

diff --git a/intel/tests/gen7-3d.batch-ref.txt b/intel/tests/gen7-3d.batch-ref.txt
index c710a78..953b7bd 100644 (file)
--- a/intel/tests/gen7-3d.batch-ref.txt
+++ b/intel/tests/gen7-3d.batch-ref.txt
@@ -282,7 +282,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x123003ec:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x123003f0:      0x02380000: MI_FLUSH
 0x123003f4:      0x00000000: MI_NOOP
-0x123003f8:      0xea9de040:    UNKNOWN
+0x123003f8:      0xea9de040: UNKNOWN
 0x123003fc:      0x00007f93: MI_NOOP
 0x12300400:      0x02279b80: MI_FLUSH
 0x12300404:      0x00000000: MI_NOOP
@@ -483,7 +483,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x123006b0:      0x00000000: MI_NOOP
 0x123006b4:      0x0000000b: MI_NOOP
 0x123006b8:      0x00000000: MI_NOOP
-0x123006bc:      0xea9de040:    UNKNOWN
+0x123006bc:      0xea9de040: UNKNOWN
 0x123006c0:      0x00007f93: MI_NOOP
 0x123006c4:      0x00000000: MI_NOOP
 0x123006c8:      0x00000001: MI_NOOP
@@ -556,7 +556,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x12300798:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x1230079c:      0x02390000: MI_FLUSH
 0x123007a0:      0x00000000: MI_NOOP
-0x123007a4:      0xea9de040:    UNKNOWN
+0x123007a4:      0xea9de040: UNKNOWN
 0x123007a8:      0x00007f93: MI_NOOP
 0x123007ac:      0x02279b80: MI_FLUSH
 0x123007b0:      0x00000000: MI_NOOP
@@ -666,7 +666,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x123008f0:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x123008f4:      0x02380000: MI_FLUSH
 0x123008f8:      0x00000000: MI_NOOP
-0x123008fc:      0xea9de040:    UNKNOWN
+0x123008fc:      0xea9de040: UNKNOWN
 0x12300900:      0x00007f93: MI_NOOP
 0x12300904:      0x02279b80: MI_FLUSH
 0x12300908:      0x00000000: MI_NOOP
@@ -844,7 +844,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x12300b4c:      0x00000000: MI_NOOP
 0x12300b50:      0x0000000b: MI_NOOP
 0x12300b54:      0x00000000: MI_NOOP
-0x12300b58:      0xea9de040:    UNKNOWN
+0x12300b58:      0xea9de040: UNKNOWN
 0x12300b5c:      0x00007f93: MI_NOOP
 0x12300b60:      0x00000000: MI_NOOP
 0x12300b64:      0x00000001: MI_NOOP
@@ -917,7 +917,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x12300c34:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x12300c38:      0x02390000: MI_FLUSH
 0x12300c3c:      0x00000000: MI_NOOP
-0x12300c40:      0xea9de040:    UNKNOWN
+0x12300c40:      0xea9de040: UNKNOWN
 0x12300c44:      0x00007f93: MI_NOOP
 0x12300c48:      0x02279b80: MI_FLUSH
 0x12300c4c:      0x00000000: MI_NOOP
@@ -1027,7 +1027,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x12300d8c:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x12300d90:      0x02380000: MI_FLUSH
 0x12300d94:      0x00000000: MI_NOOP
-0x12300d98:      0xea9de040:    UNKNOWN
+0x12300d98:      0xea9de040: UNKNOWN
 0x12300d9c:      0x00007f93: MI_NOOP
 0x12300da0:      0x02279b80: MI_FLUSH
 0x12300da4:      0x00000000: MI_NOOP
@@ -1205,7 +1205,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x12300fe8:      0x00000000: MI_NOOP
 0x12300fec:      0x0000000b: MI_NOOP
 0x12300ff0:      0x00000000: MI_NOOP
-0x12300ff4:      0xea9de040:    UNKNOWN
+0x12300ff4:      0xea9de040: UNKNOWN
 0x12300ff8:      0x00007f93: MI_NOOP
 0x12300ffc:      0x00000000: MI_NOOP
 0x12301000:      0x00000001: MI_NOOP
@@ -1278,7 +1278,7 @@ Bad count in 3DSTATE_CONSTANT_VS_STATE
 0x123010d0:      0x00600810: MI_NOOP write NOPID reg, val=0x200810
 0x123010d4:      0x02390000: MI_FLUSH
 0x123010d8:      0x00000000: MI_NOOP
-0x123010dc:      0xea9de040:    UNKNOWN
+0x123010dc:      0xea9de040: UNKNOWN
 0x123010e0:      0x00007f93: MI_NOOP
 0x123010e4:      0x02279b80: MI_FLUSH
 0x123010e8:      0x00000000: MI_NOOP