ret <4 x i32> %2
}
+define <16 x i8> @or_icmp_eq_const_1bit_diff(<16 x i8> %x) {
+; SSE-LABEL: or_icmp_eq_const_1bit_diff:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [43,43,43,43,43,43,43,43,43,43,43,43,43,43,43,43]
+; SSE-NEXT: pcmpeqb %xmm0, %xmm1
+; SSE-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: por %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: or_icmp_eq_const_1bit_diff:
+; AVX: # %bb.0:
+; AVX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %a = icmp eq <16 x i8> %x, <i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43, i8 43>
+ %b = icmp eq <16 x i8> %x, <i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45, i8 45>
+ %ax = sext <16 x i1> %a to <16 x i8>
+ %bx = sext <16 x i1> %b to <16 x i8>
+ %r = or <16 x i8> %ax, %bx
+ ret <16 x i8> %r
+}
+
+define <4 x i32> @or_icmp_ne_const_1bit_diff(<4 x i32> %x) {
+; SSE-LABEL: or_icmp_ne_const_1bit_diff:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [44,60,44,60]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm1
+; SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: por %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: or_icmp_ne_const_1bit_diff:
+; AVX: # %bb.0:
+; AVX-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
+; AVX-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; AVX-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %a = icmp ne <4 x i32> %x, <i32 44, i32 60, i32 44, i32 60>
+ %b = icmp ne <4 x i32> %x, <i32 60, i32 44, i32 60, i32 44>
+ %ax = sext <4 x i1> %a to <4 x i32>
+ %bx = sext <4 x i1> %b to <4 x i32>
+ %r = or <4 x i32> %ax, %bx
+ ret <4 x i32> %r
+}
+
+define <16 x i8> @and_icmp_eq_const_1bit_diff(<16 x i8> %x) {
+; SSE-LABEL: and_icmp_eq_const_1bit_diff:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [43,43,45,45,43,43,45,45,43,43,45,45,43,43,45,45]
+; SSE-NEXT: pcmpeqb %xmm0, %xmm1
+; SSE-NEXT: pcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pand %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: and_icmp_eq_const_1bit_diff:
+; AVX: # %bb.0:
+; AVX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpand %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %a = icmp eq <16 x i8> %x, <i8 43, i8 43, i8 45, i8 45, i8 43, i8 43, i8 45, i8 45, i8 43, i8 43, i8 45, i8 45, i8 43, i8 43, i8 45, i8 45>
+ %b = icmp eq <16 x i8> %x, <i8 45, i8 45, i8 43, i8 43, i8 45, i8 45, i8 43, i8 43, i8 45, i8 45, i8 43, i8 43, i8 45, i8 45, i8 43, i8 43>
+ %ax = sext <16 x i1> %a to <16 x i8>
+ %bx = sext <16 x i1> %b to <16 x i8>
+ %r = and <16 x i8> %ax, %bx
+ ret <16 x i8> %r
+}
+
+define <4 x i32> @and_icmp_ne_const_1bit_diff(<4 x i32> %x) {
+; SSE-LABEL: and_icmp_ne_const_1bit_diff:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [44,60,54,44]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm1
+; SSE-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: por %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: and_icmp_ne_const_1bit_diff:
+; AVX: # %bb.0:
+; AVX-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
+; AVX-NEXT: vpxor %xmm2, %xmm1, %xmm1
+; AVX-NEXT: vpcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0
+; AVX-NEXT: vpor %xmm0, %xmm1, %xmm0
+; AVX-NEXT: retq
+ %a = icmp ne <4 x i32> %x, <i32 44, i32 60, i32 54, i32 44>
+ %b = icmp ne <4 x i32> %x, <i32 60, i32 52, i32 50, i32 60>
+ %ax = sext <4 x i1> %a to <4 x i32>
+ %bx = sext <4 x i1> %b to <4 x i32>
+ %r = or <4 x i32> %ax, %bx
+ ret <4 x i32> %r
+}
+
; At one point we were incorrectly constant-folding a setcc to 0x1 instead of
; 0xff, leading to a constpool load. The instruction doesn't matter here, but it
; should set all bits to 1.