riscv: dts: starfive: Add clock and reset for i2c

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index dcea9bd..968724f 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -497,6 +497,10 @@
                i2c6: i2c@12060000 {
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x12060000 0x0 0x10000>;
+                       clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
+                                <&clkgen JH7110_I2C6_CLK_APB>;
+                       clock-names = "ref", "pclk";
+                       resets = <&rstgen RSTN_U6_DW_I2C_APB>;
                        interrupts = <51>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -506,6 +510,10 @@
                i2c0: i2c@10030000 {
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x10030000 0x0 0x10000>;
+                       clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
+                                <&clkgen JH7110_I2C0_CLK_APB>;
+                       clock-names = "ref", "pclk";
+                       resets = <&rstgen RSTN_U0_DW_I2C_APB>;
                        interrupts = <35>;
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -515,6 +523,10 @@
                i2c1: i2c@10040000 {
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x10040000 0x0 0x10000>;
+                       clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
+                                <&clkgen JH7110_I2C1_CLK_APB>;
+                       clock-names = "ref", "pclk";
+                       resets = <&rstgen RSTN_U1_DW_I2C_APB>;
                        interrupts = <36>;
                        #address-cells = <1>;
                        #size-cells = <0>;

diff --git a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
index ff79823..a974afd 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
@@ -479,6 +479,12 @@
        pinctrl-0 = <&gmac1_pins>;
 };
 
+&i2c6 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c6_pins>;
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins>;