{
ctrl_outw(0xf900, FPGA_OUT); /* FPGA */
- ctrl_outl(0x00001001, MSTPCR0);
- ctrl_outl(0x00000000, MSTPCR1);
- ctrl_outl(0xffffbfC0, MSTPCR2); /* LCDC, BEU, CEU, VEU, KEYSC */
-
ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
ctrl_outw(0x0020, PORT_PSELD);
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
+#include <asm/clock.h>
static struct resource iic0_resources[] = {
[0] = {
static int __init sh7343_devices_setup(void)
{
+ clk_always_enable("mstp031"); /* TLB */
+ clk_always_enable("mstp030"); /* IC */
+ clk_always_enable("mstp029"); /* OC */
+ clk_always_enable("mstp028"); /* URAM */
+ clk_always_enable("mstp026"); /* XYMEM */
+ clk_always_enable("mstp023"); /* INTC3 */
+ clk_always_enable("mstp022"); /* INTC */
+ clk_always_enable("mstp020"); /* SuperHyway */
+ clk_always_enable("mstp109"); /* I2C0 */
+ clk_always_enable("mstp108"); /* I2C1 */
+ clk_always_enable("mstp202"); /* VEU */
+ clk_always_enable("mstp201"); /* VPU */
+
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
+
return platform_add_devices(sh7343_devices,
ARRAY_SIZE(sh7343_devices));
}
#define PORT_PWDR 0xA4050166
#define PORT_PYDR 0xA4050168
-#define MSTPCR0 0xA4150030
-#define MSTPCR1 0xA4150034
-#define MSTPCR2 0xA4150038
-
#define FPGA_IN 0xb1400000
#define FPGA_OUT 0xb1400002