imx8m: ddr: Disable CA VREF Training for LPDDR4

Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D.  According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
index 5faa002..aa23c35 100644 (file)
--- a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
+++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c
@@ -799,7 +799,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },

diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
index 9d069fc..8c5306d 100755 (executable)
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -1298,7 +1298,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },
@@ -1330,7 +1329,6 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },