variables:
windows_vm: windows-2019
- ubuntu_vm: ubuntu-18.04
- macos_vm: macOS-10.15
+ ubuntu_vm: ubuntu-22.04
+ macos_vm: macOS-12
ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220302-15Mar2022
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
the "64" category of the Power ISA). This is necessary for ePAPR
compliance, among other possible reasons.
- CONFIG_SYS_FSL_TBCLK_DIV
-
- Defines the core time base clock divider ratio compared to the
- system clock. On most PQ3 devices this is 8, on newer QorIQ
- devices it can be 16 or 32. The ratio varies from SoC to Soc.
-
- CONFIG_SYS_FSL_PCIE_COMPAT
-
- Defines the string to utilize when trying to match PCIe device
- tree nodes for the given platform.
-
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
- CONFIG_SYS_FSL_DSP_DDR_ADDR
- This value denotes start offset of DDR memory which is
- connected exclusively to the DSP cores.
-
- CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
- This value denotes start offset of M2 memory
- which is directly connected to the DSP core.
-
- CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
- This value denotes start offset of M3 memory which is directly
- connected to the DSP core.
-
- CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
- This value denotes start offset of DSP CCSR space.
-
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL SoC's.
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
- Generic CPU options:
- CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
-
- Defines the endianess of the CPU. Implementation of those
- values is arch specific.
CONFIG_SYS_FSL_DDR
Freescale DDR driver in use. This type of DDR controller is
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
- CONFIG_SYS_FSL_DDRC_GEN1
- Freescale DDR1 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN2
- Freescale DDR2 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN3
- Freescale DDR3 controller.
-
- CONFIG_SYS_FSL_DDRC_GEN4
- Freescale DDR4 controller.
-
- CONFIG_SYS_FSL_DDRC_ARM_GEN3
- Freescale DDR3 controller for ARM-based SoCs.
-
- CONFIG_SYS_FSL_DDR1
- Board config to use DDR1. It can be enabled for SoCs with
- Freescale DDR1 or DDR2 controllers, depending on the board
- implemetation.
-
- CONFIG_SYS_FSL_DDR2
- Board config to use DDR2. It can be enabled for SoCs with
- Freescale DDR2 or DDR3 controllers, depending on the board
- implementation.
-
- CONFIG_SYS_FSL_DDR3
- Board config to use DDR3. It can be enabled for SoCs with
- Freescale DDR3 or DDR3L controllers.
-
- CONFIG_SYS_FSL_DDR3L
- Board config to use DDR3L. It can be enabled for SoCs with
- DDR3L controllers.
-
CONFIG_SYS_FSL_IFC_CLK_DIV
Defines divider of platform clock(clock input to IFC controller).
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_BE
- Defines the DDR controller register space as Big Endian
-
- CONFIG_SYS_FSL_DDR_LE
- Defines the DDR controller register space as Little Endian
-
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
- Number of controllers used as main memory.
-
- CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
- Number of controllers used for other than main memory.
-
- CONFIG_SYS_FSL_SEC_BE
- Defines the SEC controller register space as Big Endian
-
- CONFIG_SYS_FSL_SEC_LE
- Defines the SEC controller register space as Little Endian
-
- MIPS CPU options:
CONFIG_XWAY_SWAP_BYTES
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_SMC91111
- Support for SMSC's LAN91C111 chip
-
- CONFIG_SMC91111_BASE
- Define this to hold the physical address
- of the device (I/O space)
-
- CONFIG_SMC_USE_32_BIT
- Define this if data bus is 32 bits
-
- CONFIG_SMC_USE_IOFUNCS
- Define this to use i/o functions instead of macros
- (some hardware wont work with macros)
-
CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
Define this if you have more then 3 PHYs.
select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_7
select TIMER
+ select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
+ select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
config ARM
bool "ARM architecture"
endif
+config SYS_FSL_NUM_CC_PLLS
+ int "Number of clock control PLLs"
+ depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
+ default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
+ default 6 if FSL_LSCH3 || MPC85xx
+
config SYS_FSL_ESDHC_BE
bool
#
# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
-ifndef CONFIG_CPU_BIG_ENDIAN
-CONFIG_SYS_LITTLE_ENDIAN = 1
-else
-CONFIG_SYS_BIG_ENDIAN = 1
-endif
-
ifdef CONFIG_SYS_LITTLE_ENDIAN
KBUILD_LDFLAGS += -EL
PLATFORM_CPPFLAGS += -mlittle-endian
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#endif
-
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select SYS_FSL_OTHER_DDR_NUM_CTRLS
select GICV3
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#endif
-
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
-#endif
-
-
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL
-#define CONFIG_SYS_FSL_ERRATUM_A008751
-
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
#elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_PAGE_SIZE 0x10000
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
#elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* SEC */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
/* DCFG - GUR */
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
-#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define GIC_ADDR_BIT 31
#define SCFG_GIC400_ALIGN 0x1570188
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x01410000
#define GICC_BASE 0x01420000
-
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
};
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
-#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
-#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
-#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
-#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
#define CONFIG_SYS_FSL_FM1_ADDR \
#define USB_PHY0_BASE_ADDR 0x5b100000
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_ARCH_LS1021A
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
bool "Ethernut5 board"
select AT91SAM9XE
-config TARGET_SNAPPER9260
- bool "Support snapper9260"
- select AT91SAM9260
- select AT91_WANTS_COMMON_PHY
- select DM
- select DM_GPIO
- select DM_SERIAL
- imply CMD_DM
-
config TARGET_GURNARD
bool "Support gurnard"
select AT91SAM9G45
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bluewater/gurnard/Kconfig"
-source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
-#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
- defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
- halt
-#endif
jsr (%a1)
/******************************************************************************/
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
-#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE!=CONFIG_SYS_INT_FLASH_BASE) && \
- defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
- halt
-#endif
jsr (%a1)
/******************************************************************************/
select BOARD_EARLY_INIT_F
select SYS_83XX_DDR_USES_CS0
-config TARGET_IDS8313
- bool "Support ids8313"
- select ARCH_MPC8313
- select DM
- imply CMD_DM
-
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
bool
source "board/freescale/mpc837xerdb/Kconfig"
-source "board/ids/ids8313/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
endmenu
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_NGPIXIS
+ select SYS_FSL_RAID_ENGINE
imply CMD_SATA
imply PANIC_HANG
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
imply CMD_EEPROM
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
imply CMD_SATA
select SYS_FSL_ERRATUM_I2C_A004447
select SYS_FSL_ERRATUM_NMG_CPU_A011
select SYS_FSL_ERRATUM_SRIO_A004034
+ select SYS_FSL_PCIE_COMPAT_P4080_PCIE
select SYS_P4080_ERRATUM_CPU22
select SYS_P4080_ERRATUM_PCIE_A003
select SYS_P4080_ERRATUM_SERDES8
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_USB1_PHY_ENABLE
+ select SYS_FSL_USB2_PHY_ENABLE
select SYS_PPC64
select FSL_ELBC
imply CMD_SATA
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_EEPROM
imply CMD_NAND
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
+ select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRIO_LIODN
+ select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+ select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
config FSL_PCIE_RESET
bool
+config SYS_FSL_RAID_ENGINE
+ bool
+
+config SYS_FSL_RMU
+ bool
+
config SYS_FSL_QORIQ_CHASSIS1
bool
bool
select SYS_FSL_CPC
+config FSL_NGPIXIS
+ bool
+
config SYS_CPC_REINIT_F
bool
help
config SYS_CACHE_STASHING
bool "Enable cache stashing"
+config SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ bool
+
+config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ bool
+
+config SYS_FSL_PCIE_COMPAT
+ string
+ depends on FSL_CORENET
+ default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
+ default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
+ default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
+ default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
+ help
+ Defines the string to utilize when trying to match PCIe device tree
+ nodes for the given platform.
+
+config SYS_FSL_SINGLE_SOURCE_CLK
+ bool
+
+config SYS_FSL_SRIO_LIODN
+ bool
+
+config SYS_FSL_TBCLK_DIV
+ int
+ default 32 if ARCH_P2041 || ARCH_P3041
+ default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+ ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
+ ARCH_T1024 || ARCH_T2080
+ default 8
+ help
+ Defines the core time base clock divider ratio compared to the system
+ clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
+ be 16 or 32. The ratio varies from SoC to Soc.
+
+config SYS_FSL_USB1_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB2_PHY_ENABLE
+ bool
+
+config SYS_FSL_USB_DUAL_PHY_ENABLE
+ bool
+
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx
/*
* Get timebase clock frequency
*/
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
__weak unsigned long get_tbclk(void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
-#endif
/* --------------------------------------------------------------- */
void get_sys_info(sys_info_t *sys_info)
return 0;
}
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
void udelay(unsigned long usec)
{
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 32
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
-#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
-#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
-#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#elif defined(CONFIG_ARCH_T4240)
-#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#ifdef CONFIG_ARCH_T4240
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#endif
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_LIODN
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
-#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_DSP_CPUS 2
-#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
-#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
-#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRIO_LIODN
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV 16
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
-#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ISBC_VER 2
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
-#if !defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
-#endif
-
#endif /* _ASM_MPC85xx_CONFIG_H_ */
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080
-#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000
#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
-#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
-#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-#if defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
-#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
- (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
-#endif
-
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_SCFG_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
- (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
- (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \
int board_eth_init(struct bd_info *bis)
{
int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
return rc;
}
#endif
{
int rc = 0;
#ifndef CONFIG_DM_ETH
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
+++ /dev/null
-if TARGET_SNAPPER9260
-
-config SYS_BOARD
- default "snapper9260"
-
-config SYS_VENDOR
- default "bluewater"
-
-config SYS_CONFIG_NAME
- default "snapper9260"
-
-endif
+++ /dev/null
-SNAPPER9260 BOARD
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: board/bluewater/snapper9260/
-F: include/configs/snapper9260.h
-F: configs/snapper9260_defconfig
-F: configs/snapper9g20_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011 Bluewater Systems
-# Ryan Mallon <ryan@bluewatersys.com>
-
-obj-y += snapper9260.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Bluewater Systems Snapper 9260/9G20 modules
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/atmel_serial.h>
-#include <net.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <pca953x.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* IO Expander pins */
-#define IO_EXP_ETH_RESET (0 << 1)
-#define IO_EXP_ETH_POWER (1 << 1)
-
-static void macb_hw_init(void)
-{
- struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
- at91_periph_clk_enable(ATMEL_ID_EMAC0);
-
- /* Disable pull-ups to prevent PHY going into test mode */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA18),
- &pioa->pudr);
-
- /* Power down ethernet */
- pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
- pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
-
- /* Hold ethernet in reset */
- pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
- pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
-
- /* Enable ethernet power */
- pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
-
- at91_phy_reset();
-
- /* Bring the ethernet out of reset */
- pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
-
- /* The phy internal reset take 21ms */
- udelay(21 * 1000);
-
- /* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PA14) |
- pin_to_mask(AT91_PIN_PA15) |
- pin_to_mask(AT91_PIN_PA18),
- &pioa->puer);
-
- at91_macb_hw_init();
-}
-
-static void nand_hw_init(void)
-{
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- unsigned long csa;
-
- /* Enable CS3 as NAND/SmartMedia */
- csa = readl(&matrix->ebicsa);
- csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
- writel(csa, &matrix->ebicsa);
-
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
- AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- AT91_SMC_MODE_DBW_8 |
- AT91_SMC_MODE_TDF_CYCLE(3),
- &smc->cs[3].mode);
-
- /* Configure RDY/BSY */
- gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
-
- /* Enable NandFlash */
- gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-}
-
-int board_init(void)
-{
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
-
- /* The mach-type is the same for both Snapper 9260 and 9G20 */
- gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
-
- /* Address of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- /* Initialise peripherals */
- at91_seriald_hw_init();
- i2c_set_bus_num(0);
- nand_hw_init();
- macb_hw_init();
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- return 0;
-}
-
-void reset_phy(void)
-{
-}
-
-static struct atmel_serial_plat at91sam9260_serial_plat = {
- .base_addr = ATMEL_BASE_DBGU,
-};
-
-U_BOOT_DRVINFO(at91sam9260_serial) = {
- .name = "serial_atmel",
- .plat = &at91sam9260_serial_plat,
-};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+#
+
+obj-y += dh_common.o
+
+ifneq (,$(CONFIG_ARCH_MX6)$(CONFIG_ARCH_IMX8M))
+obj-y += dh_imx.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <net.h>
+
+#include "dh_common.h"
+
+bool dh_mac_is_in_env(const char *env)
+{
+ unsigned char enetaddr[6];
+
+ return eth_env_get_enetaddr(env, enetaddr);
+}
+
+int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
+{
+ struct udevice *dev;
+ int ret;
+ ofnode node;
+
+ node = ofnode_path(alias);
+ if (!ofnode_valid(node)) {
+ printf("%s: ofnode for %s not found!", __func__, alias);
+ return -ENOENT;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
+ if (ret) {
+ printf("%s: Cannot find EEPROM! ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+ if (ret) {
+ printf("%s: Error reading EEPROM! ret = %d\n", __func__, ret);
+ return ret;
+ }
+
+ if (!is_valid_ethaddr(enetaddr)) {
+ printf("%s: Address read from EEPROM is invalid!\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+__weak int dh_setup_mac_address(void)
+{
+ unsigned char enetaddr[6];
+
+ if (dh_mac_is_in_env("ethaddr"))
+ return 0;
+
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
+ return eth_env_set_enetaddr("ethaddr", enetaddr);
+
+ printf("%s: Unable to set mac address!\n", __func__);
+ return -ENXIO;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/*
+ * dh_mac_is_in_env - Check if MAC address is already set
+ *
+ * @env: name of environment variable
+ * Return: true if MAC is set, false otherwise
+ */
+bool dh_mac_is_in_env(const char *env);
+
+/*
+ * dh_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr
+ *
+ * @enetaddr: buffer where address is to be stored
+ * @alias: alias for EEPROM device tree node
+ * Return: 0 if OK, other value on error
+ */
+int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias);
+
+/*
+ * dh_setup_mac_address - Try to get MAC address from various locations and write it to env
+ *
+ * Return: 0 if OK, other value on error
+ */
+int dh_setup_mac_address(void);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <common.h>
+#include <net.h>
+#include "dh_imx.h"
+
+int dh_imx_get_mac_from_fuse(unsigned char *enetaddr)
+{
+ /*
+ * If IIM fuses contain valid MAC address, use it.
+ * The IIM MAC address fuses are NOT programmed by default.
+ */
+ imx_get_mac_from_fuse(0, enetaddr);
+ if (!is_valid_ethaddr(enetaddr))
+ return -EINVAL;
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
+ */
+
+/*
+ * dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env
+ *
+ * @enetaddr: buffer where address is to be stored
+ * Return: 0 if OK, other value on error
+ */
+int dh_imx_get_mac_from_fuse(unsigned char *enetaddr);
#include <linux/delay.h>
#include <usb/ehci-ci.h>
+#include "../common/dh_common.h"
+#include "../common/dh_imx.h"
+
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
}
#endif
-static int setup_dhcom_mac_from_fuse(void)
+int dh_setup_mac_address(void)
{
- struct udevice *dev;
- ofnode eeprom;
unsigned char enetaddr[6];
- int ret;
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret) /* ethaddr is already set */
+ if (dh_mac_is_in_env("ethaddr"))
return 0;
- imx_get_mac_from_fuse(0, enetaddr);
-
- if (is_valid_ethaddr(enetaddr)) {
- eth_env_set_enetaddr("ethaddr", enetaddr);
- return 0;
- }
-
- eeprom = ofnode_get_aliases_node("eeprom0");
- if (!ofnode_valid(eeprom)) {
- printf("Can't find eeprom0 alias!\n");
- return -ENODEV;
- }
+ if (!dh_imx_get_mac_from_fuse(enetaddr))
+ goto out;
- ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
- if (ret) {
- printf("Cannot find EEPROM!\n");
- return ret;
- }
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
+ goto out;
- ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
- if (ret) {
- printf("Error reading configuration EEPROM!\n");
- return ret;
- }
+ printf("%s: Unable to get MAC address!\n", __func__);
+ return -ENXIO;
- if (is_valid_ethaddr(enetaddr))
- eth_env_set_enetaddr("ethaddr", enetaddr);
-
- return 0;
+out:
+ return eth_env_set_enetaddr("ethaddr", enetaddr);
}
int board_early_init_f(void)
u32 hw_code;
char buf[16];
- setup_dhcom_mac_from_fuse();
+ dh_setup_mac_address();
hw_code = board_get_hwcode();
#include <miiphy.h>
#include "lpddr4_timing.h"
+#include "../common/dh_common.h"
+#include "../common/dh_imx.h"
DECLARE_GLOBAL_DATA_PTR;
set_clk_enet(ENET_125MHZ);
}
-static int setup_mac_address_from_eeprom(char *alias, char *env, bool odd)
+static int dh_imx8_setup_ethaddr(void)
{
unsigned char enetaddr[6];
- struct udevice *dev;
- int ret, offset;
-
- offset = fdt_path_offset(gd->fdt_blob, alias);
- if (offset < 0) {
- printf("%s: No eeprom0 path offset\n", __func__);
- return offset;
- }
-
- ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, offset, &dev);
- if (ret) {
- printf("Cannot find EEPROM!\n");
- return ret;
- }
-
- ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
- if (ret) {
- printf("Error reading configuration EEPROM!\n");
- return ret;
- }
+
+ if (dh_mac_is_in_env("ethaddr"))
+ return 0;
+
+ if (!dh_imx_get_mac_from_fuse(enetaddr))
+ goto out;
+
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
+ goto out;
+
+ return -ENXIO;
+
+out:
+ return eth_env_set_enetaddr("ethaddr", enetaddr);
+}
+
+static int dh_imx8_setup_eth1addr(void)
+{
+ unsigned char enetaddr[6];
+
+ if (dh_mac_is_in_env("eth1addr"))
+ return 0;
+
+ if (!dh_imx_get_mac_from_fuse(enetaddr))
+ goto increment_out;
+
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
+ goto out;
/*
* Populate second ethernet MAC from first ethernet EEPROM with MAC
* address LSByte incremented by 1. This is only used on SoMs without
* second ethernet EEPROM, i.e. early prototypes.
*/
- if (odd)
- enetaddr[5]++;
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
+ goto increment_out;
- eth_env_set_enetaddr(env, enetaddr);
+ return -ENXIO;
- return 0;
+increment_out:
+ enetaddr[5]++;
+
+out:
+ return eth_env_set_enetaddr("eth1addr", enetaddr);
}
-static void setup_mac_address(void)
+int dh_setup_mac_address(void)
{
- unsigned char enetaddr[6];
- bool skip_eth0 = false;
- bool skip_eth1 = false;
int ret;
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret) /* ethaddr is already set */
- skip_eth0 = true;
-
- ret = eth_env_get_enetaddr("eth1addr", enetaddr);
- if (ret) /* eth1addr is already set */
- skip_eth1 = true;
+ ret = dh_imx8_setup_ethaddr();
+ if (ret)
+ printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
- /* Both MAC addresses are already set in U-Boot environment. */
- if (skip_eth0 && skip_eth1)
- return;
+ ret = dh_imx8_setup_eth1addr();
+ if (ret)
+ printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
- /*
- * If IIM fuses contain valid MAC address, use it.
- * The IIM MAC address fuses are NOT programmed by default.
- */
- imx_get_mac_from_fuse(0, enetaddr);
- if (is_valid_ethaddr(enetaddr)) {
- if (!skip_eth0)
- eth_env_set_enetaddr("ethaddr", enetaddr);
- /*
- * The LSbit of MAC address in fuses is always 0, use the
- * next consecutive MAC address for the second ethernet.
- */
- enetaddr[5]++;
- if (!skip_eth1)
- eth_env_set_enetaddr("eth1addr", enetaddr);
- return;
- }
-
- /* Use on-SoM EEPROMs with pre-programmed MAC address. */
- if (!skip_eth0) {
- /* We cannot do much more if this returns -ve . */
- setup_mac_address_from_eeprom("eeprom0", "ethaddr", false);
- }
-
- if (!skip_eth1) {
- ret = setup_mac_address_from_eeprom("eeprom1", "eth1addr",
- false);
- if (ret) { /* Second EEPROM might not be populated. */
- /* We cannot do much more if this returns -ve . */
- setup_mac_address_from_eeprom("eeprom0", "eth1addr",
- true);
- }
- }
+ return ret;
}
int board_init(void)
int board_late_init(void)
{
- setup_mac_address();
+ dh_setup_mac_address();
return 0;
}
#include <usb/dwc2_udc.h>
#include <watchdog.h>
#include <dm/ofnode.h>
+#include "../common/dh_common.h"
#include "../../st/common/stpmic1.h"
/* SYSCFG registers */
#define KS_CIDER 0xC0
#define CIDER_ID 0x8870
-int setup_mac_address(void)
+static bool dh_stm32_mac_is_in_ks8851(void)
{
- unsigned char enetaddr[6];
- bool skip_eth0 = false;
- bool skip_eth1 = false;
- struct udevice *dev;
- int ret;
ofnode node;
-
- ret = eth_env_get_enetaddr("ethaddr", enetaddr);
- if (ret) /* ethaddr is already set */
- skip_eth0 = true;
+ u32 reg, cider, ccr;
node = ofnode_path("ethernet1");
- if (!ofnode_valid(node)) {
- /* ethernet1 is not present in the system */
- skip_eth1 = true;
- goto out_set_ethaddr;
- }
+ if (!ofnode_valid(node))
+ return false;
- ret = eth_env_get_enetaddr("eth1addr", enetaddr);
- if (ret) {
- /* eth1addr is already set */
- skip_eth1 = true;
- goto out_set_ethaddr;
- }
-
- ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll");
- if (ret)
- goto out_set_ethaddr;
+ if (ofnode_device_is_compatible(node, "micrel,ks8851-mll"))
+ return false;
/*
* KS8851 with EEPROM may use custom MAC from EEPROM, read
* is present. If EEPROM is present, it must contain valid
* MAC address.
*/
- u32 reg, cider, ccr;
reg = ofnode_get_addr(node);
if (!reg)
- goto out_set_ethaddr;
+ return false;
writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
cider = readw(reg);
- if ((cider & 0xfff0) != CIDER_ID) {
- skip_eth1 = true;
- goto out_set_ethaddr;
- }
+ if ((cider & 0xfff0) != CIDER_ID)
+ return true;
writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
ccr = readw(reg);
- if (ccr & KS_CCR_EEPROM) {
- skip_eth1 = true;
- goto out_set_ethaddr;
- }
+ if (ccr & KS_CCR_EEPROM)
+ return true;
+
+ return false;
+}
-out_set_ethaddr:
- if (skip_eth0 && skip_eth1)
+static int dh_stm32_setup_ethaddr(void)
+{
+ unsigned char enetaddr[6];
+
+ if (dh_mac_is_in_env("ethaddr"))
return 0;
- node = ofnode_path("eeprom0");
- if (!ofnode_valid(node)) {
- printf("%s: No eeprom0 path offset\n", __func__);
- return -ENOENT;
- }
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
+ return eth_env_set_enetaddr("ethaddr", enetaddr);
- ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev);
- if (ret) {
- printf("Cannot find EEPROM!\n");
- return ret;
- }
+ return -ENXIO;
+}
- ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
- if (ret) {
- printf("Error reading configuration EEPROM!\n");
- return ret;
- }
+static int dh_stm32_setup_eth1addr(void)
+{
+ unsigned char enetaddr[6];
- if (is_valid_ethaddr(enetaddr)) {
- if (!skip_eth0)
- eth_env_set_enetaddr("ethaddr", enetaddr);
+ if (dh_mac_is_in_env("eth1addr"))
+ return 0;
+ if (dh_stm32_mac_is_in_ks8851())
+ return 0;
+
+ if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) {
enetaddr[5]++;
- if (!skip_eth1)
- eth_env_set_enetaddr("eth1addr", enetaddr);
+ return eth_env_set_enetaddr("eth1addr", enetaddr);
}
+ return -ENXIO;
+}
+
+int setup_mac_address(void)
+{
+ if (dh_stm32_setup_ethaddr())
+ log_err("%s: Unable to setup ethaddr!\n", __func__);
+
+ if (dh_stm32_setup_eth1addr())
+ log_err("%s: Unable to setup eth1addr!\n", __func__);
+
return 0;
}
+++ /dev/null
-if TARGET_IDS8313
-
-config SYS_BOARD
- default "ids8313"
-
-config SYS_VENDOR
- default "ids"
-
-config SYS_CONFIG_NAME
- default "ids8313"
-
-endif
+++ /dev/null
-IDS8313 BOARD
-M: Heiko Schocher <hs@denx.de>
-S: Maintained
-F: board/ids/ids8313/
-F: include/configs/ids8313.h
-F: configs/ids8313_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013
-# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
-
-obj-y = ids8313.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (c) 2011 IDS GmbH, Germany
- * ids8313.c - ids8313 board support.
- *
- * Sergej Stepanov <ste@ids.de>
- * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <spi.h>
-#include <asm/bitops.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-/** CPLD contains the info about:
- * - board type: *pCpld & 0xF0
- * - hw-revision: *pCpld & 0x0F
- * - cpld-revision: *pCpld+1
- */
-int checkboard(void)
-{
- char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
- u8 u8Vers = readb(pcpld);
- u8 u8Revs = readb(pcpld + 1);
-
- printf("Board: ");
- switch (u8Vers & 0xF0) {
- case '\x40':
- printf("CU73X");
- break;
- case '\x50':
- printf("CC73X");
- break;
- default:
- printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
- return 0;
- }
- printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
- u8Vers & 0x0F, u8Revs & 0xFF);
- return 0;
-}
-
-/*
- * fixed sdram init
- */
-int fixed_sdram(unsigned long config)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
-
-#ifndef CONFIG_SYS_RAMBOOT
- u32 msize_log2 = __ilog2(msize);
-
- out_be32(&im->sysconf.ddrlaw[0].bar,
- (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
- out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
- out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
- sync();
-
- /*
- * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
- * or the DDR2 controller may fail to initialize correctly.
- */
- udelay(50000);
-
- out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], config);
-
- /* currently we use only one CS, so disable the other banks */
- out_be32(&im->ddr.cs_config[1], 0);
- out_be32(&im->ddr.cs_config[2], 0);
- out_be32(&im->ddr.cs_config[3], 0);
-
- out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
-
- out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
- out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
-
- out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
- out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
-
- out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
- out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
- sync();
- udelay(300);
-
- /* enable DDR controller */
- setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
- /* now check the real size */
- disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
- enable_addr_trans();
-#endif
- return msize;
-}
-
-static int setup_sdram(void)
-{
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
- long int size_01, size_02;
-
- size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
- size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
-
- if (size_01 > size_02)
- msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
- else
- msize = size_02;
-
- return msize;
-}
-
-int dram_init(void)
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize = 0;
-
- if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- msize = setup_sdram();
-
- out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
- out_be32(&lbc->mrtpr, 0x20000000);
- sync();
-
- gd->ram_size = msize;
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-/* gpio mask for spi_cs */
-#define IDSCPLD_SPI_CS_MASK 0x00000001
-/* spi_cs multiplexed through cpld */
-#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
-
-#if defined(CONFIG_MISC_INIT_R)
-/* srp umcr mask for rts */
-#define IDSUMCR_RTS_MASK 0x04
-int misc_init_r(void)
-{
- /*srp*/
- duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
- duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
-
- gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
- u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
-
- /* deactivate spi_cs channels */
- out_8(spi_base, 0);
- /* deactivate the spi_cs */
- setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
- /*srp - deactivate rts*/
- out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
- out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
-
-
- gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MPC8XXX_SPI
-/*
- * The following are used to control the SPI chip selects
- */
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus == 0 && ((cs >= 0) && (cs <= 2));
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
- u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
-
- /* select the spi_cs channel */
- out_8(spi_base, 1 << slave->cs);
- /* activate the spi_cs */
- clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
- u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
-
- /* select the spi_cs channel */
- out_8(spi_base, 1 << slave->cs);
- /* deactivate the spi_cs */
- setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
-}
-#endif
#include <dm/ofnode.h>
#include <tee/optee.h>
-#ifndef CONFIG_SYS_FDT_PAD
-#define CONFIG_SYS_FDT_PAD 0x3000
-#endif
-
/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
#define FDT_RAMDISK_OVERHEAD 0x80
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
# CONFIG_SYS_MALLOC_F is not set
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=5
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=5
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_BOOTCOUNT_ADDR=0x9
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_ENV_ADDR=0xFFFC0000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_IDS8313=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="INITRAM"
-CONFIG_BAT1_BASE=0xFD000000
-CONFIG_BAT1_LENGTH_256_KBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFF800000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR"
-CONFIG_BAT5_BASE=0xF0000000
-CONFIG_BAT5_LENGTH_128_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="NAND_MRAM_CPLD"
-CONFIG_BAT6_BASE=0xE0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_GUARDED=y
-CONFIG_BAT6_DCACHE_GUARDED=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_NAND_LBLAWBAR_PRELIM_1=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFF800000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE1000000
-CONFIG_LBLAW1_NAME="NAND"
-CONFIG_LBLAW1_LENGTH_32_KBYTES=y
-CONFIG_LBLAW2=y
-CONFIG_LBLAW2_BASE=0xE2000000
-CONFIG_LBLAW2_NAME="MRAM"
-CONFIG_LBLAW2_LENGTH_128_KBYTES=y
-CONFIG_LBLAW3=y
-CONFIG_LBLAW3_BASE=0xE3000000
-CONFIG_LBLAW3_NAME="CPLD"
-CONFIG_LBLAW3_LENGTH_32_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFF800000
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_SCY_10=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="NAND"
-CONFIG_BR1_OR1_BASE=0xE1000000
-CONFIG_BR1_ERRORCHECKING_BOTH=y
-CONFIG_BR1_MACHINE_FCM=y
-CONFIG_OR1_SCY_4=y
-CONFIG_OR1_PGS_LARGE=y
-CONFIG_OR1_CSCT_8_CYCLE=y
-CONFIG_OR1_CST_ONE_CLOCK=y
-CONFIG_OR1_CHT_TWO_CLOCK=y
-CONFIG_OR1_RST_ONE_CLOCK=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR2_OR2=y
-CONFIG_BR2_OR2_NAME="MRAM"
-CONFIG_BR2_OR2_BASE=0xE2000000
-CONFIG_OR2_AM_128_KBYTES=y
-CONFIG_OR2_SCY_7=y
-CONFIG_OR2_CSNT_EARLIER=y
-CONFIG_OR2_ACS_QUARTER_CYCLE_EARLIER=y
-CONFIG_OR2_TRLX_RELAXED=y
-CONFIG_ELBC_BR3_OR3=y
-CONFIG_BR3_OR3_NAME="CPLD"
-CONFIG_BR3_OR3_BASE=0xE3000000
-CONFIG_OR3_SCY_1=y
-CONFIG_OR3_CSNT_EARLIER=y
-CONFIG_OR3_TRLX_RELAXED=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_LCRR_EADC_1=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_SYS_BARGSIZE=1024
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=1
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n"
-CONFIG_AUTOBOOT_DELAY_STR="ids"
-CONFIG_BOOT_RETRY=y
-CONFIG_BOOT_RETRY_TIME=900
-CONFIG_BOOT_RETRY_MIN=30
-CONFIG_RESET_TO_RETRY=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run boot_cramfs"
-CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="echo;echo Type \"run nfsboot\" to mount root filesystem over NFS;echo"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_CBSIZE=1024
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_ENV_FLAGS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=ff800000.flash,nand0=e1000000.flash"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:7m(dum),768k(BOOT-BIN),128k(BOOT-ENV),128k(BOOT-REDENV);e1000000.flash:-(ubi)"
-CONFIG_CMD_UBI=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR_REDUND=0xFFFE0000
-CONFIG_USE_BOOTFILE=y
-CONFIG_BOOTFILE="ids8313/uImage"
-CONFIG_USE_ETHPRIME=y
-CONFIG_ETHPRIME="TSEC1"
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_I2C=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800801
-CONFIG_SYS_OR0_PRELIM=0xFF8008A7
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE1000C21
-CONFIG_SYS_OR1_PRELIM=0xFFFF87CE
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xE2000801
-CONFIG_SYS_OR2_PRELIM=0xFFFE0C74
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xE3000801
-CONFIG_SYS_OR3_PRELIM=0xFFFF8814
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_FSL=y
-CONFIG_SYS_FSL_I2C_OFFSET=0x3100
-CONFIG_SYS_I2C_SLAVE=0x7F
-CONFIG_SYS_I2C_SPEED=400000
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_MAX_FLASH_SECT=128
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_FSL_ELBC=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-# CONFIG_PCI is not set
-CONFIG_RTC_PCF8563=y
-CONFIG_SYS_NS16550=y
-CONFIG_WATCHDOG=y
-CONFIG_JFFS2_NAND=y
-CONFIG_OF_LIBFDT=y
CONFIG_SYS_CACHE_STASHING=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=2
CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_KM_IVM_BUS=2
CONFIG_MP=y
CONFIG_ARMV8_PSCI_RELOCATE=y
CONFIG_SYS_LOAD_ADDR=0x82000000
CONFIG_AHCI=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_NXP_ESBC=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_ADDR=0x20500000
CONFIG_AHCI=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_VID_FLS_ENV="ls1088ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_FSL_QIXIS=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2160aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2160ardb_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_VID_FLS_ENV="lx2162aqds_vdd_mv"
CONFIG_VOL_MONITOR_LTC3882_READ=y
CONFIG_VOL_MONITOR_LTC3882_SET=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=4
CONFIG_FSL_QIXIS=y
CONFIG_REMAKE_ELF=y
CONFIG_MP=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_TARGET_SNAPPER9260=y
-CONFIG_AT91_GPIO_PULLUP=y
-CONFIG_ATMEL_LEGACY=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_LOAD_ADDR=0x23000000
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_RESET_PHY_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="Snapper> "
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=282
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-# CONFIG_CMD_MDIO is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RETRY_COUNT=20
-CONFIG_TFTP_PORT=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_AT91_GPIO=y
-CONFIG_CMD_PCA953X=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_MACB=y
-CONFIG_RMII=y
-CONFIG_ATMEL_USART=y
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x21f00000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_TARGET_SNAPPER9260=y
-CONFIG_AT91_GPIO_PULLUP=y
-CONFIG_ATMEL_LEGACY=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x40000
-CONFIG_ENV_OFFSET=0x80000
-CONFIG_SYS_LOAD_ADDR=0x23000000
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 ip=any"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_RESET_PHY_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_BOOTFILESIZE=y
-CONFIG_CMD_MII=y
-# CONFIG_CMD_MDIO is not set
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RETRY_COUNT=20
-CONFIG_TFTP_PORT=y
-CONFIG_TFTP_TSIZE=y
-CONFIG_AT91_GPIO=y
-CONFIG_CMD_PCA953X=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SOFT=y
-CONFIG_SYS_I2C_SOFT_SLAVE=0x7F
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_MACB=y
-CONFIG_RMII=y
-CONFIG_ATMEL_USART=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_TEN64_CONTROLLER=y
CONFIG_AHCI=y
+CONFIG_SYS_FSL_NUM_CC_PLLS=3
CONFIG_DISTRO_DEFAULTS=y
CONFIG_MP=y
CONFIG_FIT_VERBOSE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE=y
CONFIG_FSL_USDHC=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_I2C=y
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
+config SYS_FSL_MAX_NUM_OF_SEC
+ int "Number of job rings in the CAAM"
+ depends on FSL_CAAM
+ default 1
+
config CAAM_64BIT
bool
default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
bool
+config SYS_FSL_OTHER_DDR_NUM_CTRLS
+ bool
+
menu "Freescale DDR controllers"
depends on SYS_FSL_DDR
int "Number of DIMM slots per controller"
default 1
+config SYS_FSL_DDR_MAIN_NUM_CTRLS
+ int "Number of controllers used as main memory"
+ default SYS_NUM_DDR_CTLRS
+
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
Controller) found on numerous Freescale/NXP SoCs.
+config SYS_FSL_ESDHC_HAS_DDR_MODE
+ bool "i.MX eSDHC controller supports DDR mode"
+ depends on FSL_ESDHC_IMX
+
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT
help
QBman fixups to allow deep sleep in DPAA 1 SOCs
+config SYS_FSL_QMAN_V3
+ bool # QMAN version 3
+ depends on SYS_DPAA_QBMAN
+
config TSEC_ENET
select PHYLIB
bool "Enable Three-Speed Ethernet Controller"
obj-$(CONFIG_RTL8169) += rtl8169.o
obj-$(CONFIG_SH_ETHER) += sh_eth.o
obj-$(CONFIG_SJA1105) += sja1105.o
-obj-$(CONFIG_SMC91111) += smc91111.o
obj-$(CONFIG_SMC911X) += smc911x.o
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*------------------------------------------------------------------------
- . smc91111.c
- . This is a driver for SMSC's 91C111 single-chip Ethernet device.
- .
- . (C) Copyright 2002
- . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- . Rolf Offermanns <rof@sysgo.de>
- .
- . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- . Developed by Simple Network Magic Corporation (SNMC)
- . Copyright (C) 1996 by Erik Stahlman (ES)
- .
- .
- . Information contained in this file was obtained from the LAN91C111
- . manual from SMC. To get a copy, if you really want one, you can find
- . information under www.smsc.com.
- .
- .
- . "Features" of the SMC chip:
- . Integrated PHY/MAC for 10/100BaseT Operation
- . Supports internal and external MII
- . Integrated 8K packet memory
- . EEPROM interface for configuration
- .
- . Arguments:
- . io = for the base address
- . irq = for the IRQ
- .
- . author:
- . Erik Stahlman ( erik@vt.edu )
- . Daris A Nevil ( dnevil@snmc.com )
- .
- .
- . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
- .
- . Sources:
- . o SMSC LAN91C111 databook (www.smsc.com)
- . o smc9194.c by Erik Stahlman
- . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
- .
- . History:
- . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
- . 10/17/01 Marco Hasewinkel Modify for DNP/1110
- . 07/25/01 Woojung Huh Modify for ADS Bitsy
- . 04/25/01 Daris A Nevil Initial public release through SMSC
- . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
- ----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <command.h>
-#include <config.h>
-#include <malloc.h>
-#include <linux/delay.h>
-#include "smc91111.h"
-#include <net.h>
-
-/* Use power-down feature of the chip */
-#define POWER_DOWN 0
-
-#define NO_AUTOPROBE
-
-#define SMC_DEBUG 0
-
-#if SMC_DEBUG > 1
-static const char version[] =
- "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
-#endif
-
-/* Autonegotiation timeout in seconds */
-#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
-#define CONFIG_SMC_AUTONEG_TIMEOUT 10
-#endif
-
-/*------------------------------------------------------------------------
- .
- . Configuration options, for the experienced user to change.
- .
- -------------------------------------------------------------------------*/
-
-/*
- . Wait time for memory to be free. This probably shouldn't be
- . tuned that much, as waiting for this means nothing else happens
- . in the system
-*/
-#define MEMORY_WAIT_TIME 16
-
-
-#if (SMC_DEBUG > 2 )
-#define PRINTK3(args...) printf(args)
-#else
-#define PRINTK3(args...)
-#endif
-
-#if SMC_DEBUG > 1
-#define PRINTK2(args...) printf(args)
-#else
-#define PRINTK2(args...)
-#endif
-
-#ifdef SMC_DEBUG
-#define PRINTK(args...) printf(args)
-#else
-#define PRINTK(args...)
-#endif
-
-
-/*------------------------------------------------------------------------
- .
- . The internal workings of the driver. If you are changing anything
- . here with the SMC stuff, you should have the datasheet and know
- . what you are doing.
- .
- -------------------------------------------------------------------------*/
-
-/* Memory sizing constant */
-#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
-
-#ifndef CONFIG_SMC91111_BASE
-#error "SMC91111 Base address must be passed to initialization funciton"
-/* #define CONFIG_SMC91111_BASE 0x20000300 */
-#endif
-
-#define SMC_DEV_NAME "SMC91111"
-#define SMC_PHY_ADDR 0x0000
-#define SMC_ALLOC_MAX_TRY 5
-#define SMC_TX_TIMEOUT 30
-
-#define SMC_PHY_CLOCK_DELAY 1000
-
-#define ETH_ZLEN 60
-
-#ifdef CONFIG_SMC_USE_32_BIT
-#define USE_32_BIT 1
-#else
-#undef USE_32_BIT
-#endif
-
-#ifdef SHARED_RESOURCES
-extern void swap_to(int device_id);
-#else
-# define swap_to(x)
-#endif
-
-#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure(struct eth_device *dev);
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-/*
- ------------------------------------------------------------
- .
- . Internal routines
- .
- ------------------------------------------------------------
-*/
-
-#ifdef CONFIG_SMC_USE_IOFUNCS
-/*
- * input and output functions
- *
- * Implemented due to inx,outx macros accessing the device improperly
- * and putting the device into an unkown state.
- *
- * For instance, on Sharp LPD7A400 SDK, affects were chip memory
- * could not be free'd (hence the alloc failures), duplicate packets,
- * packets being corrupt (shifted) on the wire, etc. Switching to the
- * inx,outx functions fixed this problem.
- */
-
-static inline word SMC_inw(struct eth_device *dev, dword offset)
-{
- word v;
- v = *((volatile word*)(dev->iobase + offset));
- barrier(); *(volatile u32*)(0xc0000000);
- return v;
-}
-
-static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
-{
- *((volatile word*)(dev->iobase + offset)) = value;
- barrier(); *(volatile u32*)(0xc0000000);
-}
-
-static inline byte SMC_inb(struct eth_device *dev, dword offset)
-{
- word _w;
-
- _w = SMC_inw(dev, offset & ~((dword)1));
- return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
-}
-
-static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
-{
- word _w;
-
- _w = SMC_inw(dev, offset & ~((dword)1));
- if (offset & 1)
- *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
- (value<<8) | (_w & 0x00ff);
- else
- *((volatile word*)(dev->iobase + offset)) =
- value | (_w & 0xff00);
-}
-
-static inline void SMC_insw(struct eth_device *dev, dword offset,
- volatile uchar* buf, dword len)
-{
- volatile word *p = (volatile word *)buf;
-
- while (len-- > 0) {
- *p++ = SMC_inw(dev, offset);
- barrier();
- *((volatile u32*)(0xc0000000));
- }
-}
-
-static inline void SMC_outsw(struct eth_device *dev, dword offset,
- uchar* buf, dword len)
-{
- volatile word *p = (volatile word *)buf;
-
- while (len-- > 0) {
- SMC_outw(dev, *p++, offset);
- barrier();
- *(volatile u32*)(0xc0000000);
- }
-}
-#endif /* CONFIG_SMC_USE_IOFUNCS */
-
-/*
- . A rather simple routine to print out a packet for debugging purposes.
-*/
-#if SMC_DEBUG > 2
-static void print_packet( byte *, int );
-#endif
-
-#define tx_done(dev) 1
-
-static int poll4int (struct eth_device *dev, byte mask, int timeout)
-{
- int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
- int is_timeout = 0;
- word old_bank = SMC_inw (dev, BSR_REG);
-
- PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK (dev, 2);
- while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
- if (get_timer (0) >= tmo) {
- is_timeout = 1;
- break;
- }
- }
-
- /* restore old bank selection */
- SMC_SELECT_BANK (dev, old_bank);
-
- if (is_timeout)
- return 1;
- else
- return 0;
-}
-
-/* Only one release command at a time, please */
-static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
-{
- int count = 0;
-
- /* assume bank 2 selected */
- while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay(1); /* Wait until not busy */
- if (++count > 200)
- break;
- }
-}
-
-/*
- . Function: smc_reset( void )
- . Purpose:
- . This sets the SMC91111 chip to its normal state, hopefully from whatever
- . mess that any other DOS driver has put it in.
- .
- . Maybe I should reset more registers to defaults in here? SOFTRST should
- . do that for me.
- .
- . Method:
- . 1. send a SOFT RESET
- . 2. wait for it to finish
- . 3. enable autorelease mode
- . 4. reset the memory management unit
- . 5. clear all interrupts
- .
-*/
-static void smc_reset (struct eth_device *dev)
-{
- PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
-
- /* This resets the registers mostly to defaults, but doesn't
- affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK (dev, 0);
- SMC_outw (dev, RCR_SOFTRST, RCR_REG);
-
- /* Setup the Configuration Register */
- /* This is necessary because the CONFIG_REG is not affected */
- /* by a soft reset */
-
- SMC_SELECT_BANK (dev, 1);
-#if defined(CONFIG_SMC91111_EXT_PHY)
- SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
-#else
- SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
-#endif
-
-
- /* Release from possible power-down state */
- /* Configuration register is not affected by Soft Reset */
- SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
- CONFIG_REG);
-
- SMC_SELECT_BANK (dev, 0);
-
- /* this should pause enough for the chip to be happy */
- udelay(10);
-
- /* Disable transmit and receive functionality */
- SMC_outw (dev, RCR_CLEAR, RCR_REG);
- SMC_outw (dev, TCR_CLEAR, TCR_REG);
-
- /* set the control register */
- SMC_SELECT_BANK (dev, 1);
- SMC_outw (dev, CTL_DEFAULT, CTL_REG);
-
- /* Reset the MMU */
- SMC_SELECT_BANK (dev, 2);
- smc_wait_mmu_release_complete (dev);
- SMC_outw (dev, MC_RESET, MMU_CMD_REG);
- while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
- udelay(1); /* Wait until not busy */
-
- /* Note: It doesn't seem that waiting for the MMU busy is needed here,
- but this is a place where future chipsets _COULD_ break. Be wary
- of issuing another MMU command right after this */
-
- /* Disable all interrupts */
- SMC_outb (dev, 0, IM_REG);
-}
-
-/*
- . Function: smc_enable
- . Purpose: let the chip talk to the outside work
- . Method:
- . 1. Enable the transmitter
- . 2. Enable the receiver
- . 3. Enable interrupts
-*/
-static void smc_enable(struct eth_device *dev)
-{
- PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
- SMC_SELECT_BANK( dev, 0 );
- /* see the header file for options in TCR/RCR DEFAULT*/
- SMC_outw( dev, TCR_DEFAULT, TCR_REG );
- SMC_outw( dev, RCR_DEFAULT, RCR_REG );
-
- /* clear MII_DIS */
-/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
-}
-
-/*
- . Function: smc_halt
- . Purpose: closes down the SMC91xxx chip.
- . Method:
- . 1. zero the interrupt mask
- . 2. clear the enable receive flag
- . 3. clear the enable xmit flags
- .
- . TODO:
- . (1) maybe utilize power down mode.
- . Why not yet? Because while the chip will go into power down mode,
- . the manual says that it will wake up in response to any I/O requests
- . in the register space. Empirical results do not show this working.
-*/
-static void smc_halt(struct eth_device *dev)
-{
- PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
-
- /* no more interrupts for me */
- SMC_SELECT_BANK( dev, 2 );
- SMC_outb( dev, 0, IM_REG );
-
- /* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK( dev, 0 );
- SMC_outb( dev, RCR_CLEAR, RCR_REG );
- SMC_outb( dev, TCR_CLEAR, TCR_REG );
-
- swap_to(FLASH);
-}
-
-
-/*
- . Function: smc_send(struct net_device * )
- . Purpose:
- . This sends the actual packet to the SMC9xxx chip.
- .
- . Algorithm:
- . First, see if a saved_skb is available.
- . ( this should NOT be called if there is no 'saved_skb'
- . Now, find the packet number that the chip allocated
- . Point the data pointers at it in memory
- . Set the length word in the chip's memory
- . Dump the packet to chip memory
- . Check if a last byte is needed ( odd length packet )
- . if so, set the control flag right
- . Tell the card to send it
- . Enable the transmit interrupt, so I know if it failed
- . Free the kernel data if I actually sent it.
-*/
-static int smc_send(struct eth_device *dev, void *packet, int packet_length)
-{
- byte packet_no;
- byte *buf;
- int length;
- int numPages;
- int try = 0;
- int time_out;
- byte status;
- byte saved_pnr;
- word saved_ptr;
-
- /* save PTR and PNR registers before manipulation */
- SMC_SELECT_BANK (dev, 2);
- saved_pnr = SMC_inb( dev, PN_REG );
- saved_ptr = SMC_inw( dev, PTR_REG );
-
- PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
-
- length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
-
- /* allocate memory
- ** The MMU wants the number of pages to be the number of 256 bytes
- ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
- **
- ** The 91C111 ignores the size bits, but the code is left intact
- ** for backwards and future compatibility.
- **
- ** Pkt size for allocating is data length +6 (for additional status
- ** words, length and ctl!)
- **
- ** If odd size then last byte is included in this header.
- */
- numPages = ((length & 0xfffe) + 6);
- numPages >>= 8; /* Divide by 256 */
-
- if (numPages > 7) {
- printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
- return 0;
- }
-
- /* now, try to allocate the memory */
- SMC_SELECT_BANK (dev, 2);
- SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
-
- /* FIXME: the ALLOC_INT bit never gets set *
- * so the following will always give a *
- * memory allocation error. *
- * same code works in armboot though *
- * -ro
- */
-
-again:
- try++;
- time_out = MEMORY_WAIT_TIME;
- do {
- status = SMC_inb (dev, SMC91111_INT_REG);
- if (status & IM_ALLOC_INT) {
- /* acknowledge the interrupt */
- SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
- break;
- }
- } while (--time_out);
-
- if (!time_out) {
- PRINTK2 ("%s: memory allocation, try %d failed ...\n",
- SMC_DEV_NAME, try);
- if (try < SMC_ALLOC_MAX_TRY)
- goto again;
- else
- return 0;
- }
-
- PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
- SMC_DEV_NAME, try);
-
- buf = (byte *) packet;
-
- /* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb (dev, AR_REG);
- if (packet_no & AR_FAILED) {
- /* or isn't there? BAD CHIP! */
- printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
- return 0;
- }
-
- /* we have a packet address, so tell the card to use it */
- SMC_outb (dev, packet_no, PN_REG);
-
- /* do not write new ptr value if Write data fifo not empty */
- while ( saved_ptr & PTR_NOTEMPTY )
- printf ("Write data fifo not empty!\n");
-
- /* point to the beginning of the packet */
- SMC_outw (dev, PTR_AUTOINC, PTR_REG);
-
- PRINTK3 ("%s: Trying to xmit packet of length %x\n",
- SMC_DEV_NAME, length);
-
-#if SMC_DEBUG > 2
- printf ("Transmitting Packet\n");
- print_packet (buf, length);
-#endif
-
- /* send the packet length ( +6 for status, length and ctl byte )
- and the status word ( set to zeros ) */
-#ifdef USE_32_BIT
- SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
-#else
- SMC_outw (dev, 0, SMC91111_DATA_REG);
- /* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
-#endif
-
- /* send the actual data
- . I _think_ it's faster to send the longs first, and then
- . mop up by sending the last word. It depends heavily
- . on alignment, at least on the 486. Maybe it would be
- . a good idea to check which is optimal? But that could take
- . almost as much time as is saved?
- */
-#ifdef USE_32_BIT
- SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
- if (length & 0x2)
- SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
- SMC91111_DATA_REG);
-#else
- SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
-#endif /* USE_32_BIT */
-
- /* Send the last byte, if there is one. */
- if ((length & 1) == 0) {
- SMC_outw (dev, 0, SMC91111_DATA_REG);
- } else {
- SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
- }
-
- /* and let the chipset deal with it */
- SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
-
- /* poll for TX INT */
- /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
- /* poll for TX_EMPTY INT - autorelease enabled */
- if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
- /* sending failed */
- PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
-
- /* release packet */
- /* no need to release, MMU does that now */
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay(10);
- }
-
- PRINTK2 ("MMU ready\n");
-
-
- return 0;
- } else {
- /* ack. int */
- SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
- /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
- PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
- length);
-
- /* release packet */
- /* no need to release, MMU does that now */
-
- /* wait for MMU getting ready (low) */
- while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
- udelay(10);
- }
-
- PRINTK2 ("MMU ready\n");
-
-
- }
-
- /* restore previously saved registers */
- SMC_outb( dev, saved_pnr, PN_REG );
- SMC_outw( dev, saved_ptr, PTR_REG );
-
- return length;
-}
-
-static int smc_write_hwaddr(struct eth_device *dev)
-{
- int i;
-
- swap_to(ETHERNET);
- SMC_SELECT_BANK (dev, 1);
-#ifdef USE_32_BIT
- for (i = 0; i < 6; i += 2) {
- word address;
-
- address = dev->enetaddr[i + 1] << 8;
- address |= dev->enetaddr[i];
- SMC_outw(dev, address, (ADDR0_REG + i));
- }
-#else
- for (i = 0; i < 6; i++)
- SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
-#endif
- swap_to(FLASH);
- return 0;
-}
-
-/*
- * Open and Initialize the board
- *
- * Set up everything, reset the card, etc ..
- *
- */
-static int smc_init(struct eth_device *dev, struct bd_info *bd)
-{
- swap_to(ETHERNET);
-
- PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
-
- /* reset the hardware */
- smc_reset (dev);
- smc_enable (dev);
-
- /* Configure the PHY */
-#ifndef CONFIG_SMC91111_EXT_PHY
- smc_phy_configure (dev);
-#endif
-
- /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
-/* SMC_SELECT_BANK(dev, 0); */
-/* SMC_outw(dev, 0, RPC_REG); */
-
- printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
-
- return 0;
-}
-
-/*-------------------------------------------------------------
- .
- . smc_rcv - receive a packet from the card
- .
- . There is ( at least ) a packet waiting to be read from
- . chip-memory.
- .
- . o Read the status
- . o If an error, record it
- . o otherwise, read in the packet
- --------------------------------------------------------------
-*/
-static int smc_rcv(struct eth_device *dev)
-{
- int packet_number;
- word status;
- word packet_length;
- int is_error = 0;
-#ifdef USE_32_BIT
- dword stat_len;
-#endif
- byte saved_pnr;
- word saved_ptr;
-
- SMC_SELECT_BANK(dev, 2);
- /* save PTR and PTR registers */
- saved_pnr = SMC_inb( dev, PN_REG );
- saved_ptr = SMC_inw( dev, PTR_REG );
-
- packet_number = SMC_inw( dev, RXFIFO_REG );
-
- if ( packet_number & RXFIFO_REMPTY ) {
-
- return 0;
- }
-
- PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
- /* start reading from the start of the packet */
- SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
-
- /* First two words are status and packet_length */
-#ifdef USE_32_BIT
- stat_len = SMC_inl(dev, SMC91111_DATA_REG);
- status = stat_len & 0xffff;
- packet_length = stat_len >> 16;
-#else
- status = SMC_inw( dev, SMC91111_DATA_REG );
- packet_length = SMC_inw( dev, SMC91111_DATA_REG );
-#endif
-
- packet_length &= 0x07ff; /* mask off top bits */
-
- PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
-
- if ( !(status & RS_ERRORS ) ){
- /* Adjust for having already read the first two words */
- packet_length -= 4; /*4; */
-
-
- /* set odd length for bug in LAN91C111, */
- /* which never sets RS_ODDFRAME */
- /* TODO ? */
-
-
-#ifdef USE_32_BIT
- PRINTK3(" Reading %d dwords (and %d bytes)\n",
- packet_length >> 2, packet_length & 3 );
- /* QUESTION: Like in the TX routine, do I want
- to send the DWORDs or the bytes first, or some
- mixture. A mixture might improve already slow PIO
- performance */
- SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
- packet_length >> 2);
- /* read the left over bytes */
- if (packet_length & 3) {
- int i;
-
- byte *tail = (byte *)(net_rx_packets[0] +
- (packet_length & ~3));
- dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
- for (i=0; i<(packet_length & 3); i++)
- *tail++ = (byte) (leftover >> (8*i)) & 0xff;
- }
-#else
- PRINTK3(" Reading %d words and %d byte(s)\n",
- (packet_length >> 1 ), packet_length & 1 );
- SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
- packet_length >> 1);
-
-#endif /* USE_32_BIT */
-
-#if SMC_DEBUG > 2
- printf("Receiving Packet\n");
- print_packet(net_rx_packets[0], packet_length);
-#endif
- } else {
- /* error ... */
- /* TODO ? */
- is_error = 1;
- }
-
- while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
- udelay(1); /* Wait until not busy */
-
- /* error or good, tell the card to get rid of this packet */
- SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
-
- while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
- udelay(1); /* Wait until not busy */
-
- /* restore saved registers */
- SMC_outb( dev, saved_pnr, PN_REG );
- SMC_outw( dev, saved_ptr, PTR_REG );
-
- if (!is_error) {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[0], packet_length);
- return packet_length;
- } else {
- return 0;
- }
-
-}
-
-
-#if 0
-/*------------------------------------------------------------
- . Modify a bit in the LAN91C111 register set
- .-------------------------------------------------------------*/
-static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
- unsigned int bit, int val)
-{
- word regval;
-
- SMC_SELECT_BANK( dev, bank );
-
- regval = SMC_inw( dev, reg );
- if (val)
- regval |= bit;
- else
- regval &= ~bit;
-
- SMC_outw( dev, regval, 0 );
- return(regval);
-}
-
-
-/*------------------------------------------------------------
- . Retrieve a bit in the LAN91C111 register set
- .-------------------------------------------------------------*/
-static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
-{
- SMC_SELECT_BANK( dev, bank );
- if ( SMC_inw( dev, reg ) & bit)
- return(1);
- else
- return(0);
-}
-
-
-/*------------------------------------------------------------
- . Modify a LAN91C111 register (word access only)
- .-------------------------------------------------------------*/
-static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
-{
- SMC_SELECT_BANK( dev, bank );
- SMC_outw( dev, val, reg );
-}
-
-
-/*------------------------------------------------------------
- . Retrieve a LAN91C111 register (word access only)
- .-------------------------------------------------------------*/
-static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
-{
- SMC_SELECT_BANK( dev, bank );
- return(SMC_inw( dev, reg ));
-}
-
-#endif /* 0 */
-
-/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
-
-#if (SMC_DEBUG > 2 )
-
-/*------------------------------------------------------------
- . Debugging function for viewing MII Management serial bitstream
- .-------------------------------------------------------------*/
-static void smc_dump_mii_stream (byte * bits, int size)
-{
- int i;
-
- printf ("BIT#:");
- for (i = 0; i < size; ++i) {
- printf ("%d", i % 10);
- }
-
- printf ("\nMDOE:");
- for (i = 0; i < size; ++i) {
- if (bits[i] & MII_MDOE)
- printf ("1");
- else
- printf ("0");
- }
-
- printf ("\nMDO :");
- for (i = 0; i < size; ++i) {
- if (bits[i] & MII_MDO)
- printf ("1");
- else
- printf ("0");
- }
-
- printf ("\nMDI :");
- for (i = 0; i < size; ++i) {
- if (bits[i] & MII_MDI)
- printf ("1");
- else
- printf ("0");
- }
-
- printf ("\n");
-}
-#endif
-
-/*------------------------------------------------------------
- . Reads a register from the MII Management serial interface
- .-------------------------------------------------------------*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
-{
- int oldBank;
- int i;
- byte mask;
- word mii_reg;
- byte bits[64];
- int clk_idx = 0;
- int input_idx;
- word phydata;
- byte phyaddr = SMC_PHY_ADDR;
-
- /* 32 consecutive ones on MDO to establish sync */
- for (i = 0; i < 32; ++i)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
-
- /* Start code <01> */
- bits[clk_idx++] = MII_MDOE;
- bits[clk_idx++] = MII_MDOE | MII_MDO;
-
- /* Read command <10> */
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- bits[clk_idx++] = MII_MDOE;
-
- /* Output the PHY address, msb first */
- mask = (byte) 0x10;
- for (i = 0; i < 5; ++i) {
- if (phyaddr & mask)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- else
- bits[clk_idx++] = MII_MDOE;
-
- /* Shift to next lowest bit */
- mask >>= 1;
- }
-
- /* Output the phy register number, msb first */
- mask = (byte) 0x10;
- for (i = 0; i < 5; ++i) {
- if (phyreg & mask)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- else
- bits[clk_idx++] = MII_MDOE;
-
- /* Shift to next lowest bit */
- mask >>= 1;
- }
-
- /* Tristate and turnaround (2 bit times) */
- bits[clk_idx++] = 0;
- /*bits[clk_idx++] = 0; */
-
- /* Input starts at this bit time */
- input_idx = clk_idx;
-
- /* Will input 16 bits */
- for (i = 0; i < 16; ++i)
- bits[clk_idx++] = 0;
-
- /* Final clock bit */
- bits[clk_idx++] = 0;
-
- /* Save the current bank */
- oldBank = SMC_inw (dev, BANK_SELECT);
-
- /* Select bank 3 */
- SMC_SELECT_BANK (dev, 3);
-
- /* Get the current MII register value */
- mii_reg = SMC_inw (dev, MII_REG);
-
- /* Turn off all MII Interface bits */
- mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
-
- /* Clock all 64 cycles */
- for (i = 0; i < sizeof bits; ++i) {
- /* Clock Low - output data */
- SMC_outw (dev, mii_reg | bits[i], MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
-
-
- /* Clock Hi - input data */
- SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
- }
-
- /* Return to idle state */
- /* Set clock to low, data to low, and output tristated */
- SMC_outw (dev, mii_reg, MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
-
- /* Restore original bank select */
- SMC_SELECT_BANK (dev, oldBank);
-
- /* Recover input data */
- phydata = 0;
- for (i = 0; i < 16; ++i) {
- phydata <<= 1;
-
- if (bits[input_idx++] & MII_MDI)
- phydata |= 0x0001;
- }
-
-#if (SMC_DEBUG > 2 )
- printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
- phyaddr, phyreg, phydata);
- smc_dump_mii_stream (bits, sizeof bits);
-#endif
-
- return (phydata);
-}
-
-
-/*------------------------------------------------------------
- . Writes a register to the MII Management serial interface
- .-------------------------------------------------------------*/
-static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
- word phydata)
-{
- int oldBank;
- int i;
- word mask;
- word mii_reg;
- byte bits[65];
- int clk_idx = 0;
- byte phyaddr = SMC_PHY_ADDR;
-
- /* 32 consecutive ones on MDO to establish sync */
- for (i = 0; i < 32; ++i)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
-
- /* Start code <01> */
- bits[clk_idx++] = MII_MDOE;
- bits[clk_idx++] = MII_MDOE | MII_MDO;
-
- /* Write command <01> */
- bits[clk_idx++] = MII_MDOE;
- bits[clk_idx++] = MII_MDOE | MII_MDO;
-
- /* Output the PHY address, msb first */
- mask = (byte) 0x10;
- for (i = 0; i < 5; ++i) {
- if (phyaddr & mask)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- else
- bits[clk_idx++] = MII_MDOE;
-
- /* Shift to next lowest bit */
- mask >>= 1;
- }
-
- /* Output the phy register number, msb first */
- mask = (byte) 0x10;
- for (i = 0; i < 5; ++i) {
- if (phyreg & mask)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- else
- bits[clk_idx++] = MII_MDOE;
-
- /* Shift to next lowest bit */
- mask >>= 1;
- }
-
- /* Tristate and turnaround (2 bit times) */
- bits[clk_idx++] = 0;
- bits[clk_idx++] = 0;
-
- /* Write out 16 bits of data, msb first */
- mask = 0x8000;
- for (i = 0; i < 16; ++i) {
- if (phydata & mask)
- bits[clk_idx++] = MII_MDOE | MII_MDO;
- else
- bits[clk_idx++] = MII_MDOE;
-
- /* Shift to next lowest bit */
- mask >>= 1;
- }
-
- /* Final clock bit (tristate) */
- bits[clk_idx++] = 0;
-
- /* Save the current bank */
- oldBank = SMC_inw (dev, BANK_SELECT);
-
- /* Select bank 3 */
- SMC_SELECT_BANK (dev, 3);
-
- /* Get the current MII register value */
- mii_reg = SMC_inw (dev, MII_REG);
-
- /* Turn off all MII Interface bits */
- mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
-
- /* Clock all cycles */
- for (i = 0; i < sizeof bits; ++i) {
- /* Clock Low - output data */
- SMC_outw (dev, mii_reg | bits[i], MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
-
-
- /* Clock Hi - input data */
- SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
- }
-
- /* Return to idle state */
- /* Set clock to low, data to low, and output tristated */
- SMC_outw (dev, mii_reg, MII_REG);
- udelay(SMC_PHY_CLOCK_DELAY);
-
- /* Restore original bank select */
- SMC_SELECT_BANK (dev, oldBank);
-
-#if (SMC_DEBUG > 2 )
- printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
- phyaddr, phyreg, phydata);
- smc_dump_mii_stream (bits, sizeof bits);
-#endif
-}
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-/*------------------------------------------------------------
- . Configures the specified PHY using Autonegotiation. Calls
- . smc_phy_fixed() if the user has requested a certain config.
- .-------------------------------------------------------------*/
-#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure (struct eth_device *dev)
-{
- int timeout;
- word my_phy_caps; /* My PHY capabilities */
- word my_ad_caps; /* My Advertised capabilities */
- word status = 0; /*;my status = 0 */
-
- PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
-
- /* Reset the PHY, setting all other bits to zero */
- smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
-
- /* Wait for the reset to complete, or time out */
- timeout = 6; /* Wait up to 3 seconds */
- while (timeout--) {
- if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
- & PHY_CNTL_RST)) {
- /* reset complete */
- break;
- }
-
- mdelay(500); /* wait 500 millisecs */
- }
-
- if (timeout < 1) {
- printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
- goto smc_phy_configure_exit;
- }
-
- /* Read PHY Register 18, Status Output */
- /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
-
- /* Enable PHY Interrupts (for register 18) */
- /* Interrupts listed here are disabled */
- smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
-
- /* Configure the Receive/Phy Control register */
- SMC_SELECT_BANK (dev, 0);
- SMC_outw (dev, RPC_DEFAULT, RPC_REG);
-
- /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
- my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
- my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
-
- if (my_phy_caps & PHY_STAT_CAP_T4)
- my_ad_caps |= PHY_AD_T4;
-
- if (my_phy_caps & PHY_STAT_CAP_TXF)
- my_ad_caps |= PHY_AD_TX_FDX;
-
- if (my_phy_caps & PHY_STAT_CAP_TXH)
- my_ad_caps |= PHY_AD_TX_HDX;
-
- if (my_phy_caps & PHY_STAT_CAP_TF)
- my_ad_caps |= PHY_AD_10_FDX;
-
- if (my_phy_caps & PHY_STAT_CAP_TH)
- my_ad_caps |= PHY_AD_10_HDX;
-
- /* Update our Auto-Neg Advertisement Register */
- smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
-
- /* Read the register back. Without this, it appears that when */
- /* auto-negotiation is restarted, sometimes it isn't ready and */
- /* the link does not come up. */
- smc_read_phy_register(dev, PHY_AD_REG);
-
- PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
- PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
-
- /* Restart auto-negotiation process in order to advertise my caps */
- smc_write_phy_register (dev, PHY_CNTL_REG,
- PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
-
- /* Wait for the auto-negotiation to complete. This may take from */
- /* 2 to 3 seconds. */
- /* Wait for the reset to complete, or time out */
- timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
- while (timeout--) {
-
- status = smc_read_phy_register (dev, PHY_STAT_REG);
- if (status & PHY_STAT_ANEG_ACK) {
- /* auto-negotiate complete */
- break;
- }
-
- mdelay(500); /* wait 500 millisecs */
-
- /* Restart auto-negotiation if remote fault */
- if (status & PHY_STAT_REM_FLT) {
- printf ("%s: PHY remote fault detected\n",
- SMC_DEV_NAME);
-
- /* Restart auto-negotiation */
- printf ("%s: PHY restarting auto-negotiation\n",
- SMC_DEV_NAME);
- smc_write_phy_register (dev, PHY_CNTL_REG,
- PHY_CNTL_ANEG_EN |
- PHY_CNTL_ANEG_RST |
- PHY_CNTL_SPEED |
- PHY_CNTL_DPLX);
- }
- }
-
- if (timeout < 1) {
- printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
- }
-
- /* Fail if we detected an auto-negotiate remote fault */
- if (status & PHY_STAT_REM_FLT) {
- printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
- }
-
- /* Re-Configure the Receive/Phy Control register */
- SMC_outw (dev, RPC_DEFAULT, RPC_REG);
-
-smc_phy_configure_exit: ;
-
-}
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-#if SMC_DEBUG > 2
-static void print_packet( byte * buf, int length )
-{
- int i;
- int remainder;
- int lines;
-
- printf("Packet of length %d \n", length );
-
-#if SMC_DEBUG > 3
- lines = length / 16;
- remainder = length % 16;
-
- for ( i = 0; i < lines ; i ++ ) {
- int cur;
-
- for ( cur = 0; cur < 8; cur ++ ) {
- byte a, b;
-
- a = *(buf ++ );
- b = *(buf ++ );
- printf("%02x%02x ", a, b );
- }
- printf("\n");
- }
- for ( i = 0; i < remainder/2 ; i++ ) {
- byte a, b;
-
- a = *(buf ++ );
- b = *(buf ++ );
- printf("%02x%02x ", a, b );
- }
- printf("\n");
-#endif
-}
-#endif
-
-int smc91111_initialize(u8 dev_num, phys_addr_t base_addr)
-{
- struct smc91111_priv *priv;
- struct eth_device *dev;
- int i;
-
- priv = malloc(sizeof(*priv));
- if (!priv)
- return 0;
- dev = malloc(sizeof(*dev));
- if (!dev) {
- free(priv);
- return 0;
- }
-
- memset(dev, 0, sizeof(*dev));
- priv->dev_num = dev_num;
- dev->priv = priv;
- dev->iobase = base_addr;
-
- swap_to(ETHERNET);
- SMC_SELECT_BANK(dev, 1);
- for (i = 0; i < 6; ++i)
- dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
- swap_to(FLASH);
-
- dev->init = smc_init;
- dev->halt = smc_halt;
- dev->send = smc_send;
- dev->recv = smc_rcv;
- dev->write_hwaddr = smc_write_hwaddr;
- sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
-
- eth_register(dev);
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*------------------------------------------------------------------------
- . smc91111.h - macros for the LAN91C111 Ethernet Driver
- .
- . (C) Copyright 2002
- . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- . Rolf Offermanns <rof@sysgo.de>
- . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
- . Developed by Simple Network Magic Corporation (SNMC)
- . Copyright (C) 1996 by Erik Stahlman (ES)
- .
- . This file contains register information and access macros for
- . the LAN91C111 single chip ethernet controller. It is a modified
- . version of the smc9194.h file.
- .
- . Information contained in this file was obtained from the LAN91C111
- . manual from SMC. To get a copy, if you really want one, you can find
- . information under www.smsc.com.
- .
- . Authors
- . Erik Stahlman ( erik@vt.edu )
- . Daris A Nevil ( dnevil@snmc.com )
- .
- . History
- . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
- .
- ---------------------------------------------------------------------------*/
-#ifndef _SMC91111_H_
-#define _SMC91111_H_
-
-#include <asm/types.h>
-#include <config.h>
-#include <net.h>
-
-/*
- * This function may be called by the board specific initialisation code
- * in order to override the default mac address.
- */
-
-void smc_set_mac_addr (const unsigned char *addr);
-
-
-/* I want some simple types */
-
-typedef unsigned char byte;
-typedef unsigned short word;
-typedef unsigned long int dword;
-
-struct smc91111_priv{
- u8 dev_num;
-};
-
-/*
- . DEBUGGING LEVELS
- .
- . 0 for normal operation
- . 1 for slightly more details
- . >2 for various levels of increasingly useless information
- . 2 for interrupt tracking, status flags
- . 3 for packet info
- . 4 for complete packet dumps
-*/
-/*#define SMC_DEBUG 0 */
-
-/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
-
-#define SMC_IO_EXTENT 16
-
-#if defined(CONFIG_MS7206SE)
-#define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
-#define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
-#define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
-#define SMC_insw(a, r, b, l) \
- do { \
- int __i; \
- word *__b2 = (word *)(b); \
- for (__i = 0; __i < (l); __i++) { \
- *__b2++ = SWAB7206(SMC_inw(a, r)); \
- } \
- } while (0)
-#define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d)
-#define SMC_outb(a, d, r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((a), ((r)&(~1))); \
- if (((r) & 1)) \
- __w = (__w & 0x00ff) | (__d << 8); \
- else \
- __w = (__w & 0xff00) | (__d); \
- SMC_outw((a), __w, ((r)&(~1))); \
- })
-#define SMC_outsw(a, r, b, l) \
- do { \
- int __i; \
- word *__b2 = (word *)(b); \
- for (__i = 0; __i < (l); __i++) { \
- SMC_outw(a, SWAB7206(*__b2), r); \
- __b2++; \
- } \
- } while (0)
-#else
-
-#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
-/*
- * We have only 16 Bit PCMCIA access on Socket 0
- */
-
-#if CONFIG_ARM64
-#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
-#else
-#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
-#endif
-#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
-
-#if CONFIG_ARM64
-#define SMC_outw(a, d, r) \
- (*((volatile word*)((a)->iobase+((dword)(r)))) = d)
-#else
-#define SMC_outw(a, d, r) \
- (*((volatile word*)((a)->iobase+(r))) = d)
-#endif
-#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((a),(r)&~1); \
- __w &= ((r)&1) ? 0x00FF : 0xFF00; \
- __w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw((a),__w,(r)&~1); \
- })
-#if 0
-#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
-#else
-#define SMC_outsw(a,r,b,l) ({ int __i; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outw((a), *(__b2 + __i), r); \
- } \
- })
-#endif
-
-#if 0
-#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
-#else
-#define SMC_insw(a,r,b,l) ({ int __i ; \
- word *__b2; \
- __b2 = (word *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw((a),(r)); \
- SMC_inw((a),0); \
- }; \
- })
-#endif
-
-#endif /* CONFIG_SMC_USE_IOFUNCS */
-
-#if defined(CONFIG_SMC_USE_32_BIT)
-
-#ifdef CONFIG_XSENGINE
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
-#else
-#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
-#endif
-
-#define SMC_insl(a,r,b,l) ({ int __i ; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl((a),(r)); \
- SMC_inl((a),0); \
- }; \
- })
-
-#ifdef CONFIG_XSENGINE
-#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
-#else
-#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
-#endif
-#define SMC_outsl(a,r,b,l) ({ int __i; \
- dword *__b2; \
- __b2 = (dword *) b; \
- for (__i = 0; __i < l; __i++) { \
- SMC_outl((a), *(__b2 + __i), r); \
- } \
- })
-
-#endif /* CONFIG_SMC_USE_32_BIT */
-
-#endif
-
-/*---------------------------------------------------------------
- .
- . A description of the SMSC registers is probably in order here,
- . although for details, the SMC datasheet is invaluable.
- .
- . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
- . are accessed by writing a number into the BANK_SELECT register
- . ( I also use a SMC_SELECT_BANK macro for this ).
- .
- . The banks are configured so that for most purposes, bank 2 is all
- . that is needed for simple run time tasks.
- -----------------------------------------------------------------------*/
-
-/*
- . Bank Select Register:
- .
- . yyyy yyyy 0000 00xx
- . xx = bank number
- . yyyy yyyy = 0x33, for identification purposes.
-*/
-#define BANK_SELECT 14
-
-/* Transmit Control Register */
-/* BANK 0 */
-#define TCR_REG 0x0000 /* transmit control register */
-#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
-#define TCR_LOOP 0x0002 /* Controls output pin LBK */
-#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
-#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
-#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
-#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
-#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
-#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
-#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
-#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
-
-#define TCR_CLEAR 0 /* do NOTHING */
-/* the default settings for the TCR register : */
-/* QUESTION: do I want to enable padding of short packets ? */
-#define TCR_DEFAULT TCR_ENABLE
-
-
-/* EPH Status Register */
-/* BANK 0 */
-#define EPH_STATUS_REG 0x0002
-#define ES_TX_SUC 0x0001 /* Last TX was successful */
-#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
-#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
-#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
-#define ES_16COL 0x0010 /* 16 Collisions Reached */
-#define ES_SQET 0x0020 /* Signal Quality Error Test */
-#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
-#define ES_TXDEFR 0x0080 /* Transmit Deferred */
-#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
-#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
-#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
-#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
-#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
-#define ES_TXUNRN 0x8000 /* Tx Underrun */
-
-
-/* Receive Control Register */
-/* BANK 0 */
-#define RCR_REG 0x0004
-#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
-#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
-#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
-#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
-#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
-#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
-#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
-#define RCR_SOFTRST 0x8000 /* resets the chip */
-
-/* the normal settings for the RCR register : */
-#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
-#define RCR_CLEAR 0x0 /* set it to a base state */
-
-/* Counter Register */
-/* BANK 0 */
-#define COUNTER_REG 0x0006
-
-/* Memory Information Register */
-/* BANK 0 */
-#define MIR_REG 0x0008
-
-/* Receive/Phy Control Register */
-/* BANK 0 */
-#define RPC_REG 0x000A
-#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
-#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
-#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
-#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
-#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
-#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
-#define RPC_LED_RES (0x01) /* LED = Reserved */
-#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
-#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
-#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
-#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
-#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
-#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
-#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
-/* buggy schematic: LEDa -> yellow, LEDb --> green */
-#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
- | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
- | (RPC_LED_100_10 << RPC_LSXB_SHFT) )
-#else
-/* SMSC reference design: LEDa --> green, LEDb --> yellow */
-#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
- | (RPC_LED_100_10 << RPC_LSXA_SHFT) \
- | (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
-#endif
-
-/* Bank 0 0x000C is reserved */
-
-/* Bank Select Register */
-/* All Banks */
-#define BSR_REG 0x000E
-
-
-/* Configuration Reg */
-/* BANK 1 */
-#define CONFIG_REG 0x0000
-#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
-#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
-#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
-#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
-
-/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
-#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
-
-
-/* Base Address Register */
-/* BANK 1 */
-#define BASE_REG 0x0002
-
-
-/* Individual Address Registers */
-/* BANK 1 */
-#define ADDR0_REG 0x0004
-#define ADDR1_REG 0x0006
-#define ADDR2_REG 0x0008
-
-
-/* General Purpose Register */
-/* BANK 1 */
-#define GP_REG 0x000A
-
-
-/* Control Register */
-/* BANK 1 */
-#define CTL_REG 0x000C
-#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
-#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
-#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
-#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
-#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
-#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
-#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
-#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
-#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
-
-/* MMU Command Register */
-/* BANK 2 */
-#define MMU_CMD_REG 0x0000
-#define MC_BUSY 1 /* When 1 the last release has not completed */
-#define MC_NOP (0<<5) /* No Op */
-#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
-#define MC_RESET (2<<5) /* Reset MMU to initial state */
-#define MC_REMOVE (3<<5) /* Remove the current rx packet */
-#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
-#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
-#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
-#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
-
-
-/* Packet Number Register */
-/* BANK 2 */
-#define PN_REG 0x0002
-
-
-/* Allocation Result Register */
-/* BANK 2 */
-#define AR_REG 0x0003
-#define AR_FAILED 0x80 /* Alocation Failed */
-
-
-/* RX FIFO Ports Register */
-/* BANK 2 */
-#define RXFIFO_REG 0x0004 /* Must be read as a word */
-#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
-
-
-/* TX FIFO Ports Register */
-/* BANK 2 */
-#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
-#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
-
-
-/* Pointer Register */
-/* BANK 2 */
-#define PTR_REG 0x0006
-#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
-#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
-#define PTR_READ 0x2000 /* When 1 the operation is a read */
-#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
-
-
-/* Data Register */
-/* BANK 2 */
-#define SMC91111_DATA_REG 0x0008
-
-
-/* Interrupt Status/Acknowledge Register */
-/* BANK 2 */
-#define SMC91111_INT_REG 0x000C
-
-
-/* Interrupt Mask Register */
-/* BANK 2 */
-#define IM_REG 0x000D
-#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
-#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
-#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
-#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
-#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
-#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
-#define IM_TX_INT 0x02 /* Transmit Interrrupt */
-#define IM_RCV_INT 0x01 /* Receive Interrupt */
-
-
-/* Multicast Table Registers */
-/* BANK 3 */
-#define MCAST_REG1 0x0000
-#define MCAST_REG2 0x0002
-#define MCAST_REG3 0x0004
-#define MCAST_REG4 0x0006
-
-
-/* Management Interface Register (MII) */
-/* BANK 3 */
-#define MII_REG 0x0008
-#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
-#define MII_MDOE 0x0008 /* MII Output Enable */
-#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
-#define MII_MDI 0x0002 /* MII Input, pin MDI */
-#define MII_MDO 0x0001 /* MII Output, pin MDO */
-
-
-/* Revision Register */
-/* BANK 3 */
-#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
-
-
-/* Early RCV Register */
-/* BANK 3 */
-/* this is NOT on SMC9192 */
-#define ERCV_REG 0x000C
-#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
-#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
-
-/* External Register */
-/* BANK 7 */
-#define EXT_REG 0x0000
-
-
-#define CHIP_9192 3
-#define CHIP_9194 4
-#define CHIP_9195 5
-#define CHIP_9196 6
-#define CHIP_91100 7
-#define CHIP_91100FD 8
-#define CHIP_91111FD 9
-
-#if 0
-static const char * chip_ids[ 15 ] = {
- NULL, NULL, NULL,
- /* 3 */ "SMC91C90/91C92",
- /* 4 */ "SMC91C94",
- /* 5 */ "SMC91C95",
- /* 6 */ "SMC91C96",
- /* 7 */ "SMC91C100",
- /* 8 */ "SMC91C100FD",
- /* 9 */ "SMC91C111",
- NULL, NULL,
- NULL, NULL, NULL};
-#endif
-
-/*
- . Transmit status bits
-*/
-#define TS_SUCCESS 0x0001
-#define TS_LOSTCAR 0x0400
-#define TS_LATCOL 0x0200
-#define TS_16COL 0x0010
-
-/*
- . Receive status bits
-*/
-#define RS_ALGNERR 0x8000
-#define RS_BRODCAST 0x4000
-#define RS_BADCRC 0x2000
-#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
-#define RS_TOOLONG 0x0800
-#define RS_TOOSHORT 0x0400
-#define RS_MULTICAST 0x0001
-#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
-
-
-/* PHY Types */
-enum {
- PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
- PHY_LAN83C180
-};
-
-
-/* PHY Register Addresses (LAN91C111 Internal PHY) */
-
-/* PHY Control Register */
-#define PHY_CNTL_REG 0x00
-#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
-#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
-#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
-#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
-#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
-#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
-#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
-#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
-#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
-
-/* PHY Status Register */
-#define PHY_STAT_REG 0x01
-#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
-#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
-#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
-#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
-#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
-#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
-#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
-#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
-#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
-#define PHY_STAT_LINK 0x0004 /* 1=valid link */
-#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
-#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
-
-/* PHY Identifier Registers */
-#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
-#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
-
-/* PHY Auto-Negotiation Advertisement Register */
-#define PHY_AD_REG 0x04
-#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
-#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
-#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
-#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
-#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
-#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
-#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
-#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
-#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
-
-/* PHY Auto-negotiation Remote End Capability Register */
-#define PHY_RMT_REG 0x05
-/* Uses same bit definitions as PHY_AD_REG */
-
-/* PHY Configuration Register 1 */
-#define PHY_CFG1_REG 0x10
-#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
-#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
-#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
-#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
-#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
-#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
-#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
-#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
-#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
-#define PHY_CFG1_TLVL_MASK 0x003C
-#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
-
-
-/* PHY Configuration Register 2 */
-#define PHY_CFG2_REG 0x11
-#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
-#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
-#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
-#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
-
-/* PHY Status Output (and Interrupt status) Register */
-#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
-#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
-#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
-#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
-#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
-#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
-#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
-#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
-#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
-#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
-#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
-
-/* PHY Interrupt/Status Mask Register */
-#define PHY_MASK_REG 0x13 /* Interrupt Mask */
-/* Uses the same bit definitions as PHY_INT_REG */
-
-
-/*-------------------------------------------------------------------------
- . I define some macros to make it easier to do somewhat common
- . or slightly complicated, repeated tasks.
- --------------------------------------------------------------------------*/
-
-/* select a register bank, 0 to 3 */
-
-#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
-
-/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(a,x) {\
- unsigned char mask;\
- SMC_SELECT_BANK((a),2);\
- mask = SMC_inb((a), IM_REG );\
- mask |= (x);\
- SMC_outb( (a), mask, IM_REG ); \
-}
-
-/* this disables an interrupt from the interrupt mask register */
-
-#define SMC_DISABLE_INT(a,x) {\
- unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = SMC_inb( (a), IM_REG );\
- mask &= ~(x);\
- SMC_outb( (a), mask, IM_REG ); \
-}
-
-/*----------------------------------------------------------------------
- . Define the interrupts that I want to receive from the card
- .
- . I want:
- . IM_EPH_INT, for nasty errors
- . IM_RCV_INT, for happy received packets
- . IM_RX_OVRN_INT, because I have to kick the receiver
- . IM_MDINT, for PHY Register 18 Status Changes
- --------------------------------------------------------------------------*/
-#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
- IM_MDINT)
-
-#endif /* _SMC_91111_H_ */
config USB_EHCI_FSL
bool "Support for FSL on-chip EHCI USB controller"
select EHCI_HCD_INIT_AFTER_RESET
+ select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
+ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
---help---
Enables support for the on-chip EHCI controller on FSL chips.
+config SYS_FSL_USB_INTERNAL_UTMI_PHY
+ bool
+ depends on USB_EHCI_FSL
+
config USB_EHCI_TXFIFO_THRESH
hex
depends on USB_EHCI_TEGRA
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y := hello_world
-extra-$(CONFIG_SMC91111) += smc91111_eeprom
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_PPC) += sched
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004
- * Robin Getz rgetz@blacfin.uclinux.org
- *
- * Heavily borrowed from the following peoples GPL'ed software:
- * - Wolfgang Denk, DENX Software Engineering, wd@denx.de
- * Das U-Boot
- * - Ladislav Michl ladis@linux-mips.org
- * A rejected patch on the U-Boot mailing list
- */
-
-#include <common.h>
-#include <exports.h>
-#include <linux/delay.h>
-#include "../drivers/net/smc91111.h"
-
-#ifndef SMC91111_EEPROM_INIT
-# define SMC91111_EEPROM_INIT()
-#endif
-
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-#define EEPROM 0x1
-#define MAC 0x2
-#define UNKNOWN 0x4
-
-void dump_reg (struct eth_device *dev);
-void dump_eeprom (struct eth_device *dev);
-int write_eeprom_reg (struct eth_device *dev, int value, int reg);
-void copy_from_eeprom (struct eth_device *dev);
-void print_MAC (struct eth_device *dev);
-int read_eeprom_reg (struct eth_device *dev, int reg);
-void print_macaddr (struct eth_device *dev);
-
-int smc91111_eeprom(int argc, char *const argv[])
-{
- int c, i, j, done, line, reg, value, start, what;
- char input[50];
-
- struct eth_device dev;
- dev.iobase = CONFIG_SMC91111_BASE;
-
- /* Print the ABI version */
- app_startup (argv);
- if (XF_VERSION != (int) get_version ()) {
- printf ("Expects ABI version %d\n", XF_VERSION);
- printf ("Actual U-Boot ABI version %d\n",
- (int) get_version ());
- printf ("Can't run\n\n");
- return (0);
- }
-
- SMC91111_EEPROM_INIT();
-
- if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
- printf ("Can't find SMSC91111\n");
- return (0);
- }
-
- done = 0;
- what = UNKNOWN;
- printf ("\n");
- while (!done) {
- /* print the prompt */
- printf ("SMC91111> ");
- line = 0;
- i = 0;
- start = 1;
- while (!line) {
- /* Wait for a keystroke */
- while (!tstc ());
-
- c = getc ();
- /* Make Uppercase */
- if (c >= 'Z')
- c -= ('a' - 'A');
- /* printf(" |%02x| ",c); */
-
- switch (c) {
- case '\r': /* Enter */
- case '\n':
- input[i] = 0;
- puts ("\r\n");
- line = 1;
- break;
- case '\0': /* nul */
- continue;
-
- case 0x03: /* ^C - break */
- input[0] = 0;
- i = 0;
- line = 1;
- done = 1;
- break;
-
- case 0x5F:
- case 0x08: /* ^H - backspace */
- case 0x7F: /* DEL - backspace */
- if (i > 0) {
- puts ("\b \b");
- i--;
- }
- break;
- default:
- if (start) {
- if ((c == 'W') || (c == 'D')
- || (c == 'M') || (c == 'C')
- || (c == 'P')) {
- putc (c);
- input[i] = c;
- if (i <= 45)
- i++;
- start = 0;
- }
- } else {
- if ((c >= '0' && c <= '9')
- || (c >= 'A' && c <= 'F')
- || (c == 'E') || (c == 'M')
- || (c == ' ')) {
- putc (c);
- input[i] = c;
- if (i <= 45)
- i++;
- break;
- }
- }
- break;
- }
- }
-
- for (; i < 49; i++)
- input[i] = 0;
-
- switch (input[0]) {
- case ('W'):
- /* Line should be w reg value */
- i = 0;
- reg = 0;
- value = 0;
- /* Skip to the next space or end) */
- while ((input[i] != ' ') && (input[i] != 0))
- i++;
-
- if (input[i] != 0)
- i++;
-
- /* Are we writing to EEPROM or MAC */
- switch (input[i]) {
- case ('E'):
- what = EEPROM;
- break;
- case ('M'):
- what = MAC;
- break;
- default:
- what = UNKNOWN;
- break;
- }
-
- /* skip to the next space or end */
- while ((input[i] != ' ') && (input[i] != 0))
- i++;
- if (input[i] != 0)
- i++;
-
- /* Find register to write into */
- j = 0;
- while ((input[i] != ' ') && (input[i] != 0)) {
- j = input[i] - 0x30;
- if (j >= 0xA) {
- j -= 0x07;
- }
- reg = (reg * 0x10) + j;
- i++;
- }
-
- while ((input[i] != ' ') && (input[i] != 0))
- i++;
-
- if (input[i] != 0)
- i++;
- else
- what = UNKNOWN;
-
- /* Get the value to write */
- j = 0;
- while ((input[i] != ' ') && (input[i] != 0)) {
- j = input[i] - 0x30;
- if (j >= 0xA) {
- j -= 0x07;
- }
- value = (value * 0x10) + j;
- i++;
- }
-
- switch (what) {
- case 1:
- printf ("Writing EEPROM register %02x with %04x\n", reg, value);
- write_eeprom_reg (&dev, value, reg);
- break;
- case 2:
- printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
- SMC_SELECT_BANK (&dev, reg >> 4);
- SMC_outw (&dev, value, reg & 0xE);
- break;
- default:
- printf ("Wrong\n");
- break;
- }
- break;
- case ('D'):
- dump_eeprom (&dev);
- break;
- case ('M'):
- dump_reg (&dev);
- break;
- case ('C'):
- copy_from_eeprom (&dev);
- break;
- case ('P'):
- print_macaddr (&dev);
- break;
- default:
- break;
- }
-
- }
-
- return (0);
-}
-
-void copy_from_eeprom (struct eth_device *dev)
-{
- int i;
-
- SMC_SELECT_BANK (dev, 1);
- SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
- CTL_RELOAD, CTL_REG);
- i = 100;
- while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
- udelay(100);
- if (i == 0) {
- printf ("Timeout Refreshing EEPROM registers\n");
- } else {
- printf ("EEPROM contents copied to MAC\n");
- }
-
-}
-
-void print_macaddr (struct eth_device *dev)
-{
- int i, j, k, mac[6];
-
- printf ("Current MAC Address in SMSC91111 ");
- SMC_SELECT_BANK (dev, 1);
- for (i = 0; i < 5; i++) {
- printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
- }
-
- printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
-
- i = 0;
- for (j = 0x20; j < 0x23; j++) {
- k = read_eeprom_reg (dev, j);
- mac[i] = k & 0xFF;
- i++;
- mac[i] = k >> 8;
- i++;
- }
-
- printf ("Current MAC Address in EEPROM ");
- for (i = 0; i < 5; i++)
- printf ("%02x:", mac[i]);
- printf ("%02x\n", mac[5]);
-
-}
-void dump_eeprom (struct eth_device *dev)
-{
- int j, k;
-
- printf ("IOS2-0 ");
- for (j = 0; j < 8; j++) {
- printf ("%03x ", j);
- }
- printf ("\n");
-
- for (k = 0; k < 4; k++) {
- if (k == 0)
- printf ("CONFIG ");
- if (k == 1)
- printf ("BASE ");
- if ((k == 2) || (k == 3))
- printf (" ");
- for (j = 0; j < 0x20; j += 4) {
- printf ("%02x:%04x ", j + k,
- read_eeprom_reg (dev, j + k));
- }
- printf ("\n");
- }
-
- for (j = 0x20; j < 0x40; j++) {
- if ((j & 0x07) == 0)
- printf ("\n");
- printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
- }
- printf ("\n");
-
-}
-
-int read_eeprom_reg (struct eth_device *dev, int reg)
-{
- int timeout;
-
- SMC_SELECT_BANK (dev, 2);
- SMC_outw (dev, reg, PTR_REG);
-
- SMC_SELECT_BANK (dev, 1);
- SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
- CTL_RELOAD, CTL_REG);
- timeout = 100;
- while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
- udelay(100);
- if (timeout == 0) {
- printf ("Timeout Reading EEPROM register %02x\n", reg);
- return 0;
- }
-
- return SMC_inw (dev, GP_REG);
-
-}
-
-int write_eeprom_reg (struct eth_device *dev, int value, int reg)
-{
- int timeout;
-
- SMC_SELECT_BANK (dev, 2);
- SMC_outw (dev, reg, PTR_REG);
-
- SMC_SELECT_BANK (dev, 1);
- SMC_outw (dev, value, GP_REG);
- SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
- CTL_STORE, CTL_REG);
- timeout = 100;
- while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
- udelay(100);
- if (timeout == 0) {
- printf ("Timeout Writing EEPROM register %02x\n", reg);
- return 0;
- }
-
- return 1;
-
-}
-
-void dump_reg (struct eth_device *dev)
-{
- int i, j;
-
- printf (" ");
- for (j = 0; j < 4; j++) {
- printf ("Bank%i ", j);
- }
- printf ("\n");
- for (i = 0; i < 0xF; i += 2) {
- printf ("%02x ", i);
- for (j = 0; j < 4; j++) {
- SMC_SELECT_BANK (dev, j);
- printf ("%04x ", SMC_inw (dev, i));
- }
- printf ("\n");
- }
-}
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*
* P3041 DS board configuration file
*
*/
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_SRIO
* P4080 DS board configuration file
* Also supports P4040 DS
*/
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
* P5040 DS board configuration file
*
*/
-#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-
-#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
*/
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_SYS_INTERLAKEN
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
*/
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_INTERLAKEN
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
#define IMX_FEC1_BASE ENET1_BASE_ADDR
-/* QSPI Configs*/
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE (SZ_16M)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
/* boot command, including the target-defined one if any */
/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif
/*
#ifndef _CONFIG_EB_CPU5282_H_
#define _CONFIG_EB_CPU5282_H_
-#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-
/*----------------------------------------------------------------------*
* High Level Configuration Options (easy to change) *
*----------------------------------------------------------------------*/
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * Copyright (c) 2011 IDS GmbH, Germany
- * Sergej Stepanov <ste@ids.de>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_SYS_SICRH 0x00000000
-#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
-
-#define CONFIG_HWCONFIG
-
-/*
- * Definitions for initial stack pointer and data area (in DCACHE )
- */
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
-
-/*
- * Internal Definitions
- */
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/*
- * Manually set up DDR parameters,
- * as this board has not the SPD connected to I2C.
- */
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
- 0x00010000 |\
- CSCONFIG_ROW_BIT_13 |\
- CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
- CSCONFIG_BANK_BIT_3)
-
-#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
-#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
- (3 << TIMING_CFG0_WRT_SHIFT) |\
- (3 << TIMING_CFG0_RRT_SHIFT) |\
- (3 << TIMING_CFG0_WWT_SHIFT) |\
- (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
- (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
- (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
- (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
- (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
- (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
- (7 << TIMING_CFG1_CASLAT_SHIFT) |\
- (4 << TIMING_CFG1_REFREC_SHIFT) |\
- (4 << TIMING_CFG1_WRREC_SHIFT) |\
- (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
- (2 << TIMING_CFG1_WRTORD_SHIFT))
-#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
- (5 << TIMING_CFG2_CPO_SHIFT) |\
- (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
- (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
- (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
- (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
- (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
-
-#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
- (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-
-#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
- SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
- SDRAM_CFG_DBW_32 |\
- SDRAM_CFG_SDRAM_TYPE_DDR2)
-
-#define CONFIG_SYS_SDRAM_CFG2 0x00401000
-#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
- (0x0242 << SDRAM_MODE_SD_SHIFT))
-#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
-#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
- DDRCDR_PZ_NOMZ |\
- DDRCDR_NZ_NOMZ |\
- DDRCDR_ODT |\
- DDRCDR_M_ODR |\
- DDRCDR_Q_DRN)
-
-/*
- * on-board devices
- */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC2
-
-/*
- * NOR FLASH setup
- */
-#define CONFIG_FLASH_SHOW_PROGRESS 50
-
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_FLASH_SIZE 8
-
-/*
- * NAND FLASH setup
- */
-#define CONFIG_SYS_NAND_BASE 0xE1000000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_CACHE_PAGES 64
-
-
-/*
- * MRAM setup
- */
-#define CONFIG_SYS_MRAM_BASE 0xE2000000
-#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
-
-/*
- * CPLD setup
- */
-#define CONFIG_SYS_CPLD_BASE 0xE3000000
-
-/*
- * HW-Watchdog
- */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
-/*
- * I2C setup
- */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-/*
- * Ethernet setup
- */
-#ifdef CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x1
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC2_PHY_ADDR 0x3
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-
-#define CONFIG_SYS_SCCR_USBDRCM 3
-
-/*
- * U-Boot environment setup
- */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
-/*
- * Environment Configuration
- */
-
-#define CONFIG_NETDEV eth1
-#define CONFIG_HOSTNAME "ids8313"
-#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
-#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
-#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
-#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
-
-/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_LOADS_ECHO
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* mtdparts command line support */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" __stringify(CONFIG_NETDEV) "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +${filesize}; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +${filesize}; " \
- "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
- " ${filesize}; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +${filesize}; " \
- "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
- " ${filesize}\0" \
- "console=ttyS0\0" \
- "fdtaddr=0x780000\0" \
- "kernel_addr=ff800000\0" \
- "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
- "setbootargs=setenv bootargs " \
- "root=${rootdev} rw console=${console}," \
- "${baudrate} ${othbootargs}\0" \
- "setipargs=setenv bootargs root=${rootdev} rw " \
- "nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off " \
- "console=${console},${baudrate} ${othbootargs}\0" \
- "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "\0"
-
-/* UBI Support */
-
-#endif /* __CONFIG_H */
/* Integrator CP-specific configuration */
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
-/*
- * Hardware drivers
- */
-#define CONFIG_SMC91111
-#define CONFIG_SMC_USE_32_BIT
-#define CONFIG_SMC91111_BASE 0xC8000000
-#undef CONFIG_SMC91111_EXT_PHY
-
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_IPADDR 192.168.1.104
/* GPR_1 */
#define CONFIG_SYS_GPR1 0x50008060
-#define CONFIG_SYS_GP1DIR 0x00000000
-#define CONFIG_SYS_GP1ODR 0x00000000
-#define CONFIG_SYS_GP2DIR 0xFF000000
-#define CONFIG_SYS_GP2ODR 0x00000000
-
#define CONFIG_SYS_DDRCDR (\
DDRCDR_EN | \
DDRCDR_PZ_MAXZ | \
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
-
/* Qman / Bman */
/* RGMII (FM1@DTESC5) is local managemant interface */
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/* early stack pointer */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
-/* QSPI */
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-
/* PCIe */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/*
* SMP Definitinos
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#endif
-#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
/*
* SMP Definitinos
*/
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
/*
* SMP Definitinos
*/
#define CPU_RELEASE_ADDR secondary_boot_addr
-#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-
/*
* This is not an accurate number. It is used in start.S. The frequency
* will be udpated later when get_bus_freq(0) is available.
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
#endif
/*
* MMC Configs
* */
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* bootz: zImage/initrd.img support */
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
/* MMC Configuration */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Bluewater Systems Snapper 9260 and 9G20 modules
- *
- * (C) Copyright 2011 Bluewater Systems
- * Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* SoC type is defined in boards.cfg */
-#include <asm/hardware.h>
-#include <linux/sizes.h>
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
-#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
-
-/* CPU */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
-#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
-
-/* Mem test settings */
-
-/* NAND Flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
-
-/* GPIOs and IO expander */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
-#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
-
-/* UARTs/Serial console */
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_USART_BASE ATMEL_BASE_DBGU
-#define CONFIG_USART_ID ATMEL_ID_SYS
-#endif
-
-/* I2C - Bit-bashed */
-#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#define I2C_INIT do { \
- at91_set_gpio_output(AT91_PIN_PA23, 1); \
- at91_set_gpio_output(AT91_PIN_PA24, 1); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
- } while (0)
-#define I2C_SOFT_DECLARATIONS
-#define I2C_ACTIVE
-#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
-#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
-#define I2C_SDA(bit) do { \
- if (bit) { \
- at91_set_gpio_input(AT91_PIN_PA23, 1); \
- } else { \
- at91_set_gpio_output(AT91_PIN_PA23, 1); \
- at91_set_gpio_value(AT91_PIN_PA23, bit); \
- } \
- } while (0)
-#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
-#define I2C_DELAY udelay(2)
-
-/* Boot options */
-
-/* Environment settings */
-
-/* Console settings */
-
-#endif /* __CONFIG_H */
/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
-#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* SD/MMC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB */
#define CONFIG_MXC_USB_PORT 1
#endif
#endif /* !CONFIG_GICV3 */
-#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
-/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
-#define CONFIG_SMC91111 1
-#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
-#endif
-
/* PL011 Serial Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7372800
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
#define CONFIG_FEC_MXC_PHYADDR 0
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
/* Watchdog */
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
#define CONFIG_DFU_ENV_SETTINGS \
"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
struct cmd_tbl;
-#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-/* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
-#endif
-
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
#define ddr_out32(a, v) out_le32(a, v)
help
This enables the FDT library (libfdt) overlay support.
+config SYS_FDT_PAD
+ hex "Maximum size of the FDT memory area passeed to the OS"
+ depends on OF_LIBFDT
+ default 0x13000 if FMAN_ENET || QE || U_QE
+ default 0x3000
+ help
+ During OS boot, we allocate a region of memory within the bootmap
+ for the FDT. This is the size that we will expand the FDT that we
+ are using will be extended to be, in bytes.
+
config SPL_OF_LIBFDT
bool "Enable the FDT library for SPL"
depends on SPL_LIBGENERIC_SUPPORT
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_AUTO_ZRELADDR
CONFIG_BOARDDIR
-CONFIG_DEFAULT
CONFIG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC
CONFIG_DFU_ALT_BOOT_SD
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
CONFIG_FSL_LBC
-CONFIG_FSL_NGPIXIS
CONFIG_FSL_PMIC_BITLEN
CONFIG_FSL_PMIC_BUS
CONFIG_FSL_PMIC_CLK
CONFIG_SH_QSPI_BASE
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SLIC
-CONFIG_SMC91111
-CONFIG_SMC91111_BASE
-CONFIG_SMC91111_EXT_PHY
-CONFIG_SMC_USE_32_BIT
CONFIG_SMDK5420
CONFIG_SMP_PEN_ADDR
CONFIG_SMSC_LPC47M
CONFIG_SYS_DDR_CLK_CTRL_800
CONFIG_SYS_DDR_CONFIG
CONFIG_SYS_DDR_CONFIG_2
-CONFIG_SYS_DDR_CONFIG_256
CONFIG_SYS_DDR_CONTROL
CONFIG_SYS_DDR_CONTROL_2
CONFIG_SYS_DDR_CS0_BNDS
CONFIG_SYS_ETHOC_BUFFER_ADDR
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
CONFIG_SYS_FAST_CLK
-CONFIG_SYS_FDT_PAD
CONFIG_SYS_FEC_BUF_USE_SRAM
CONFIG_SYS_FLASH0
CONFIG_SYS_FLASH1
CONFIG_SYS_FSL_DDR2_ADDR
CONFIG_SYS_FSL_DDR3_ADDR
CONFIG_SYS_FSL_DDR_ADDR
-CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
-CONFIG_SYS_FSL_DSPI_BE
-CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
-CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
-CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
-CONFIG_SYS_FSL_DSP_DDR_ADDR
-CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
-CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
-CONFIG_SYS_FSL_ERRATUM_A008751
CONFIG_SYS_FSL_ESDHC_ADDR
-CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-CONFIG_SYS_FSL_ESDHC_NUM
-CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
CONFIG_SYS_FSL_FM
CONFIG_SYS_FSL_FM1_ADDR
CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
CONFIG_SYS_FSL_GUTS_ADDR
-CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_JR0_ADDR
CONFIG_SYS_FSL_JR0_OFFSET
CONFIG_SYS_FSL_LS1_CLK_ADDR
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
-CONFIG_SYS_FSL_MAX_NUM_OF_SEC
CONFIG_SYS_FSL_NUM_CC_PLL
-CONFIG_SYS_FSL_NUM_CC_PLLS
CONFIG_SYS_FSL_OCRAM_BASE
CONFIG_SYS_FSL_OCRAM_SIZE
-CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
CONFIG_SYS_FSL_PAMU_OFFSET
-CONFIG_SYS_FSL_PCIE_COMPAT
CONFIG_SYS_FSL_PMIC_I2C_ADDR
CONFIG_SYS_FSL_PMU_ADDR
CONFIG_SYS_FSL_PMU_CLTBENR
CONFIG_SYS_FSL_QMAN_ADDR
CONFIG_SYS_FSL_QMAN_OFFSET
-CONFIG_SYS_FSL_QMAN_V3
CONFIG_SYS_FSL_QSPI_BASE
-CONFIG_SYS_FSL_QSPI_LE
-CONFIG_SYS_FSL_RAID_ENGINE
CONFIG_SYS_FSL_RAID_ENGINE_ADDR
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
CONFIG_SYS_FSL_RCPM_ADDR
-CONFIG_SYS_FSL_RMU
CONFIG_SYS_FSL_RST_ADDR
CONFIG_SYS_FSL_SCFG_ADDR
-CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
-CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
CONFIG_SYS_FSL_SCFG_OFFSET
-CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
-CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
CONFIG_SYS_FSL_SEC_ADDR
CONFIG_SYS_FSL_SEC_IDX_OFFSET
CONFIG_SYS_FSL_SEC_OFFSET
CONFIG_SYS_FSL_SERDES
CONFIG_SYS_FSL_SERDES_ADDR
-CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
CONFIG_SYS_FSL_SRDS_3
CONFIG_SYS_FSL_SRDS_4
-CONFIG_SYS_FSL_SRDS_NUM_PLLS
CONFIG_SYS_FSL_SRIO_ADDR
CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
-CONFIG_SYS_FSL_SRIO_LIODN
CONFIG_SYS_FSL_SRIO_MAX_PORTS
CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
CONFIG_SYS_FSL_SRIO_OFFSET
-CONFIG_SYS_FSL_TBCLK_DIV
CONFIG_SYS_FSL_TIMER_ADDR
-CONFIG_SYS_FSL_USB1_PHY_ENABLE
-CONFIG_SYS_FSL_USB2_PHY_ENABLE
-CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
CONFIG_SYS_FSL_USDHC_NUM
-CONFIG_SYS_FSL_WDOG_BE
CONFIG_SYS_FSL_WRIOP1_ADDR
CONFIG_SYS_FSL_WRIOP1_MDIO1
CONFIG_SYS_FSL_WRIOP1_MDIO2
-CONFIG_SYS_GP1DIR
-CONFIG_SYS_GP1ODR
-CONFIG_SYS_GP2DIR
-CONFIG_SYS_GP2ODR
CONFIG_SYS_GPIO1_EN
CONFIG_SYS_GPIO1_FUNC
CONFIG_SYS_GPIO1_LED
CONFIG_SYS_GPIO_FUNC
CONFIG_SYS_GPIO_OUT
CONFIG_SYS_GPR1
-CONFIG_SYS_HALT_BEFOR_RAM_JUMP
-CONFIG_SYS_HMI_BASE
CONFIG_SYS_HZ_CLOCK
CONFIG_SYS_I2C_BUSES
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_MPC8xxx_DDR_OFFSET
CONFIG_SYS_MPC8xxx_PIC_ADDR
CONFIG_SYS_MRAM_BASE
-CONFIG_SYS_MRAM_SIZE
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
CONFIG_SYS_NAND_AMASK
CONFIG_SYS_NAND_BASE
CONFIG_SYS_SDRAM_BASE0
CONFIG_SYS_SDRAM_BASE1
CONFIG_SYS_SDRAM_BASE2
-CONFIG_SYS_SDRAM_CFG
CONFIG_SYS_SDRAM_CFG1
CONFIG_SYS_SDRAM_CFG2
CONFIG_SYS_SDRAM_CTRL
projects / platform / kernel / u-boot.git / commitdiff