net/mlx5: DR, Adjust structure member to reduce memory hole
authorRongwei Liu <rongweil@nvidia.com>
Fri, 28 Jan 2022 03:56:28 +0000 (05:56 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Thu, 17 Mar 2022 18:51:56 +0000 (11:51 -0700)
Accord to profiling, mlx5dr_ste/mlx5dr_icm_chunk are the two
hot structures. Their memory layout can be optimized by
adjusting member sequences.

Struct mlx5dr_ste size changes from 64 bytes to 56 bytes.

In the upcoming commits, struct mlx5dr_icm_chunk memory layout
will change automatically after removing some members.
Keep it untouched here.

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Reviewed-by: Shun Hao <shunh@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h

index 88092fa..e906fef 100644 (file)
@@ -151,6 +151,9 @@ struct mlx5dr_ste {
        /* refcount: indicates the num of rules that using this ste */
        u32 refcount;
 
+       /* this ste is part of a rule, located in ste's chain */
+       u8 ste_chain_location;
+
        /* attached to the miss_list head at each htbl entry */
        struct list_head miss_list_node;
 
@@ -161,9 +164,6 @@ struct mlx5dr_ste {
 
        /* The rule this STE belongs to */
        struct mlx5dr_rule_rx_tx *rule_rx_tx;
-
-       /* this ste is part of a rule, located in ste's chain */
-       u8 ste_chain_location;
 };
 
 struct mlx5dr_ste_htbl_ctrl {