[AArch64] Extra tests for vector shift. NFC

diff --git a/llvm/test/CodeGen/AArch64/neon-shift-neg.ll b/llvm/test/CodeGen/AArch64/neon-shift-neg.ll
new file mode 100644 (file)
index 0000000..00fdb02
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/neon-shift-neg.ll
@@ -0,0 +1,264 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+define <2 x i64> @shr64x2(<2 x i64> %a, i64 %b) {
+; CHECK-LABEL: shr64x2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg x8, x0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    neg v1.2d, v1.2d
+; CHECK-NEXT:    sshl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i64 0, %b
+  %splat.splatinsert = insertelement <2 x i64> poison, i64 %sub, i32 0
+  %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> poison, <2 x i32> zeroinitializer
+  %shr = ashr <2 x i64> %a, %splat.splat
+  ret <2 x i64> %shr
+}
+
+define <4 x i32> @shr32x4(<4 x i32> %a, i32 %b) {
+; CHECK-LABEL: shr32x4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    neg v1.4s, v1.4s
+; CHECK-NEXT:    sshl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i32 0, %b
+  %splat.splatinsert = insertelement <4 x i32> poison, i32 %sub, i32 0
+  %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
+  %shr = ashr <4 x i32> %a, %splat.splat
+  ret <4 x i32> %shr
+}
+
+define <4 x i32> @shr32x4undef(<4 x i32> %a, i32 %b) {
+; CHECK-LABEL: shr32x4undef:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    neg v1.4s, v1.4s
+; CHECK-NEXT:    sshl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i32 0, %b
+  %splat.splatinsert = insertelement <4 x i32> poison, i32 %sub, i32 0
+  %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+  %shr = ashr <4 x i32> %a, %splat.splat
+  ret <4 x i32> %shr
+}
+
+define <8 x i16> @shr16x8(<8 x i16> %a, i16 %b) {
+; CHECK-LABEL: shr16x8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    neg v1.8h, v1.8h
+; CHECK-NEXT:    sshl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i16 0, %b
+  %0 = insertelement <8 x i16> undef, i16 %sub, i32 0
+  %sh_prom = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
+  %shr = ashr <8 x i16> %a, %sh_prom
+  ret <8 x i16> %shr
+}
+
+define <16 x i8> @shr8x16(<16 x i8> %a, i8 %b) {
+; CHECK-LABEL: shr8x16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.16b, w8
+; CHECK-NEXT:    neg v1.16b, v1.16b
+; CHECK-NEXT:    sshl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i8 0, %b
+  %0 = insertelement <16 x i8> undef, i8 %sub, i32 0
+  %sh_prom = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
+  %shr = ashr <16 x i8> %a, %sh_prom
+  ret <16 x i8> %shr
+}
+
+define <1 x i64> @shr64x1(<1 x i64> %a, i64 %b) {
+; CHECK-LABEL: shr64x1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg x8, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    neg d1, d1
+; CHECK-NEXT:    sshl d0, d0, d1
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i64 0, %b
+  %splat.splatinsert = insertelement <1 x i64> poison, i64 %sub, i32 0
+  %shr = ashr <1 x i64> %a, %splat.splatinsert
+  ret <1 x i64> %shr
+}
+
+define <2 x i32> @shr32x2(<2 x i32> %a, i32 %b) {
+; CHECK-LABEL: shr32x2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    neg v1.2s, v1.2s
+; CHECK-NEXT:    sshl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i32 0, %b
+  %splat.splatinsert = insertelement <2 x i32> poison, i32 %sub, i32 0
+  %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer
+  %shr = ashr <2 x i32> %a, %splat.splat
+  ret <2 x i32> %shr
+}
+
+define <4 x i16> @shr16x4(<4 x i16> %a, i16 %b) {
+; CHECK-LABEL: shr16x4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.4h, w8
+; CHECK-NEXT:    neg v1.4h, v1.4h
+; CHECK-NEXT:    sshl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i16 0, %b
+  %0 = insertelement <4 x i16> undef, i16 %sub, i32 0
+  %sh_prom = shufflevector <4 x i16> %0, <4 x i16> undef, <4 x i32> zeroinitializer
+  %shr = ashr <4 x i16> %a, %sh_prom
+  ret <4 x i16> %shr
+}
+
+define <8 x i8> @shr8x8(<8 x i8> %a, i8 %b) {
+; CHECK-LABEL: shr8x8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.8b, w8
+; CHECK-NEXT:    neg v1.8b, v1.8b
+; CHECK-NEXT:    sshl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i8 0, %b
+  %0 = insertelement <8 x i8> undef, i8 %sub, i32 0
+  %sh_prom = shufflevector <8 x i8> %0, <8 x i8> undef, <8 x i32> zeroinitializer
+  %shr = ashr <8 x i8> %a, %sh_prom
+  ret <8 x i8> %shr
+}
+
+define <2 x i64> @shl64x2(<2 x i64> %a, i64 %b) {
+; CHECK-LABEL: shl64x2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg x8, x0
+; CHECK-NEXT:    dup v1.2d, x8
+; CHECK-NEXT:    ushl v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i64 0, %b
+  %splat.splatinsert = insertelement <2 x i64> poison, i64 %sub, i32 0
+  %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> poison, <2 x i32> zeroinitializer
+  %shl = shl <2 x i64> %a, %splat.splat
+  ret <2 x i64> %shl
+}
+
+define <4 x i32> @shl32x4(<4 x i32> %a, i32 %b) {
+; CHECK-LABEL: shl32x4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    ushl v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i32 0, %b
+  %splat.splatinsert = insertelement <4 x i32> poison, i32 %sub, i32 0
+  %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
+  %shl = shl <4 x i32> %a, %splat.splat
+  ret <4 x i32> %shl
+}
+
+define <8 x i16> @shl16x8(<8 x i16> %a, i16 %b) {
+; CHECK-LABEL: shl16x8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    ushl v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i16 0, %b
+  %0 = insertelement <8 x i16> undef, i16 %sub, i32 0
+  %sh_prom = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
+  %shl = shl <8 x i16> %a, %sh_prom
+  ret <8 x i16> %shl
+}
+
+define <16 x i8> @shl8x16(<16 x i8> %a, i8 %b) {
+; CHECK-LABEL: shl8x16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.16b, w8
+; CHECK-NEXT:    ushl v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i8 0, %b
+  %0 = insertelement <16 x i8> undef, i8 %sub, i32 0
+  %sh_prom = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
+  %shl = shl <16 x i8> %a, %sh_prom
+  ret <16 x i8> %shl
+}
+
+define <1 x i64> @shl64x1(<1 x i64> %a, i64 %b) {
+; CHECK-LABEL: shl64x1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg x8, x0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    ushl d0, d0, d1
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i64 0, %b
+  %splat.splatinsert = insertelement <1 x i64> poison, i64 %sub, i32 0
+  %shl = shl <1 x i64> %a, %splat.splatinsert
+  ret <1 x i64> %shl
+}
+
+define <2 x i32> @shl32x2(<2 x i32> %a, i32 %b) {
+; CHECK-LABEL: shl32x2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    ushl v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub nsw i32 0, %b
+  %splat.splatinsert = insertelement <2 x i32> poison, i32 %sub, i32 0
+  %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer
+  %shl = shl <2 x i32> %a, %splat.splat
+  ret <2 x i32> %shl
+}
+
+define <4 x i16> @shl16x4(<4 x i16> %a, i16 %b) {
+; CHECK-LABEL: shl16x4:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.4h, w8
+; CHECK-NEXT:    ushl v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i16 0, %b
+  %0 = insertelement <4 x i16> undef, i16 %sub, i32 0
+  %sh_prom = shufflevector <4 x i16> %0, <4 x i16> undef, <4 x i32> zeroinitializer
+  %shl = shl <4 x i16> %a, %sh_prom
+  ret <4 x i16> %shl
+}
+
+define <8 x i8> @shl8x8(<8 x i8> %a, i8 %b) {
+; CHECK-LABEL: shl8x8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    neg w8, w0
+; CHECK-NEXT:    dup v1.8b, w8
+; CHECK-NEXT:    ushl v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ret
+entry:
+  %sub = sub i8 0, %b
+  %0 = insertelement <8 x i8> undef, i8 %sub, i32 0
+  %sh_prom = shufflevector <8 x i8> %0, <8 x i8> undef, <8 x i32> zeroinitializer
+  %shl = shl <8 x i8> %a, %sh_prom
+  ret <8 x i8> %shl
+}