#include <linux/notifier.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/wakelock.h>
#include <asm/intel_scu_ipc.h>
#include "../core/usb.h"
iotg->otg.set_vbus(&iotg->otg, true);
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
+
penwell_otg_add_timer(TA_WAIT_VRISE_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VRISE;
if (iotg->otg.set_vbus)
iotg->otg.set_vbus(&iotg->otg, false);
- pm_runtime_get(pnw->dev);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (hsm->a_vbus_vld || hsm->a_wait_vrise_tmout
if (iotg->otg.set_vbus)
iotg->otg.set_vbus(&iotg->otg, false);
- pm_runtime_get(pnw->dev);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
break;
}
pm_runtime_put(pnw->dev);
+ wake_unlock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_BCON_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_BCON;
}
iotg->otg.set_vbus(&iotg->otg, false);
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (!hsm->a_vbus_vld) {
iotg->otg.set_vbus(&iotg->otg, false);
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (hsm->test_device && hsm->tst_maint_tmout) {
/* Clear states and wait for SRP */
hsm->a_srp_det = 0;
hsm->a_bus_req = 0;
+ wake_unlock(&pnw->wake_lock);
iotg->otg.state = OTG_STATE_A_IDLE;
} else if (!hsm->a_vbus_vld) {
/* Move to A_VBUS_ERR state */
iotg->otg.set_vbus(&iotg->otg, false);
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TTST_NOADP_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
iotg->otg.set_vbus(&iotg->otg, false);
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (!hsm->a_vbus_vld) {
set_host_mode();
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
} else if (!hsm->a_vbus_vld) {
hsm->a_clr_err = 0;
pm_runtime_get(pnw->dev);
+ wake_lock(&pnw->wake_lock);
penwell_otg_add_timer(TA_WAIT_VFALL_TMR);
iotg->otg.state = OTG_STATE_A_WAIT_VFALL;
}
hsm->a_bus_req = 1;
pm_runtime_put(pnw->dev);
+ wake_unlock(&pnw->wake_lock);
iotg->otg.state = OTG_STATE_A_IDLE;
penwell_update_transceiver();
} else if (hsm->test_device && hsm->otg_vbus_off
hsm->a_bus_req = 1;
pm_runtime_put(pnw->dev);
+ wake_unlock(&pnw->wake_lock);
iotg->otg.state = OTG_STATE_A_IDLE;
penwell_update_transceiver();
}
spin_lock_init(&pnw->iotg.hnp_poll_lock);
spin_lock_init(&pnw->notify_lock);
+ wake_lock_init(&pnw->wake_lock, WAKE_LOCK_SUSPEND, "pnw_wake_lock");
+
init_timer(&pnw->hsm_timer);
init_timer(&pnw->bus_mon_timer);
init_timer(&pnw->hnp_poll_timer);
/* disable OTGSC interrupt as OTGSC doesn't change in reset */
writel(0, pnw->iotg.base + CI_OTGSC);
+ wake_lock_destroy(&pnw->wake_lock);
+
if (pdev->irq)
free_irq(pdev->irq, pnw);
if (pnw->cfg_region)