drm/bridge/sii8620: improve gen2 write burst IRQ routine

The patch adds code to report back feature complete IRQ, and code
to read and drop burst writes from peer.

Change-Id: I19df1e7d08c43661896aced305fe32e88b919a09
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 5286b9da1a5bf0b92e0e5f0f1703ff2253453673..3debe98ecdc1f39c8490410c480498632b077147 100644 (file)
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -1565,12 +1565,31 @@ static void sii8620_irq_disc(struct sii8620 *ctx)
        sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
 }
 
+static void sii8620_read_burst(struct sii8620 *ctx)
+{
+       u8 buf[17];
+
+       sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
+       sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
+                     BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
+                     BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
+       sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
+}
+
 static void sii8620_irq_g2wb(struct sii8620 *ctx)
 {
        u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
 
        if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
-               dev_dbg(ctx->dev, "HAWB idle\n");
+               if (ctx->mode >= CM_MHL3)
+                       sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
+                               MHL_INT_RC_FEAT_COMPLETE);
+
+       if (stat & BIT_MDT_RFIFO_DATA_RDY)
+               sii8620_read_burst(ctx);
+
+       if (stat & BIT_MDT_XFIFO_EMPTY)
+               sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
 
        sii8620_write(ctx, REG_MDT_INT_0, stat);
 }