Revert [ARM] Remove neon-testgen.ml and generated tests.

From-SVN: r230296

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 73668fa..8623e21 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2015-11-13  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       Revert [ARM] Remove neon-testgen.ml and generated tests.
+
+       2015-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       [ARM] Remove neon-testgen.ml and generated tests.
+
+       * config/arm/neon-testgen.ml: Remove.
+
 2015-11-13  Richard Biener  <rguenther@suse.de>
 
        * tree-vect-loop.c (vect_analyze_loop_2): Add fatal parameter.

diff --git a/gcc/config/arm/neon-testgen.ml b/gcc/config/arm/neon-testgen.ml
new file mode 100644 (file)
index 0000000..a80c05d
--- /dev/null
+++ b/gcc/config/arm/neon-testgen.ml
@@ -0,0 +1,324 @@
+(* Auto-generate ARM Neon intrinsics tests.
+   Copyright (C) 2006-2015 Free Software Foundation, Inc.
+   Contributed by CodeSourcery.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3, or (at your option) any later
+   version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.
+
+   This is an O'Caml program.  The O'Caml compiler is available from:
+
+     http://caml.inria.fr/
+
+   Or from your favourite OS's friendly packaging system. Tested with version
+   3.09.2, though other versions will probably work too.
+
+   Compile with:
+     ocamlc -c neon.ml
+     ocamlc -o neon-testgen neon.cmo neon-testgen.ml
+
+   Run with:
+     cd /path/to/gcc/testsuite/gcc.target/arm/neon
+     /path/to/neon-testgen
+*)
+
+open Neon
+
+type c_type_flags = Pointer | Const
+
+(* Open a test source file.  *)
+let open_test_file dir name =
+  try
+    open_out (dir ^ "/" ^ name ^ ".c")
+  with Sys_error str ->
+    failwith ("Could not create test source file " ^ name ^ ": " ^ str)
+
+(* Emit prologue code to a test source file.  *)
+let emit_prologue chan test_name effective_target compile_test_optim =
+  Printf.fprintf chan "/* Test the `%s' ARM Neon intrinsic.  */\n" test_name;
+  Printf.fprintf chan "/* This file was autogenerated by neon-testgen.  */\n\n";
+  Printf.fprintf chan "/* { dg-do assemble } */\n";
+  Printf.fprintf chan "/* { dg-require-effective-target %s_ok } */\n"
+                 effective_target;
+  Printf.fprintf chan "/* { dg-options \"-save-temps %s\" } */\n" compile_test_optim;
+  Printf.fprintf chan "/* { dg-add-options %s } */\n" effective_target;
+  Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n"
+
+(* Emit declarations of variables that are going to be passed
+   to an intrinsic, together with one to take a returned value if needed.  *)
+let emit_variables chan c_types features spaces =
+  let emit () =
+    ignore (
+      List.fold_left (fun arg_number -> fun (flags, ty) ->
+                        let pointer_bit =
+                          if List.mem Pointer flags then "*" else ""
+                        in
+                          (* Const arguments to builtins are directly
+                             written in as constants.  *)
+                          if not (List.mem Const flags) then
+                            Printf.fprintf chan "%s%s %sarg%d_%s;\n"
+                                           spaces ty pointer_bit arg_number ty;
+                        arg_number + 1)
+                     0 (List.tl c_types))
+  in
+    match c_types with
+      (_, return_ty) :: tys ->
+        if return_ty <> "void" then begin
+          (* The intrinsic returns a value.  We need to do explicit register
+             allocation for vget_low tests or they fail because of copy
+             elimination.  *)
+          ((if List.mem Fixed_vector_reg features then
+              Printf.fprintf chan "%sregister %s out_%s asm (\"d18\");\n"
+                             spaces return_ty return_ty
+            else if List.mem Fixed_core_reg features then
+              Printf.fprintf chan "%sregister %s out_%s asm (\"r0\");\n"
+                             spaces return_ty return_ty
+            else
+              Printf.fprintf chan "%s%s out_%s;\n" spaces return_ty return_ty);
+          emit ())
+        end else
+          (* The intrinsic does not return a value.  *)
+          emit ()
+    | _ -> assert false
+
+(* Emit code to call an intrinsic.  *)
+let emit_call chan const_valuator c_types name elt_ty =
+  (if snd (List.hd c_types) <> "void" then
+     Printf.fprintf chan "  out_%s = " (snd (List.hd c_types))
+   else
+     Printf.fprintf chan "  ");
+  Printf.fprintf chan "%s_%s (" (intrinsic_name name) (string_of_elt elt_ty);
+  let print_arg chan arg_number (flags, ty) =
+    (* If the argument is of const type, then directly write in the
+       constant now.  *)
+    if List.mem Const flags then
+      match const_valuator with
+        None ->
+          if List.mem Pointer flags then
+            Printf.fprintf chan "0"
+          else
+            Printf.fprintf chan "1"
+      | Some f -> Printf.fprintf chan "%s" (string_of_int (f arg_number))
+    else
+      Printf.fprintf chan "arg%d_%s" arg_number ty
+  in
+  let rec print_args arg_number tys =
+    match tys with
+      [] -> ()
+    | [ty] -> print_arg chan arg_number ty
+    | ty::tys ->
+      print_arg chan arg_number ty;
+      Printf.fprintf chan ", ";
+      print_args (arg_number + 1) tys
+  in
+    print_args 0 (List.tl c_types);
+    Printf.fprintf chan ");\n"
+
+(* Emit epilogue code to a test source file.  *)
+let emit_epilogue chan features regexps =
+  let no_op = List.exists (fun feature -> feature = No_op) features in
+    Printf.fprintf chan "}\n\n";
+    if not no_op then
+      List.iter (fun regexp ->
+                  Printf.fprintf chan
+                    "/* { dg-final { scan-assembler \"%s\" } } */\n" regexp)
+                regexps
+    else
+      ()
+    
+
+(* Check a list of C types to determine which ones are pointers and which
+   ones are const.  *)
+let check_types tys =
+  let tys' =
+    List.map (fun ty ->
+                let len = String.length ty in
+                  if len > 2 && String.get ty (len - 2) = ' '
+                             && String.get ty (len - 1) = '*'
+                  then ([Pointer], String.sub ty 0 (len - 2))
+                  else ([], ty)) tys
+  in
+    List.map (fun (flags, ty) ->
+                if String.length ty > 6 && String.sub ty 0 6 = "const "
+                then (Const :: flags, String.sub ty 6 ((String.length ty) - 6))
+                else (flags, ty)) tys'
+
+(* Work out what the effective target should be.  *)
+let effective_target features =
+  try
+    match List.find (fun feature ->
+                       match feature with Requires_feature _ -> true
+                                        | Requires_arch _ -> true
+                                        | Requires_FP_bit 1 -> true
+                                        | _ -> false)
+                     features with
+      Requires_feature "FMA" -> "arm_neonv2"
+    | Requires_feature "CRYPTO" -> "arm_crypto"
+    | Requires_arch 8 -> "arm_v8_neon"
+    | Requires_FP_bit 1 -> "arm_neon_fp16"
+    | _ -> assert false
+  with Not_found -> "arm_neon"
+
+(* Work out what the testcase optimization level should be, default to -O0.  *)
+let compile_test_optim features =
+  try
+    match List.find (fun feature ->
+                       match feature with Compiler_optim _ -> true
+                                        | _ -> false)
+                     features with
+      Compiler_optim opt -> opt
+    | _ -> assert false
+  with Not_found -> "-O0"
+
+(* Given an intrinsic shape, produce a regexp that will match
+   the right-hand sides of instructions generated by an intrinsic of
+   that shape.  *)
+let rec analyze_shape shape =
+  let rec n_things n thing =
+    match n with
+      0 -> []
+    | n -> thing :: (n_things (n - 1) thing)
+  in
+  let rec analyze_shape_elt elt =
+    match elt with
+      Dreg -> "\\[dD\\]\\[0-9\\]+"
+    | Qreg -> "\\[qQ\\]\\[0-9\\]+"
+    | Corereg -> "\\[rR\\]\\[0-9\\]+"
+    | Immed -> "#\\[0-9\\]+"
+    | VecArray (1, elt) ->
+        let elt_regexp = analyze_shape_elt elt in
+          "((\\\\\\{" ^ elt_regexp ^ "\\\\\\})|(" ^ elt_regexp ^ "))"
+    | VecArray (n, elt) ->
+      let elt_regexp = analyze_shape_elt elt in
+      let alt1 = elt_regexp ^ "-" ^ elt_regexp in
+      let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
+        "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
+    | (PtrTo elt | CstPtrTo elt) ->
+      "\\\\\\[" ^ (analyze_shape_elt elt) ^ "\\(:\\[0-9\\]+\\)?\\\\\\]"
+    | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+    | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
+    | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
+    | Alternatives (elts) -> "(" ^ (String.concat "|" (List.map analyze_shape_elt elts)) ^ ")"
+  in
+    match shape with
+      All (n, elt) -> commas analyze_shape_elt (n_things n elt) ""
+    | Long -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Dreg) ^
+              ", " ^ (analyze_shape_elt Dreg)
+    | Long_noreg elt -> (analyze_shape_elt elt) ^ ", " ^ (analyze_shape_elt elt)
+    | Wide -> (analyze_shape_elt Qreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+              ", " ^ (analyze_shape_elt Dreg)
+    | Wide_noreg elt -> analyze_shape (Long_noreg elt)
+    | Narrow -> (analyze_shape_elt Dreg) ^ ", " ^ (analyze_shape_elt Qreg) ^
+                ", " ^ (analyze_shape_elt Qreg)
+    | Use_operands elts -> commas analyze_shape_elt (Array.to_list elts) ""
+    | By_scalar Dreg ->
+        analyze_shape (Use_operands [| Dreg; Dreg; Element_of_dreg |])
+    | By_scalar Qreg ->
+        analyze_shape (Use_operands [| Qreg; Qreg; Element_of_dreg |])
+    | By_scalar _ -> assert false
+    | Wide_lane ->
+        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+    | Wide_scalar ->
+        analyze_shape (Use_operands [| Qreg; Dreg; Element_of_dreg |])
+    | Pair_result elt ->
+      let elt_regexp = analyze_shape_elt elt in
+        elt_regexp ^ ", " ^ elt_regexp
+    | Unary_scalar _ -> "FIXME Unary_scalar"
+    | Binary_imm elt -> analyze_shape (Use_operands [| elt; elt; Immed |])
+    | Narrow_imm -> analyze_shape (Use_operands [| Dreg; Qreg; Immed |])
+    | Long_imm -> analyze_shape (Use_operands [| Qreg; Dreg; Immed |])
+
+(* Generate tests for one intrinsic.  *)
+let test_intrinsic dir opcode features shape name munge elt_ty =
+  (* Open the test source file.  *)
+  let test_name = name ^ (string_of_elt elt_ty) in
+  let chan = open_test_file dir test_name in
+  (* Work out what argument and return types the intrinsic has.  *)
+  let c_arity, new_elt_ty = munge shape elt_ty in
+  let c_types = check_types (strings_of_arity c_arity) in
+  (* Extract any constant valuator (a function specifying what constant
+     values are to be written into the intrinsic call) from the features
+     list.  *)
+  let const_valuator =
+    try
+      match (List.find (fun feature -> match feature with
+                                         Const_valuator _ -> true
+                                      | _ -> false) features) with
+        Const_valuator f -> Some f
+      | _ -> assert false
+    with Not_found -> None
+  in
+  (* Work out what instruction name(s) to expect.  *)
+  let insns = get_insn_names features name in
+  let no_suffix = (new_elt_ty = NoElts) in
+  let insns =
+    if no_suffix then insns
+                 else List.map (fun insn ->
+                                  let suffix = string_of_elt_dots new_elt_ty in
+                                    insn ^ "\\." ^ suffix) insns
+  in
+  (* Construct a regexp to match against the expected instruction name(s).  *)
+  let insn_regexp =
+    match insns with
+      [] -> assert false
+    | [insn] -> insn
+    | _ ->
+      let rec calc_regexp insns cur_regexp =
+        match insns with
+          [] -> cur_regexp
+        | [insn] -> cur_regexp ^ "(" ^ insn ^ "))"
+        | insn::insns -> calc_regexp insns (cur_regexp ^ "(" ^ insn ^ ")|")
+      in calc_regexp insns "("
+  in
+  (* Construct regexps to match against the instructions that this
+     intrinsic expands to.  Watch out for any writeback character and
+     comments after the instruction.  *)
+  let regexps = List.map (fun regexp -> insn_regexp ^ "\\[ \t\\]+" ^ regexp ^
+                         "!?\\(\\[ \t\\]+@\\[a-zA-Z0-9 \\]+\\)?\\n")
+                         (analyze_all_shapes features shape analyze_shape)
+  in
+  let effective_target = effective_target features in
+  let compile_test_optim = compile_test_optim features
+  in
+    (* Emit file and function prologues.  *)
+    emit_prologue chan test_name effective_target compile_test_optim;
+
+    if (compare compile_test_optim "-O0") <> 0 then
+        (* Emit variable declarations.  *)
+        emit_variables chan c_types features "";
+
+    Printf.fprintf chan "void test_%s (void)\n{\n" test_name;
+
+    if compare compile_test_optim "-O0" = 0 then
+        (* Emit variable declarations.  *)
+        emit_variables chan c_types features "  ";
+
+    Printf.fprintf chan "\n";
+    (* Emit the call to the intrinsic.  *)
+    emit_call chan const_valuator c_types name elt_ty;
+    (* Emit the function epilogue and the DejaGNU scan-assembler directives.  *)
+    emit_epilogue chan features regexps;
+    (* Close the test file.  *)
+    close_out chan
+
+(* Generate tests for one element of the "ops" table.  *)
+let test_intrinsic_group dir (opcode, features, shape, name, munge, types) =
+  List.iter (test_intrinsic dir opcode features shape name munge) types
+
+(* Program entry point.  *)
+let _ =
+  let directory = if Array.length Sys.argv <> 1 then Sys.argv.(1) else "." in
+    List.iter (test_intrinsic_group directory) (reinterp @ reinterpq @ ops)
+

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 60b5087..5e8bdba 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,1998 @@
+2015-11-13  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       Revert [ARM] Remove neon-testgen.ml and generated tests.
+       2015-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
+
+       * gcc.target/arm/neon/vRaddhns16.c: Remove.
+       * gcc.target/arm/neon/vRaddhns32.c: Remove.
+       * gcc.target/arm/neon/vRaddhns64.c: Remove.
+       * gcc.target/arm/neon/vRaddhnu16.c: Remove.
+       * gcc.target/arm/neon/vRaddhnu32.c: Remove.
+       * gcc.target/arm/neon/vRaddhnu64.c: Remove.
+       * gcc.target/arm/neon/vRhaddQs16.c: Remove.
+       * gcc.target/arm/neon/vRhaddQs32.c: Remove.
+       * gcc.target/arm/neon/vRhaddQs8.c: Remove.
+       * gcc.target/arm/neon/vRhaddQu16.c: Remove.
+       * gcc.target/arm/neon/vRhaddQu32.c: Remove.
+       * gcc.target/arm/neon/vRhaddQu8.c: Remove.
+       * gcc.target/arm/neon/vRhadds16.c: Remove.
+       * gcc.target/arm/neon/vRhadds32.c: Remove.
+       * gcc.target/arm/neon/vRhadds8.c: Remove.
+       * gcc.target/arm/neon/vRhaddu16.c: Remove.
+       * gcc.target/arm/neon/vRhaddu32.c: Remove.
+       * gcc.target/arm/neon/vRhaddu8.c: Remove.
+       * gcc.target/arm/neon/vRshlQs16.c: Remove.
+       * gcc.target/arm/neon/vRshlQs32.c: Remove.
+       * gcc.target/arm/neon/vRshlQs64.c: Remove.
+       * gcc.target/arm/neon/vRshlQs8.c: Remove.
+       * gcc.target/arm/neon/vRshlQu16.c: Remove.
+       * gcc.target/arm/neon/vRshlQu32.c: Remove.
+       * gcc.target/arm/neon/vRshlQu64.c: Remove.
+       * gcc.target/arm/neon/vRshlQu8.c: Remove.
+       * gcc.target/arm/neon/vRshls16.c: Remove.
+       * gcc.target/arm/neon/vRshls32.c: Remove.
+       * gcc.target/arm/neon/vRshls64.c: Remove.
+       * gcc.target/arm/neon/vRshls8.c: Remove.
+       * gcc.target/arm/neon/vRshlu16.c: Remove.
+       * gcc.target/arm/neon/vRshlu32.c: Remove.
+       * gcc.target/arm/neon/vRshlu64.c: Remove.
+       * gcc.target/arm/neon/vRshlu8.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vRshrQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vRshr_ns16.c: Remove.
+       * gcc.target/arm/neon/vRshr_ns32.c: Remove.
+       * gcc.target/arm/neon/vRshr_ns64.c: Remove.
+       * gcc.target/arm/neon/vRshr_ns8.c: Remove.
+       * gcc.target/arm/neon/vRshr_nu16.c: Remove.
+       * gcc.target/arm/neon/vRshr_nu32.c: Remove.
+       * gcc.target/arm/neon/vRshr_nu64.c: Remove.
+       * gcc.target/arm/neon/vRshr_nu8.c: Remove.
+       * gcc.target/arm/neon/vRshrn_ns16.c: Remove.
+       * gcc.target/arm/neon/vRshrn_ns32.c: Remove.
+       * gcc.target/arm/neon/vRshrn_ns64.c: Remove.
+       * gcc.target/arm/neon/vRshrn_nu16.c: Remove.
+       * gcc.target/arm/neon/vRshrn_nu32.c: Remove.
+       * gcc.target/arm/neon/vRshrn_nu64.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vRsraQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vRsra_ns16.c: Remove.
+       * gcc.target/arm/neon/vRsra_ns32.c: Remove.
+       * gcc.target/arm/neon/vRsra_ns64.c: Remove.
+       * gcc.target/arm/neon/vRsra_ns8.c: Remove.
+       * gcc.target/arm/neon/vRsra_nu16.c: Remove.
+       * gcc.target/arm/neon/vRsra_nu32.c: Remove.
+       * gcc.target/arm/neon/vRsra_nu64.c: Remove.
+       * gcc.target/arm/neon/vRsra_nu8.c: Remove.
+       * gcc.target/arm/neon/vRsubhns16.c: Remove.
+       * gcc.target/arm/neon/vRsubhns32.c: Remove.
+       * gcc.target/arm/neon/vRsubhns64.c: Remove.
+       * gcc.target/arm/neon/vRsubhnu16.c: Remove.
+       * gcc.target/arm/neon/vRsubhnu32.c: Remove.
+       * gcc.target/arm/neon/vRsubhnu64.c: Remove.
+       * gcc.target/arm/neon/vabaQs16.c: Remove.
+       * gcc.target/arm/neon/vabaQs32.c: Remove.
+       * gcc.target/arm/neon/vabaQs8.c: Remove.
+       * gcc.target/arm/neon/vabaQu16.c: Remove.
+       * gcc.target/arm/neon/vabaQu32.c: Remove.
+       * gcc.target/arm/neon/vabaQu8.c: Remove.
+       * gcc.target/arm/neon/vabals16.c: Remove.
+       * gcc.target/arm/neon/vabals32.c: Remove.
+       * gcc.target/arm/neon/vabals8.c: Remove.
+       * gcc.target/arm/neon/vabalu16.c: Remove.
+       * gcc.target/arm/neon/vabalu32.c: Remove.
+       * gcc.target/arm/neon/vabalu8.c: Remove.
+       * gcc.target/arm/neon/vabas16.c: Remove.
+       * gcc.target/arm/neon/vabas32.c: Remove.
+       * gcc.target/arm/neon/vabas8.c: Remove.
+       * gcc.target/arm/neon/vabau16.c: Remove.
+       * gcc.target/arm/neon/vabau32.c: Remove.
+       * gcc.target/arm/neon/vabau8.c: Remove.
+       * gcc.target/arm/neon/vabdQf32.c: Remove.
+       * gcc.target/arm/neon/vabdQs16.c: Remove.
+       * gcc.target/arm/neon/vabdQs32.c: Remove.
+       * gcc.target/arm/neon/vabdQs8.c: Remove.
+       * gcc.target/arm/neon/vabdQu16.c: Remove.
+       * gcc.target/arm/neon/vabdQu32.c: Remove.
+       * gcc.target/arm/neon/vabdQu8.c: Remove.
+       * gcc.target/arm/neon/vabdf32.c: Remove.
+       * gcc.target/arm/neon/vabdls16.c: Remove.
+       * gcc.target/arm/neon/vabdls32.c: Remove.
+       * gcc.target/arm/neon/vabdls8.c: Remove.
+       * gcc.target/arm/neon/vabdlu16.c: Remove.
+       * gcc.target/arm/neon/vabdlu32.c: Remove.
+       * gcc.target/arm/neon/vabdlu8.c: Remove.
+       * gcc.target/arm/neon/vabds16.c: Remove.
+       * gcc.target/arm/neon/vabds32.c: Remove.
+       * gcc.target/arm/neon/vabds8.c: Remove.
+       * gcc.target/arm/neon/vabdu16.c: Remove.
+       * gcc.target/arm/neon/vabdu32.c: Remove.
+       * gcc.target/arm/neon/vabdu8.c: Remove.
+       * gcc.target/arm/neon/vabsQf32.c: Remove.
+       * gcc.target/arm/neon/vabsQs16.c: Remove.
+       * gcc.target/arm/neon/vabsQs32.c: Remove.
+       * gcc.target/arm/neon/vabsQs8.c: Remove.
+       * gcc.target/arm/neon/vabsf32.c: Remove.
+       * gcc.target/arm/neon/vabss16.c: Remove.
+       * gcc.target/arm/neon/vabss32.c: Remove.
+       * gcc.target/arm/neon/vabss8.c: Remove.
+       * gcc.target/arm/neon/vaddQf32.c: Remove.
+       * gcc.target/arm/neon/vaddQs16.c: Remove.
+       * gcc.target/arm/neon/vaddQs32.c: Remove.
+       * gcc.target/arm/neon/vaddQs64.c: Remove.
+       * gcc.target/arm/neon/vaddQs8.c: Remove.
+       * gcc.target/arm/neon/vaddQu16.c: Remove.
+       * gcc.target/arm/neon/vaddQu32.c: Remove.
+       * gcc.target/arm/neon/vaddQu64.c: Remove.
+       * gcc.target/arm/neon/vaddQu8.c: Remove.
+       * gcc.target/arm/neon/vaddf32.c: Remove.
+       * gcc.target/arm/neon/vaddhns16.c: Remove.
+       * gcc.target/arm/neon/vaddhns32.c: Remove.
+       * gcc.target/arm/neon/vaddhns64.c: Remove.
+       * gcc.target/arm/neon/vaddhnu16.c: Remove.
+       * gcc.target/arm/neon/vaddhnu32.c: Remove.
+       * gcc.target/arm/neon/vaddhnu64.c: Remove.
+       * gcc.target/arm/neon/vaddls16.c: Remove.
+       * gcc.target/arm/neon/vaddls32.c: Remove.
+       * gcc.target/arm/neon/vaddls8.c: Remove.
+       * gcc.target/arm/neon/vaddlu16.c: Remove.
+       * gcc.target/arm/neon/vaddlu32.c: Remove.
+       * gcc.target/arm/neon/vaddlu8.c: Remove.
+       * gcc.target/arm/neon/vadds16.c: Remove.
+       * gcc.target/arm/neon/vadds32.c: Remove.
+       * gcc.target/arm/neon/vadds64.c: Remove.
+       * gcc.target/arm/neon/vadds8.c: Remove.
+       * gcc.target/arm/neon/vaddu16.c: Remove.
+       * gcc.target/arm/neon/vaddu32.c: Remove.
+       * gcc.target/arm/neon/vaddu64.c: Remove.
+       * gcc.target/arm/neon/vaddu8.c: Remove.
+       * gcc.target/arm/neon/vaddws16.c: Remove.
+       * gcc.target/arm/neon/vaddws32.c: Remove.
+       * gcc.target/arm/neon/vaddws8.c: Remove.
+       * gcc.target/arm/neon/vaddwu16.c: Remove.
+       * gcc.target/arm/neon/vaddwu32.c: Remove.
+       * gcc.target/arm/neon/vaddwu8.c: Remove.
+       * gcc.target/arm/neon/vandQs16.c: Remove.
+       * gcc.target/arm/neon/vandQs32.c: Remove.
+       * gcc.target/arm/neon/vandQs64.c: Remove.
+       * gcc.target/arm/neon/vandQs8.c: Remove.
+       * gcc.target/arm/neon/vandQu16.c: Remove.
+       * gcc.target/arm/neon/vandQu32.c: Remove.
+       * gcc.target/arm/neon/vandQu64.c: Remove.
+       * gcc.target/arm/neon/vandQu8.c: Remove.
+       * gcc.target/arm/neon/vands16.c: Remove.
+       * gcc.target/arm/neon/vands32.c: Remove.
+       * gcc.target/arm/neon/vands64.c: Remove.
+       * gcc.target/arm/neon/vands8.c: Remove.
+       * gcc.target/arm/neon/vandu16.c: Remove.
+       * gcc.target/arm/neon/vandu32.c: Remove.
+       * gcc.target/arm/neon/vandu64.c: Remove.
+       * gcc.target/arm/neon/vandu8.c: Remove.
+       * gcc.target/arm/neon/vbicQs16.c: Remove.
+       * gcc.target/arm/neon/vbicQs32.c: Remove.
+       * gcc.target/arm/neon/vbicQs64.c: Remove.
+       * gcc.target/arm/neon/vbicQs8.c: Remove.
+       * gcc.target/arm/neon/vbicQu16.c: Remove.
+       * gcc.target/arm/neon/vbicQu32.c: Remove.
+       * gcc.target/arm/neon/vbicQu64.c: Remove.
+       * gcc.target/arm/neon/vbicQu8.c: Remove.
+       * gcc.target/arm/neon/vbics16.c: Remove.
+       * gcc.target/arm/neon/vbics32.c: Remove.
+       * gcc.target/arm/neon/vbics64.c: Remove.
+       * gcc.target/arm/neon/vbics8.c: Remove.
+       * gcc.target/arm/neon/vbicu16.c: Remove.
+       * gcc.target/arm/neon/vbicu32.c: Remove.
+       * gcc.target/arm/neon/vbicu64.c: Remove.
+       * gcc.target/arm/neon/vbicu8.c: Remove.
+       * gcc.target/arm/neon/vbslQf32.c: Remove.
+       * gcc.target/arm/neon/vbslQp16.c: Remove.
+       * gcc.target/arm/neon/vbslQp64.c: Remove.
+       * gcc.target/arm/neon/vbslQp8.c: Remove.
+       * gcc.target/arm/neon/vbslQs16.c: Remove.
+       * gcc.target/arm/neon/vbslQs32.c: Remove.
+       * gcc.target/arm/neon/vbslQs64.c: Remove.
+       * gcc.target/arm/neon/vbslQs8.c: Remove.
+       * gcc.target/arm/neon/vbslQu16.c: Remove.
+       * gcc.target/arm/neon/vbslQu32.c: Remove.
+       * gcc.target/arm/neon/vbslQu64.c: Remove.
+       * gcc.target/arm/neon/vbslQu8.c: Remove.
+       * gcc.target/arm/neon/vbslf32.c: Remove.
+       * gcc.target/arm/neon/vbslp16.c: Remove.
+       * gcc.target/arm/neon/vbslp64.c: Remove.
+       * gcc.target/arm/neon/vbslp8.c: Remove.
+       * gcc.target/arm/neon/vbsls16.c: Remove.
+       * gcc.target/arm/neon/vbsls32.c: Remove.
+       * gcc.target/arm/neon/vbsls64.c: Remove.
+       * gcc.target/arm/neon/vbsls8.c: Remove.
+       * gcc.target/arm/neon/vbslu16.c: Remove.
+       * gcc.target/arm/neon/vbslu32.c: Remove.
+       * gcc.target/arm/neon/vbslu64.c: Remove.
+       * gcc.target/arm/neon/vbslu8.c: Remove.
+       * gcc.target/arm/neon/vcageQf32.c: Remove.
+       * gcc.target/arm/neon/vcagef32.c: Remove.
+       * gcc.target/arm/neon/vcagtQf32.c: Remove.
+       * gcc.target/arm/neon/vcagtf32.c: Remove.
+       * gcc.target/arm/neon/vcaleQf32.c: Remove.
+       * gcc.target/arm/neon/vcalef32.c: Remove.
+       * gcc.target/arm/neon/vcaltQf32.c: Remove.
+       * gcc.target/arm/neon/vcaltf32.c: Remove.
+       * gcc.target/arm/neon/vceqQf32.c: Remove.
+       * gcc.target/arm/neon/vceqQp8.c: Remove.
+       * gcc.target/arm/neon/vceqQs16.c: Remove.
+       * gcc.target/arm/neon/vceqQs32.c: Remove.
+       * gcc.target/arm/neon/vceqQs8.c: Remove.
+       * gcc.target/arm/neon/vceqQu16.c: Remove.
+       * gcc.target/arm/neon/vceqQu32.c: Remove.
+       * gcc.target/arm/neon/vceqQu8.c: Remove.
+       * gcc.target/arm/neon/vceqf32.c: Remove.
+       * gcc.target/arm/neon/vceqp8.c: Remove.
+       * gcc.target/arm/neon/vceqs16.c: Remove.
+       * gcc.target/arm/neon/vceqs32.c: Remove.
+       * gcc.target/arm/neon/vceqs8.c: Remove.
+       * gcc.target/arm/neon/vcequ16.c: Remove.
+       * gcc.target/arm/neon/vcequ32.c: Remove.
+       * gcc.target/arm/neon/vcequ8.c: Remove.
+       * gcc.target/arm/neon/vcgeQf32.c: Remove.
+       * gcc.target/arm/neon/vcgeQs16.c: Remove.
+       * gcc.target/arm/neon/vcgeQs32.c: Remove.
+       * gcc.target/arm/neon/vcgeQs8.c: Remove.
+       * gcc.target/arm/neon/vcgeQu16.c: Remove.
+       * gcc.target/arm/neon/vcgeQu32.c: Remove.
+       * gcc.target/arm/neon/vcgeQu8.c: Remove.
+       * gcc.target/arm/neon/vcgef32.c: Remove.
+       * gcc.target/arm/neon/vcges16.c: Remove.
+       * gcc.target/arm/neon/vcges32.c: Remove.
+       * gcc.target/arm/neon/vcges8.c: Remove.
+       * gcc.target/arm/neon/vcgeu16.c: Remove.
+       * gcc.target/arm/neon/vcgeu32.c: Remove.
+       * gcc.target/arm/neon/vcgeu8.c: Remove.
+       * gcc.target/arm/neon/vcgtQf32.c: Remove.
+       * gcc.target/arm/neon/vcgtQs16.c: Remove.
+       * gcc.target/arm/neon/vcgtQs32.c: Remove.
+       * gcc.target/arm/neon/vcgtQs8.c: Remove.
+       * gcc.target/arm/neon/vcgtQu16.c: Remove.
+       * gcc.target/arm/neon/vcgtQu32.c: Remove.
+       * gcc.target/arm/neon/vcgtQu8.c: Remove.
+       * gcc.target/arm/neon/vcgtf32.c: Remove.
+       * gcc.target/arm/neon/vcgts16.c: Remove.
+       * gcc.target/arm/neon/vcgts32.c: Remove.
+       * gcc.target/arm/neon/vcgts8.c: Remove.
+       * gcc.target/arm/neon/vcgtu16.c: Remove.
+       * gcc.target/arm/neon/vcgtu32.c: Remove.
+       * gcc.target/arm/neon/vcgtu8.c: Remove.
+       * gcc.target/arm/neon/vcleQf32.c: Remove.
+       * gcc.target/arm/neon/vcleQs16.c: Remove.
+       * gcc.target/arm/neon/vcleQs32.c: Remove.
+       * gcc.target/arm/neon/vcleQs8.c: Remove.
+       * gcc.target/arm/neon/vcleQu16.c: Remove.
+       * gcc.target/arm/neon/vcleQu32.c: Remove.
+       * gcc.target/arm/neon/vcleQu8.c: Remove.
+       * gcc.target/arm/neon/vclef32.c: Remove.
+       * gcc.target/arm/neon/vcles16.c: Remove.
+       * gcc.target/arm/neon/vcles32.c: Remove.
+       * gcc.target/arm/neon/vcles8.c: Remove.
+       * gcc.target/arm/neon/vcleu16.c: Remove.
+       * gcc.target/arm/neon/vcleu32.c: Remove.
+       * gcc.target/arm/neon/vcleu8.c: Remove.
+       * gcc.target/arm/neon/vclsQs16.c: Remove.
+       * gcc.target/arm/neon/vclsQs32.c: Remove.
+       * gcc.target/arm/neon/vclsQs8.c: Remove.
+       * gcc.target/arm/neon/vclss16.c: Remove.
+       * gcc.target/arm/neon/vclss32.c: Remove.
+       * gcc.target/arm/neon/vclss8.c: Remove.
+       * gcc.target/arm/neon/vcltQf32.c: Remove.
+       * gcc.target/arm/neon/vcltQs16.c: Remove.
+       * gcc.target/arm/neon/vcltQs32.c: Remove.
+       * gcc.target/arm/neon/vcltQs8.c: Remove.
+       * gcc.target/arm/neon/vcltQu16.c: Remove.
+       * gcc.target/arm/neon/vcltQu32.c: Remove.
+       * gcc.target/arm/neon/vcltQu8.c: Remove.
+       * gcc.target/arm/neon/vcltf32.c: Remove.
+       * gcc.target/arm/neon/vclts16.c: Remove.
+       * gcc.target/arm/neon/vclts32.c: Remove.
+       * gcc.target/arm/neon/vclts8.c: Remove.
+       * gcc.target/arm/neon/vcltu16.c: Remove.
+       * gcc.target/arm/neon/vcltu32.c: Remove.
+       * gcc.target/arm/neon/vcltu8.c: Remove.
+       * gcc.target/arm/neon/vclzQs16.c: Remove.
+       * gcc.target/arm/neon/vclzQs32.c: Remove.
+       * gcc.target/arm/neon/vclzQs8.c: Remove.
+       * gcc.target/arm/neon/vclzQu16.c: Remove.
+       * gcc.target/arm/neon/vclzQu32.c: Remove.
+       * gcc.target/arm/neon/vclzQu8.c: Remove.
+       * gcc.target/arm/neon/vclzs16.c: Remove.
+       * gcc.target/arm/neon/vclzs32.c: Remove.
+       * gcc.target/arm/neon/vclzs8.c: Remove.
+       * gcc.target/arm/neon/vclzu16.c: Remove.
+       * gcc.target/arm/neon/vclzu32.c: Remove.
+       * gcc.target/arm/neon/vclzu8.c: Remove.
+       * gcc.target/arm/neon/vcntQp8.c: Remove.
+       * gcc.target/arm/neon/vcntQs8.c: Remove.
+       * gcc.target/arm/neon/vcntQu8.c: Remove.
+       * gcc.target/arm/neon/vcntp8.c: Remove.
+       * gcc.target/arm/neon/vcnts8.c: Remove.
+       * gcc.target/arm/neon/vcntu8.c: Remove.
+       * gcc.target/arm/neon/vcombinef32.c: Remove.
+       * gcc.target/arm/neon/vcombinep16.c: Remove.
+       * gcc.target/arm/neon/vcombinep64.c: Remove.
+       * gcc.target/arm/neon/vcombinep8.c: Remove.
+       * gcc.target/arm/neon/vcombines16.c: Remove.
+       * gcc.target/arm/neon/vcombines32.c: Remove.
+       * gcc.target/arm/neon/vcombines64.c: Remove.
+       * gcc.target/arm/neon/vcombines8.c: Remove.
+       * gcc.target/arm/neon/vcombineu16.c: Remove.
+       * gcc.target/arm/neon/vcombineu32.c: Remove.
+       * gcc.target/arm/neon/vcombineu64.c: Remove.
+       * gcc.target/arm/neon/vcombineu8.c: Remove.
+       * gcc.target/arm/neon/vcreatef32.c: Remove.
+       * gcc.target/arm/neon/vcreatep16.c: Remove.
+       * gcc.target/arm/neon/vcreatep64.c: Remove.
+       * gcc.target/arm/neon/vcreatep8.c: Remove.
+       * gcc.target/arm/neon/vcreates16.c: Remove.
+       * gcc.target/arm/neon/vcreates32.c: Remove.
+       * gcc.target/arm/neon/vcreates64.c: Remove.
+       * gcc.target/arm/neon/vcreates8.c: Remove.
+       * gcc.target/arm/neon/vcreateu16.c: Remove.
+       * gcc.target/arm/neon/vcreateu32.c: Remove.
+       * gcc.target/arm/neon/vcreateu64.c: Remove.
+       * gcc.target/arm/neon/vcreateu8.c: Remove.
+       * gcc.target/arm/neon/vcvtQ_nf32_s32.c: Remove.
+       * gcc.target/arm/neon/vcvtQ_nf32_u32.c: Remove.
+       * gcc.target/arm/neon/vcvtQ_ns32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtQ_nu32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtQf32_s32.c: Remove.
+       * gcc.target/arm/neon/vcvtQf32_u32.c: Remove.
+       * gcc.target/arm/neon/vcvtQs32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtQu32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvt_nf32_s32.c: Remove.
+       * gcc.target/arm/neon/vcvt_nf32_u32.c: Remove.
+       * gcc.target/arm/neon/vcvt_ns32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvt_nu32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtf16_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtf32_f16.c: Remove.
+       * gcc.target/arm/neon/vcvtf32_s32.c: Remove.
+       * gcc.target/arm/neon/vcvtf32_u32.c: Remove.
+       * gcc.target/arm/neon/vcvts32_f32.c: Remove.
+       * gcc.target/arm/neon/vcvtu32_f32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanep16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanep64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanep8.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanes64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_lanes8.c: Remove.
+       * gcc.target/arm/neon/vdupQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_laneu64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_laneu8.c: Remove.
+       * gcc.target/arm/neon/vdupQ_nf32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_np16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_np64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_np8.c: Remove.
+       * gcc.target/arm/neon/vdupQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vdupQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vdupQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vdupQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vdupQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vdup_lanef32.c: Remove.
+       * gcc.target/arm/neon/vdup_lanep16.c: Remove.
+       * gcc.target/arm/neon/vdup_lanep64.c: Remove.
+       * gcc.target/arm/neon/vdup_lanep8.c: Remove.
+       * gcc.target/arm/neon/vdup_lanes16.c: Remove.
+       * gcc.target/arm/neon/vdup_lanes32.c: Remove.
+       * gcc.target/arm/neon/vdup_lanes64.c: Remove.
+       * gcc.target/arm/neon/vdup_lanes8.c: Remove.
+       * gcc.target/arm/neon/vdup_laneu16.c: Remove.
+       * gcc.target/arm/neon/vdup_laneu32.c: Remove.
+       * gcc.target/arm/neon/vdup_laneu64.c: Remove.
+       * gcc.target/arm/neon/vdup_laneu8.c: Remove.
+       * gcc.target/arm/neon/vdup_nf32.c: Remove.
+       * gcc.target/arm/neon/vdup_np16.c: Remove.
+       * gcc.target/arm/neon/vdup_np64.c: Remove.
+       * gcc.target/arm/neon/vdup_np8.c: Remove.
+       * gcc.target/arm/neon/vdup_ns16.c: Remove.
+       * gcc.target/arm/neon/vdup_ns32.c: Remove.
+       * gcc.target/arm/neon/vdup_ns64.c: Remove.
+       * gcc.target/arm/neon/vdup_ns8.c: Remove.
+       * gcc.target/arm/neon/vdup_nu16.c: Remove.
+       * gcc.target/arm/neon/vdup_nu32.c: Remove.
+       * gcc.target/arm/neon/vdup_nu64.c: Remove.
+       * gcc.target/arm/neon/vdup_nu8.c: Remove.
+       * gcc.target/arm/neon/veorQs16.c: Remove.
+       * gcc.target/arm/neon/veorQs32.c: Remove.
+       * gcc.target/arm/neon/veorQs64.c: Remove.
+       * gcc.target/arm/neon/veorQs8.c: Remove.
+       * gcc.target/arm/neon/veorQu16.c: Remove.
+       * gcc.target/arm/neon/veorQu32.c: Remove.
+       * gcc.target/arm/neon/veorQu64.c: Remove.
+       * gcc.target/arm/neon/veorQu8.c: Remove.
+       * gcc.target/arm/neon/veors16.c: Remove.
+       * gcc.target/arm/neon/veors32.c: Remove.
+       * gcc.target/arm/neon/veors64.c: Remove.
+       * gcc.target/arm/neon/veors8.c: Remove.
+       * gcc.target/arm/neon/veoru16.c: Remove.
+       * gcc.target/arm/neon/veoru32.c: Remove.
+       * gcc.target/arm/neon/veoru64.c: Remove.
+       * gcc.target/arm/neon/veoru8.c: Remove.
+       * gcc.target/arm/neon/vextQf32.c: Remove.
+       * gcc.target/arm/neon/vextQp16.c: Remove.
+       * gcc.target/arm/neon/vextQp64.c: Remove.
+       * gcc.target/arm/neon/vextQp8.c: Remove.
+       * gcc.target/arm/neon/vextQs16.c: Remove.
+       * gcc.target/arm/neon/vextQs32.c: Remove.
+       * gcc.target/arm/neon/vextQs64.c: Remove.
+       * gcc.target/arm/neon/vextQs8.c: Remove.
+       * gcc.target/arm/neon/vextQu16.c: Remove.
+       * gcc.target/arm/neon/vextQu32.c: Remove.
+       * gcc.target/arm/neon/vextQu64.c: Remove.
+       * gcc.target/arm/neon/vextQu8.c: Remove.
+       * gcc.target/arm/neon/vextf32.c: Remove.
+       * gcc.target/arm/neon/vextp16.c: Remove.
+       * gcc.target/arm/neon/vextp64.c: Remove.
+       * gcc.target/arm/neon/vextp8.c: Remove.
+       * gcc.target/arm/neon/vexts16.c: Remove.
+       * gcc.target/arm/neon/vexts32.c: Remove.
+       * gcc.target/arm/neon/vexts64.c: Remove.
+       * gcc.target/arm/neon/vexts8.c: Remove.
+       * gcc.target/arm/neon/vextu16.c: Remove.
+       * gcc.target/arm/neon/vextu32.c: Remove.
+       * gcc.target/arm/neon/vextu64.c: Remove.
+       * gcc.target/arm/neon/vextu8.c: Remove.
+       * gcc.target/arm/neon/vfmaQf32.c: Remove.
+       * gcc.target/arm/neon/vfmaf32.c: Remove.
+       * gcc.target/arm/neon/vfmsQf32.c: Remove.
+       * gcc.target/arm/neon/vfmsf32.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanep16.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanep8.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanes64.c: Remove.
+       * gcc.target/arm/neon/vgetQ_lanes8.c: Remove.
+       * gcc.target/arm/neon/vgetQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vgetQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vgetQ_laneu64.c: Remove.
+       * gcc.target/arm/neon/vgetQ_laneu8.c: Remove.
+       * gcc.target/arm/neon/vget_highf32.c: Remove.
+       * gcc.target/arm/neon/vget_highp16.c: Remove.
+       * gcc.target/arm/neon/vget_highp64.c: Remove.
+       * gcc.target/arm/neon/vget_highp8.c: Remove.
+       * gcc.target/arm/neon/vget_highs16.c: Remove.
+       * gcc.target/arm/neon/vget_highs32.c: Remove.
+       * gcc.target/arm/neon/vget_highs64.c: Remove.
+       * gcc.target/arm/neon/vget_highs8.c: Remove.
+       * gcc.target/arm/neon/vget_highu16.c: Remove.
+       * gcc.target/arm/neon/vget_highu32.c: Remove.
+       * gcc.target/arm/neon/vget_highu64.c: Remove.
+       * gcc.target/arm/neon/vget_highu8.c: Remove.
+       * gcc.target/arm/neon/vget_lanef32.c: Remove.
+       * gcc.target/arm/neon/vget_lanep16.c: Remove.
+       * gcc.target/arm/neon/vget_lanep8.c: Remove.
+       * gcc.target/arm/neon/vget_lanes16.c: Remove.
+       * gcc.target/arm/neon/vget_lanes32.c: Remove.
+       * gcc.target/arm/neon/vget_lanes64.c: Remove.
+       * gcc.target/arm/neon/vget_lanes8.c: Remove.
+       * gcc.target/arm/neon/vget_laneu16.c: Remove.
+       * gcc.target/arm/neon/vget_laneu32.c: Remove.
+       * gcc.target/arm/neon/vget_laneu64.c: Remove.
+       * gcc.target/arm/neon/vget_laneu8.c: Remove.
+       * gcc.target/arm/neon/vget_lowf32.c: Remove.
+       * gcc.target/arm/neon/vget_lowp16.c: Remove.
+       * gcc.target/arm/neon/vget_lowp64.c: Remove.
+       * gcc.target/arm/neon/vget_lowp8.c: Remove.
+       * gcc.target/arm/neon/vget_lows16.c: Remove.
+       * gcc.target/arm/neon/vget_lows32.c: Remove.
+       * gcc.target/arm/neon/vget_lows64.c: Remove.
+       * gcc.target/arm/neon/vget_lows8.c: Remove.
+       * gcc.target/arm/neon/vget_lowu16.c: Remove.
+       * gcc.target/arm/neon/vget_lowu32.c: Remove.
+       * gcc.target/arm/neon/vget_lowu64.c: Remove.
+       * gcc.target/arm/neon/vget_lowu8.c: Remove.
+       * gcc.target/arm/neon/vhaddQs16.c: Remove.
+       * gcc.target/arm/neon/vhaddQs32.c: Remove.
+       * gcc.target/arm/neon/vhaddQs8.c: Remove.
+       * gcc.target/arm/neon/vhaddQu16.c: Remove.
+       * gcc.target/arm/neon/vhaddQu32.c: Remove.
+       * gcc.target/arm/neon/vhaddQu8.c: Remove.
+       * gcc.target/arm/neon/vhadds16.c: Remove.
+       * gcc.target/arm/neon/vhadds32.c: Remove.
+       * gcc.target/arm/neon/vhadds8.c: Remove.
+       * gcc.target/arm/neon/vhaddu16.c: Remove.
+       * gcc.target/arm/neon/vhaddu32.c: Remove.
+       * gcc.target/arm/neon/vhaddu8.c: Remove.
+       * gcc.target/arm/neon/vhsubQs16.c: Remove.
+       * gcc.target/arm/neon/vhsubQs32.c: Remove.
+       * gcc.target/arm/neon/vhsubQs8.c: Remove.
+       * gcc.target/arm/neon/vhsubQu16.c: Remove.
+       * gcc.target/arm/neon/vhsubQu32.c: Remove.
+       * gcc.target/arm/neon/vhsubQu8.c: Remove.
+       * gcc.target/arm/neon/vhsubs16.c: Remove.
+       * gcc.target/arm/neon/vhsubs32.c: Remove.
+       * gcc.target/arm/neon/vhsubs8.c: Remove.
+       * gcc.target/arm/neon/vhsubu16.c: Remove.
+       * gcc.target/arm/neon/vhsubu32.c: Remove.
+       * gcc.target/arm/neon/vhsubu8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupf32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupp16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupp64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupp8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dups16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dups32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dups64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dups8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupu16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupu32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupu64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_dupu8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanep64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanep8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanes64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_lanes8.c: Remove.
+       * gcc.target/arm/neon/vld1Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld1Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld1Q_laneu64.c: Remove.
+       * gcc.target/arm/neon/vld1Q_laneu8.c: Remove.
+       * gcc.target/arm/neon/vld1Qf32.c: Remove.
+       * gcc.target/arm/neon/vld1Qp16.c: Remove.
+       * gcc.target/arm/neon/vld1Qp64.c: Remove.
+       * gcc.target/arm/neon/vld1Qp8.c: Remove.
+       * gcc.target/arm/neon/vld1Qs16.c: Remove.
+       * gcc.target/arm/neon/vld1Qs32.c: Remove.
+       * gcc.target/arm/neon/vld1Qs64.c: Remove.
+       * gcc.target/arm/neon/vld1Qs8.c: Remove.
+       * gcc.target/arm/neon/vld1Qu16.c: Remove.
+       * gcc.target/arm/neon/vld1Qu32.c: Remove.
+       * gcc.target/arm/neon/vld1Qu64.c: Remove.
+       * gcc.target/arm/neon/vld1Qu8.c: Remove.
+       * gcc.target/arm/neon/vld1_dupf32.c: Remove.
+       * gcc.target/arm/neon/vld1_dupp16.c: Remove.
+       * gcc.target/arm/neon/vld1_dupp64.c: Remove.
+       * gcc.target/arm/neon/vld1_dupp8.c: Remove.
+       * gcc.target/arm/neon/vld1_dups16.c: Remove.
+       * gcc.target/arm/neon/vld1_dups32.c: Remove.
+       * gcc.target/arm/neon/vld1_dups64.c: Remove.
+       * gcc.target/arm/neon/vld1_dups8.c: Remove.
+       * gcc.target/arm/neon/vld1_dupu16.c: Remove.
+       * gcc.target/arm/neon/vld1_dupu32.c: Remove.
+       * gcc.target/arm/neon/vld1_dupu64.c: Remove.
+       * gcc.target/arm/neon/vld1_dupu8.c: Remove.
+       * gcc.target/arm/neon/vld1_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld1_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld1_lanep64.c: Remove.
+       * gcc.target/arm/neon/vld1_lanep8.c: Remove.
+       * gcc.target/arm/neon/vld1_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld1_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld1_lanes64.c: Remove.
+       * gcc.target/arm/neon/vld1_lanes8.c: Remove.
+       * gcc.target/arm/neon/vld1_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld1_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld1_laneu64.c: Remove.
+       * gcc.target/arm/neon/vld1_laneu8.c: Remove.
+       * gcc.target/arm/neon/vld1f32.c: Remove.
+       * gcc.target/arm/neon/vld1p16.c: Remove.
+       * gcc.target/arm/neon/vld1p64.c: Remove.
+       * gcc.target/arm/neon/vld1p8.c: Remove.
+       * gcc.target/arm/neon/vld1s16.c: Remove.
+       * gcc.target/arm/neon/vld1s32.c: Remove.
+       * gcc.target/arm/neon/vld1s64.c: Remove.
+       * gcc.target/arm/neon/vld1s8.c: Remove.
+       * gcc.target/arm/neon/vld1u16.c: Remove.
+       * gcc.target/arm/neon/vld1u32.c: Remove.
+       * gcc.target/arm/neon/vld1u64.c: Remove.
+       * gcc.target/arm/neon/vld1u8.c: Remove.
+       * gcc.target/arm/neon/vld2Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld2Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld2Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld2Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld2Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld2Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld2Qf32.c: Remove.
+       * gcc.target/arm/neon/vld2Qp16.c: Remove.
+       * gcc.target/arm/neon/vld2Qp8.c: Remove.
+       * gcc.target/arm/neon/vld2Qs16.c: Remove.
+       * gcc.target/arm/neon/vld2Qs32.c: Remove.
+       * gcc.target/arm/neon/vld2Qs8.c: Remove.
+       * gcc.target/arm/neon/vld2Qu16.c: Remove.
+       * gcc.target/arm/neon/vld2Qu32.c: Remove.
+       * gcc.target/arm/neon/vld2Qu8.c: Remove.
+       * gcc.target/arm/neon/vld2_dupf32.c: Remove.
+       * gcc.target/arm/neon/vld2_dupp16.c: Remove.
+       * gcc.target/arm/neon/vld2_dupp64.c: Remove.
+       * gcc.target/arm/neon/vld2_dupp8.c: Remove.
+       * gcc.target/arm/neon/vld2_dups16.c: Remove.
+       * gcc.target/arm/neon/vld2_dups32.c: Remove.
+       * gcc.target/arm/neon/vld2_dups64.c: Remove.
+       * gcc.target/arm/neon/vld2_dups8.c: Remove.
+       * gcc.target/arm/neon/vld2_dupu16.c: Remove.
+       * gcc.target/arm/neon/vld2_dupu32.c: Remove.
+       * gcc.target/arm/neon/vld2_dupu64.c: Remove.
+       * gcc.target/arm/neon/vld2_dupu8.c: Remove.
+       * gcc.target/arm/neon/vld2_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld2_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld2_lanep8.c: Remove.
+       * gcc.target/arm/neon/vld2_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld2_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld2_lanes8.c: Remove.
+       * gcc.target/arm/neon/vld2_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld2_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld2_laneu8.c: Remove.
+       * gcc.target/arm/neon/vld2f32.c: Remove.
+       * gcc.target/arm/neon/vld2p16.c: Remove.
+       * gcc.target/arm/neon/vld2p64.c: Remove.
+       * gcc.target/arm/neon/vld2p8.c: Remove.
+       * gcc.target/arm/neon/vld2s16.c: Remove.
+       * gcc.target/arm/neon/vld2s32.c: Remove.
+       * gcc.target/arm/neon/vld2s64.c: Remove.
+       * gcc.target/arm/neon/vld2s8.c: Remove.
+       * gcc.target/arm/neon/vld2u16.c: Remove.
+       * gcc.target/arm/neon/vld2u32.c: Remove.
+       * gcc.target/arm/neon/vld2u64.c: Remove.
+       * gcc.target/arm/neon/vld2u8.c: Remove.
+       * gcc.target/arm/neon/vld3Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld3Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld3Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld3Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld3Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld3Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld3Qf32.c: Remove.
+       * gcc.target/arm/neon/vld3Qp16.c: Remove.
+       * gcc.target/arm/neon/vld3Qp8.c: Remove.
+       * gcc.target/arm/neon/vld3Qs16.c: Remove.
+       * gcc.target/arm/neon/vld3Qs32.c: Remove.
+       * gcc.target/arm/neon/vld3Qs8.c: Remove.
+       * gcc.target/arm/neon/vld3Qu16.c: Remove.
+       * gcc.target/arm/neon/vld3Qu32.c: Remove.
+       * gcc.target/arm/neon/vld3Qu8.c: Remove.
+       * gcc.target/arm/neon/vld3_dupf32.c: Remove.
+       * gcc.target/arm/neon/vld3_dupp16.c: Remove.
+       * gcc.target/arm/neon/vld3_dupp64.c: Remove.
+       * gcc.target/arm/neon/vld3_dupp8.c: Remove.
+       * gcc.target/arm/neon/vld3_dups16.c: Remove.
+       * gcc.target/arm/neon/vld3_dups32.c: Remove.
+       * gcc.target/arm/neon/vld3_dups64.c: Remove.
+       * gcc.target/arm/neon/vld3_dups8.c: Remove.
+       * gcc.target/arm/neon/vld3_dupu16.c: Remove.
+       * gcc.target/arm/neon/vld3_dupu32.c: Remove.
+       * gcc.target/arm/neon/vld3_dupu64.c: Remove.
+       * gcc.target/arm/neon/vld3_dupu8.c: Remove.
+       * gcc.target/arm/neon/vld3_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld3_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld3_lanep8.c: Remove.
+       * gcc.target/arm/neon/vld3_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld3_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld3_lanes8.c: Remove.
+       * gcc.target/arm/neon/vld3_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld3_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld3_laneu8.c: Remove.
+       * gcc.target/arm/neon/vld3f32.c: Remove.
+       * gcc.target/arm/neon/vld3p16.c: Remove.
+       * gcc.target/arm/neon/vld3p64.c: Remove.
+       * gcc.target/arm/neon/vld3p8.c: Remove.
+       * gcc.target/arm/neon/vld3s16.c: Remove.
+       * gcc.target/arm/neon/vld3s32.c: Remove.
+       * gcc.target/arm/neon/vld3s64.c: Remove.
+       * gcc.target/arm/neon/vld3s8.c: Remove.
+       * gcc.target/arm/neon/vld3u16.c: Remove.
+       * gcc.target/arm/neon/vld3u32.c: Remove.
+       * gcc.target/arm/neon/vld3u64.c: Remove.
+       * gcc.target/arm/neon/vld3u8.c: Remove.
+       * gcc.target/arm/neon/vld4Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld4Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld4Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld4Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld4Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld4Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld4Qf32.c: Remove.
+       * gcc.target/arm/neon/vld4Qp16.c: Remove.
+       * gcc.target/arm/neon/vld4Qp8.c: Remove.
+       * gcc.target/arm/neon/vld4Qs16.c: Remove.
+       * gcc.target/arm/neon/vld4Qs32.c: Remove.
+       * gcc.target/arm/neon/vld4Qs8.c: Remove.
+       * gcc.target/arm/neon/vld4Qu16.c: Remove.
+       * gcc.target/arm/neon/vld4Qu32.c: Remove.
+       * gcc.target/arm/neon/vld4Qu8.c: Remove.
+       * gcc.target/arm/neon/vld4_dupf32.c: Remove.
+       * gcc.target/arm/neon/vld4_dupp16.c: Remove.
+       * gcc.target/arm/neon/vld4_dupp64.c: Remove.
+       * gcc.target/arm/neon/vld4_dupp8.c: Remove.
+       * gcc.target/arm/neon/vld4_dups16.c: Remove.
+       * gcc.target/arm/neon/vld4_dups32.c: Remove.
+       * gcc.target/arm/neon/vld4_dups64.c: Remove.
+       * gcc.target/arm/neon/vld4_dups8.c: Remove.
+       * gcc.target/arm/neon/vld4_dupu16.c: Remove.
+       * gcc.target/arm/neon/vld4_dupu32.c: Remove.
+       * gcc.target/arm/neon/vld4_dupu64.c: Remove.
+       * gcc.target/arm/neon/vld4_dupu8.c: Remove.
+       * gcc.target/arm/neon/vld4_lanef32.c: Remove.
+       * gcc.target/arm/neon/vld4_lanep16.c: Remove.
+       * gcc.target/arm/neon/vld4_lanep8.c: Remove.
+       * gcc.target/arm/neon/vld4_lanes16.c: Remove.
+       * gcc.target/arm/neon/vld4_lanes32.c: Remove.
+       * gcc.target/arm/neon/vld4_lanes8.c: Remove.
+       * gcc.target/arm/neon/vld4_laneu16.c: Remove.
+       * gcc.target/arm/neon/vld4_laneu32.c: Remove.
+       * gcc.target/arm/neon/vld4_laneu8.c: Remove.
+       * gcc.target/arm/neon/vld4f32.c: Remove.
+       * gcc.target/arm/neon/vld4p16.c: Remove.
+       * gcc.target/arm/neon/vld4p64.c: Remove.
+       * gcc.target/arm/neon/vld4p8.c: Remove.
+       * gcc.target/arm/neon/vld4s16.c: Remove.
+       * gcc.target/arm/neon/vld4s32.c: Remove.
+       * gcc.target/arm/neon/vld4s64.c: Remove.
+       * gcc.target/arm/neon/vld4s8.c: Remove.
+       * gcc.target/arm/neon/vld4u16.c: Remove.
+       * gcc.target/arm/neon/vld4u32.c: Remove.
+       * gcc.target/arm/neon/vld4u64.c: Remove.
+       * gcc.target/arm/neon/vld4u8.c: Remove.
+       * gcc.target/arm/neon/vmaxQf32.c: Remove.
+       * gcc.target/arm/neon/vmaxQs16.c: Remove.
+       * gcc.target/arm/neon/vmaxQs32.c: Remove.
+       * gcc.target/arm/neon/vmaxQs8.c: Remove.
+       * gcc.target/arm/neon/vmaxQu16.c: Remove.
+       * gcc.target/arm/neon/vmaxQu32.c: Remove.
+       * gcc.target/arm/neon/vmaxQu8.c: Remove.
+       * gcc.target/arm/neon/vmaxf32.c: Remove.
+       * gcc.target/arm/neon/vmaxs16.c: Remove.
+       * gcc.target/arm/neon/vmaxs32.c: Remove.
+       * gcc.target/arm/neon/vmaxs8.c: Remove.
+       * gcc.target/arm/neon/vmaxu16.c: Remove.
+       * gcc.target/arm/neon/vmaxu32.c: Remove.
+       * gcc.target/arm/neon/vmaxu8.c: Remove.
+       * gcc.target/arm/neon/vminQf32.c: Remove.
+       * gcc.target/arm/neon/vminQs16.c: Remove.
+       * gcc.target/arm/neon/vminQs32.c: Remove.
+       * gcc.target/arm/neon/vminQs8.c: Remove.
+       * gcc.target/arm/neon/vminQu16.c: Remove.
+       * gcc.target/arm/neon/vminQu32.c: Remove.
+       * gcc.target/arm/neon/vminQu8.c: Remove.
+       * gcc.target/arm/neon/vminf32.c: Remove.
+       * gcc.target/arm/neon/vmins16.c: Remove.
+       * gcc.target/arm/neon/vmins32.c: Remove.
+       * gcc.target/arm/neon/vmins8.c: Remove.
+       * gcc.target/arm/neon/vminu16.c: Remove.
+       * gcc.target/arm/neon/vminu32.c: Remove.
+       * gcc.target/arm/neon/vminu8.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_nf32.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vmlaQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlaQf32.c: Remove.
+       * gcc.target/arm/neon/vmlaQs16.c: Remove.
+       * gcc.target/arm/neon/vmlaQs32.c: Remove.
+       * gcc.target/arm/neon/vmlaQs8.c: Remove.
+       * gcc.target/arm/neon/vmlaQu16.c: Remove.
+       * gcc.target/arm/neon/vmlaQu32.c: Remove.
+       * gcc.target/arm/neon/vmlaQu8.c: Remove.
+       * gcc.target/arm/neon/vmla_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmla_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmla_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmla_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmla_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmla_nf32.c: Remove.
+       * gcc.target/arm/neon/vmla_ns16.c: Remove.
+       * gcc.target/arm/neon/vmla_ns32.c: Remove.
+       * gcc.target/arm/neon/vmla_nu16.c: Remove.
+       * gcc.target/arm/neon/vmla_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlaf32.c: Remove.
+       * gcc.target/arm/neon/vmlal_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmlal_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmlal_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmlal_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmlal_ns16.c: Remove.
+       * gcc.target/arm/neon/vmlal_ns32.c: Remove.
+       * gcc.target/arm/neon/vmlal_nu16.c: Remove.
+       * gcc.target/arm/neon/vmlal_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlals16.c: Remove.
+       * gcc.target/arm/neon/vmlals32.c: Remove.
+       * gcc.target/arm/neon/vmlals8.c: Remove.
+       * gcc.target/arm/neon/vmlalu16.c: Remove.
+       * gcc.target/arm/neon/vmlalu32.c: Remove.
+       * gcc.target/arm/neon/vmlalu8.c: Remove.
+       * gcc.target/arm/neon/vmlas16.c: Remove.
+       * gcc.target/arm/neon/vmlas32.c: Remove.
+       * gcc.target/arm/neon/vmlas8.c: Remove.
+       * gcc.target/arm/neon/vmlau16.c: Remove.
+       * gcc.target/arm/neon/vmlau32.c: Remove.
+       * gcc.target/arm/neon/vmlau8.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_nf32.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vmlsQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlsQf32.c: Remove.
+       * gcc.target/arm/neon/vmlsQs16.c: Remove.
+       * gcc.target/arm/neon/vmlsQs32.c: Remove.
+       * gcc.target/arm/neon/vmlsQs8.c: Remove.
+       * gcc.target/arm/neon/vmlsQu16.c: Remove.
+       * gcc.target/arm/neon/vmlsQu32.c: Remove.
+       * gcc.target/arm/neon/vmlsQu8.c: Remove.
+       * gcc.target/arm/neon/vmls_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmls_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmls_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmls_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmls_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmls_nf32.c: Remove.
+       * gcc.target/arm/neon/vmls_ns16.c: Remove.
+       * gcc.target/arm/neon/vmls_ns32.c: Remove.
+       * gcc.target/arm/neon/vmls_nu16.c: Remove.
+       * gcc.target/arm/neon/vmls_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlsf32.c: Remove.
+       * gcc.target/arm/neon/vmlsl_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmlsl_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmlsl_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmlsl_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmlsl_ns16.c: Remove.
+       * gcc.target/arm/neon/vmlsl_ns32.c: Remove.
+       * gcc.target/arm/neon/vmlsl_nu16.c: Remove.
+       * gcc.target/arm/neon/vmlsl_nu32.c: Remove.
+       * gcc.target/arm/neon/vmlsls16.c: Remove.
+       * gcc.target/arm/neon/vmlsls32.c: Remove.
+       * gcc.target/arm/neon/vmlsls8.c: Remove.
+       * gcc.target/arm/neon/vmlslu16.c: Remove.
+       * gcc.target/arm/neon/vmlslu32.c: Remove.
+       * gcc.target/arm/neon/vmlslu8.c: Remove.
+       * gcc.target/arm/neon/vmlss16.c: Remove.
+       * gcc.target/arm/neon/vmlss32.c: Remove.
+       * gcc.target/arm/neon/vmlss8.c: Remove.
+       * gcc.target/arm/neon/vmlsu16.c: Remove.
+       * gcc.target/arm/neon/vmlsu32.c: Remove.
+       * gcc.target/arm/neon/vmlsu8.c: Remove.
+       * gcc.target/arm/neon/vmovQ_nf32.c: Remove.
+       * gcc.target/arm/neon/vmovQ_np16.c: Remove.
+       * gcc.target/arm/neon/vmovQ_np8.c: Remove.
+       * gcc.target/arm/neon/vmovQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vmovQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vmovQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vmovQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vmovQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vmovQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vmovQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vmovQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vmov_nf32.c: Remove.
+       * gcc.target/arm/neon/vmov_np16.c: Remove.
+       * gcc.target/arm/neon/vmov_np8.c: Remove.
+       * gcc.target/arm/neon/vmov_ns16.c: Remove.
+       * gcc.target/arm/neon/vmov_ns32.c: Remove.
+       * gcc.target/arm/neon/vmov_ns64.c: Remove.
+       * gcc.target/arm/neon/vmov_ns8.c: Remove.
+       * gcc.target/arm/neon/vmov_nu16.c: Remove.
+       * gcc.target/arm/neon/vmov_nu32.c: Remove.
+       * gcc.target/arm/neon/vmov_nu64.c: Remove.
+       * gcc.target/arm/neon/vmov_nu8.c: Remove.
+       * gcc.target/arm/neon/vmovls16.c: Remove.
+       * gcc.target/arm/neon/vmovls32.c: Remove.
+       * gcc.target/arm/neon/vmovls8.c: Remove.
+       * gcc.target/arm/neon/vmovlu16.c: Remove.
+       * gcc.target/arm/neon/vmovlu32.c: Remove.
+       * gcc.target/arm/neon/vmovlu8.c: Remove.
+       * gcc.target/arm/neon/vmovns16.c: Remove.
+       * gcc.target/arm/neon/vmovns32.c: Remove.
+       * gcc.target/arm/neon/vmovns64.c: Remove.
+       * gcc.target/arm/neon/vmovnu16.c: Remove.
+       * gcc.target/arm/neon/vmovnu32.c: Remove.
+       * gcc.target/arm/neon/vmovnu64.c: Remove.
+       * gcc.target/arm/neon/vmulQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmulQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmulQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmulQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmulQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmulQ_nf32.c: Remove.
+       * gcc.target/arm/neon/vmulQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vmulQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vmulQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vmulQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vmulQf32.c: Remove.
+       * gcc.target/arm/neon/vmulQp8.c: Remove.
+       * gcc.target/arm/neon/vmulQs16.c: Remove.
+       * gcc.target/arm/neon/vmulQs32.c: Remove.
+       * gcc.target/arm/neon/vmulQs8.c: Remove.
+       * gcc.target/arm/neon/vmulQu16.c: Remove.
+       * gcc.target/arm/neon/vmulQu32.c: Remove.
+       * gcc.target/arm/neon/vmulQu8.c: Remove.
+       * gcc.target/arm/neon/vmul_lanef32.c: Remove.
+       * gcc.target/arm/neon/vmul_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmul_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmul_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmul_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmul_nf32.c: Remove.
+       * gcc.target/arm/neon/vmul_ns16.c: Remove.
+       * gcc.target/arm/neon/vmul_ns32.c: Remove.
+       * gcc.target/arm/neon/vmul_nu16.c: Remove.
+       * gcc.target/arm/neon/vmul_nu32.c: Remove.
+       * gcc.target/arm/neon/vmulf32.c: Remove.
+       * gcc.target/arm/neon/vmull_lanes16.c: Remove.
+       * gcc.target/arm/neon/vmull_lanes32.c: Remove.
+       * gcc.target/arm/neon/vmull_laneu16.c: Remove.
+       * gcc.target/arm/neon/vmull_laneu32.c: Remove.
+       * gcc.target/arm/neon/vmull_ns16.c: Remove.
+       * gcc.target/arm/neon/vmull_ns32.c: Remove.
+       * gcc.target/arm/neon/vmull_nu16.c: Remove.
+       * gcc.target/arm/neon/vmull_nu32.c: Remove.
+       * gcc.target/arm/neon/vmullp8.c: Remove.
+       * gcc.target/arm/neon/vmulls16.c: Remove.
+       * gcc.target/arm/neon/vmulls32.c: Remove.
+       * gcc.target/arm/neon/vmulls8.c: Remove.
+       * gcc.target/arm/neon/vmullu16.c: Remove.
+       * gcc.target/arm/neon/vmullu32.c: Remove.
+       * gcc.target/arm/neon/vmullu8.c: Remove.
+       * gcc.target/arm/neon/vmulp8.c: Remove.
+       * gcc.target/arm/neon/vmuls16.c: Remove.
+       * gcc.target/arm/neon/vmuls32.c: Remove.
+       * gcc.target/arm/neon/vmuls8.c: Remove.
+       * gcc.target/arm/neon/vmulu16.c: Remove.
+       * gcc.target/arm/neon/vmulu32.c: Remove.
+       * gcc.target/arm/neon/vmulu8.c: Remove.
+       * gcc.target/arm/neon/vmvnQp8.c: Remove.
+       * gcc.target/arm/neon/vmvnQs16.c: Remove.
+       * gcc.target/arm/neon/vmvnQs32.c: Remove.
+       * gcc.target/arm/neon/vmvnQs8.c: Remove.
+       * gcc.target/arm/neon/vmvnQu16.c: Remove.
+       * gcc.target/arm/neon/vmvnQu32.c: Remove.
+       * gcc.target/arm/neon/vmvnQu8.c: Remove.
+       * gcc.target/arm/neon/vmvnp8.c: Remove.
+       * gcc.target/arm/neon/vmvns16.c: Remove.
+       * gcc.target/arm/neon/vmvns32.c: Remove.
+       * gcc.target/arm/neon/vmvns8.c: Remove.
+       * gcc.target/arm/neon/vmvnu16.c: Remove.
+       * gcc.target/arm/neon/vmvnu32.c: Remove.
+       * gcc.target/arm/neon/vmvnu8.c: Remove.
+       * gcc.target/arm/neon/vnegQf32.c: Remove.
+       * gcc.target/arm/neon/vnegQs16.c: Remove.
+       * gcc.target/arm/neon/vnegQs32.c: Remove.
+       * gcc.target/arm/neon/vnegQs8.c: Remove.
+       * gcc.target/arm/neon/vnegf32.c: Remove.
+       * gcc.target/arm/neon/vnegs16.c: Remove.
+       * gcc.target/arm/neon/vnegs32.c: Remove.
+       * gcc.target/arm/neon/vnegs8.c: Remove.
+       * gcc.target/arm/neon/vornQs16.c: Remove.
+       * gcc.target/arm/neon/vornQs32.c: Remove.
+       * gcc.target/arm/neon/vornQs64.c: Remove.
+       * gcc.target/arm/neon/vornQs8.c: Remove.
+       * gcc.target/arm/neon/vornQu16.c: Remove.
+       * gcc.target/arm/neon/vornQu32.c: Remove.
+       * gcc.target/arm/neon/vornQu64.c: Remove.
+       * gcc.target/arm/neon/vornQu8.c: Remove.
+       * gcc.target/arm/neon/vorns16.c: Remove.
+       * gcc.target/arm/neon/vorns32.c: Remove.
+       * gcc.target/arm/neon/vorns64.c: Remove.
+       * gcc.target/arm/neon/vorns8.c: Remove.
+       * gcc.target/arm/neon/vornu16.c: Remove.
+       * gcc.target/arm/neon/vornu32.c: Remove.
+       * gcc.target/arm/neon/vornu64.c: Remove.
+       * gcc.target/arm/neon/vornu8.c: Remove.
+       * gcc.target/arm/neon/vorrQs16.c: Remove.
+       * gcc.target/arm/neon/vorrQs32.c: Remove.
+       * gcc.target/arm/neon/vorrQs64.c: Remove.
+       * gcc.target/arm/neon/vorrQs8.c: Remove.
+       * gcc.target/arm/neon/vorrQu16.c: Remove.
+       * gcc.target/arm/neon/vorrQu32.c: Remove.
+       * gcc.target/arm/neon/vorrQu64.c: Remove.
+       * gcc.target/arm/neon/vorrQu8.c: Remove.
+       * gcc.target/arm/neon/vorrs16.c: Remove.
+       * gcc.target/arm/neon/vorrs32.c: Remove.
+       * gcc.target/arm/neon/vorrs64.c: Remove.
+       * gcc.target/arm/neon/vorrs8.c: Remove.
+       * gcc.target/arm/neon/vorru16.c: Remove.
+       * gcc.target/arm/neon/vorru32.c: Remove.
+       * gcc.target/arm/neon/vorru64.c: Remove.
+       * gcc.target/arm/neon/vorru8.c: Remove.
+       * gcc.target/arm/neon/vpadalQs16.c: Remove.
+       * gcc.target/arm/neon/vpadalQs32.c: Remove.
+       * gcc.target/arm/neon/vpadalQs8.c: Remove.
+       * gcc.target/arm/neon/vpadalQu16.c: Remove.
+       * gcc.target/arm/neon/vpadalQu32.c: Remove.
+       * gcc.target/arm/neon/vpadalQu8.c: Remove.
+       * gcc.target/arm/neon/vpadals16.c: Remove.
+       * gcc.target/arm/neon/vpadals32.c: Remove.
+       * gcc.target/arm/neon/vpadals8.c: Remove.
+       * gcc.target/arm/neon/vpadalu16.c: Remove.
+       * gcc.target/arm/neon/vpadalu32.c: Remove.
+       * gcc.target/arm/neon/vpadalu8.c: Remove.
+       * gcc.target/arm/neon/vpaddf32.c: Remove.
+       * gcc.target/arm/neon/vpaddlQs16.c: Remove.
+       * gcc.target/arm/neon/vpaddlQs32.c: Remove.
+       * gcc.target/arm/neon/vpaddlQs8.c: Remove.
+       * gcc.target/arm/neon/vpaddlQu16.c: Remove.
+       * gcc.target/arm/neon/vpaddlQu32.c: Remove.
+       * gcc.target/arm/neon/vpaddlQu8.c: Remove.
+       * gcc.target/arm/neon/vpaddls16.c: Remove.
+       * gcc.target/arm/neon/vpaddls32.c: Remove.
+       * gcc.target/arm/neon/vpaddls8.c: Remove.
+       * gcc.target/arm/neon/vpaddlu16.c: Remove.
+       * gcc.target/arm/neon/vpaddlu32.c: Remove.
+       * gcc.target/arm/neon/vpaddlu8.c: Remove.
+       * gcc.target/arm/neon/vpadds16.c: Remove.
+       * gcc.target/arm/neon/vpadds32.c: Remove.
+       * gcc.target/arm/neon/vpadds8.c: Remove.
+       * gcc.target/arm/neon/vpaddu16.c: Remove.
+       * gcc.target/arm/neon/vpaddu32.c: Remove.
+       * gcc.target/arm/neon/vpaddu8.c: Remove.
+       * gcc.target/arm/neon/vpmaxf32.c: Remove.
+       * gcc.target/arm/neon/vpmaxs16.c: Remove.
+       * gcc.target/arm/neon/vpmaxs32.c: Remove.
+       * gcc.target/arm/neon/vpmaxs8.c: Remove.
+       * gcc.target/arm/neon/vpmaxu16.c: Remove.
+       * gcc.target/arm/neon/vpmaxu32.c: Remove.
+       * gcc.target/arm/neon/vpmaxu8.c: Remove.
+       * gcc.target/arm/neon/vpminf32.c: Remove.
+       * gcc.target/arm/neon/vpmins16.c: Remove.
+       * gcc.target/arm/neon/vpmins32.c: Remove.
+       * gcc.target/arm/neon/vpmins8.c: Remove.
+       * gcc.target/arm/neon/vpminu16.c: Remove.
+       * gcc.target/arm/neon/vpminu32.c: Remove.
+       * gcc.target/arm/neon/vpminu8.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQs16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhQs32.c: Remove.
+       * gcc.target/arm/neon/vqRdmulh_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulh_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqRdmulh_ns16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulh_ns32.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhs16.c: Remove.
+       * gcc.target/arm/neon/vqRdmulhs32.c: Remove.
+       * gcc.target/arm/neon/vqRshlQs16.c: Remove.
+       * gcc.target/arm/neon/vqRshlQs32.c: Remove.
+       * gcc.target/arm/neon/vqRshlQs64.c: Remove.
+       * gcc.target/arm/neon/vqRshlQs8.c: Remove.
+       * gcc.target/arm/neon/vqRshlQu16.c: Remove.
+       * gcc.target/arm/neon/vqRshlQu32.c: Remove.
+       * gcc.target/arm/neon/vqRshlQu64.c: Remove.
+       * gcc.target/arm/neon/vqRshlQu8.c: Remove.
+       * gcc.target/arm/neon/vqRshls16.c: Remove.
+       * gcc.target/arm/neon/vqRshls32.c: Remove.
+       * gcc.target/arm/neon/vqRshls64.c: Remove.
+       * gcc.target/arm/neon/vqRshls8.c: Remove.
+       * gcc.target/arm/neon/vqRshlu16.c: Remove.
+       * gcc.target/arm/neon/vqRshlu32.c: Remove.
+       * gcc.target/arm/neon/vqRshlu64.c: Remove.
+       * gcc.target/arm/neon/vqRshlu8.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_ns16.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_ns32.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_ns64.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_nu16.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_nu32.c: Remove.
+       * gcc.target/arm/neon/vqRshrn_nu64.c: Remove.
+       * gcc.target/arm/neon/vqRshrun_ns16.c: Remove.
+       * gcc.target/arm/neon/vqRshrun_ns32.c: Remove.
+       * gcc.target/arm/neon/vqRshrun_ns64.c: Remove.
+       * gcc.target/arm/neon/vqabsQs16.c: Remove.
+       * gcc.target/arm/neon/vqabsQs32.c: Remove.
+       * gcc.target/arm/neon/vqabsQs8.c: Remove.
+       * gcc.target/arm/neon/vqabss16.c: Remove.
+       * gcc.target/arm/neon/vqabss32.c: Remove.
+       * gcc.target/arm/neon/vqabss8.c: Remove.
+       * gcc.target/arm/neon/vqaddQs16.c: Remove.
+       * gcc.target/arm/neon/vqaddQs32.c: Remove.
+       * gcc.target/arm/neon/vqaddQs64.c: Remove.
+       * gcc.target/arm/neon/vqaddQs8.c: Remove.
+       * gcc.target/arm/neon/vqaddQu16.c: Remove.
+       * gcc.target/arm/neon/vqaddQu32.c: Remove.
+       * gcc.target/arm/neon/vqaddQu64.c: Remove.
+       * gcc.target/arm/neon/vqaddQu8.c: Remove.
+       * gcc.target/arm/neon/vqadds16.c: Remove.
+       * gcc.target/arm/neon/vqadds32.c: Remove.
+       * gcc.target/arm/neon/vqadds64.c: Remove.
+       * gcc.target/arm/neon/vqadds8.c: Remove.
+       * gcc.target/arm/neon/vqaddu16.c: Remove.
+       * gcc.target/arm/neon/vqaddu32.c: Remove.
+       * gcc.target/arm/neon/vqaddu64.c: Remove.
+       * gcc.target/arm/neon/vqaddu8.c: Remove.
+       * gcc.target/arm/neon/vqdmlal_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqdmlal_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqdmlal_ns16.c: Remove.
+       * gcc.target/arm/neon/vqdmlal_ns32.c: Remove.
+       * gcc.target/arm/neon/vqdmlals16.c: Remove.
+       * gcc.target/arm/neon/vqdmlals32.c: Remove.
+       * gcc.target/arm/neon/vqdmlsl_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqdmlsl_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqdmlsl_ns16.c: Remove.
+       * gcc.target/arm/neon/vqdmlsl_ns32.c: Remove.
+       * gcc.target/arm/neon/vqdmlsls16.c: Remove.
+       * gcc.target/arm/neon/vqdmlsls32.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQs16.c: Remove.
+       * gcc.target/arm/neon/vqdmulhQs32.c: Remove.
+       * gcc.target/arm/neon/vqdmulh_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqdmulh_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqdmulh_ns16.c: Remove.
+       * gcc.target/arm/neon/vqdmulh_ns32.c: Remove.
+       * gcc.target/arm/neon/vqdmulhs16.c: Remove.
+       * gcc.target/arm/neon/vqdmulhs32.c: Remove.
+       * gcc.target/arm/neon/vqdmull_lanes16.c: Remove.
+       * gcc.target/arm/neon/vqdmull_lanes32.c: Remove.
+       * gcc.target/arm/neon/vqdmull_ns16.c: Remove.
+       * gcc.target/arm/neon/vqdmull_ns32.c: Remove.
+       * gcc.target/arm/neon/vqdmulls16.c: Remove.
+       * gcc.target/arm/neon/vqdmulls32.c: Remove.
+       * gcc.target/arm/neon/vqmovns16.c: Remove.
+       * gcc.target/arm/neon/vqmovns32.c: Remove.
+       * gcc.target/arm/neon/vqmovns64.c: Remove.
+       * gcc.target/arm/neon/vqmovnu16.c: Remove.
+       * gcc.target/arm/neon/vqmovnu32.c: Remove.
+       * gcc.target/arm/neon/vqmovnu64.c: Remove.
+       * gcc.target/arm/neon/vqmovuns16.c: Remove.
+       * gcc.target/arm/neon/vqmovuns32.c: Remove.
+       * gcc.target/arm/neon/vqmovuns64.c: Remove.
+       * gcc.target/arm/neon/vqnegQs16.c: Remove.
+       * gcc.target/arm/neon/vqnegQs32.c: Remove.
+       * gcc.target/arm/neon/vqnegQs8.c: Remove.
+       * gcc.target/arm/neon/vqnegs16.c: Remove.
+       * gcc.target/arm/neon/vqnegs32.c: Remove.
+       * gcc.target/arm/neon/vqnegs8.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vqshlQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vqshlQs16.c: Remove.
+       * gcc.target/arm/neon/vqshlQs32.c: Remove.
+       * gcc.target/arm/neon/vqshlQs64.c: Remove.
+       * gcc.target/arm/neon/vqshlQs8.c: Remove.
+       * gcc.target/arm/neon/vqshlQu16.c: Remove.
+       * gcc.target/arm/neon/vqshlQu32.c: Remove.
+       * gcc.target/arm/neon/vqshlQu64.c: Remove.
+       * gcc.target/arm/neon/vqshlQu8.c: Remove.
+       * gcc.target/arm/neon/vqshl_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshl_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshl_ns64.c: Remove.
+       * gcc.target/arm/neon/vqshl_ns8.c: Remove.
+       * gcc.target/arm/neon/vqshl_nu16.c: Remove.
+       * gcc.target/arm/neon/vqshl_nu32.c: Remove.
+       * gcc.target/arm/neon/vqshl_nu64.c: Remove.
+       * gcc.target/arm/neon/vqshl_nu8.c: Remove.
+       * gcc.target/arm/neon/vqshls16.c: Remove.
+       * gcc.target/arm/neon/vqshls32.c: Remove.
+       * gcc.target/arm/neon/vqshls64.c: Remove.
+       * gcc.target/arm/neon/vqshls8.c: Remove.
+       * gcc.target/arm/neon/vqshlu16.c: Remove.
+       * gcc.target/arm/neon/vqshlu32.c: Remove.
+       * gcc.target/arm/neon/vqshlu64.c: Remove.
+       * gcc.target/arm/neon/vqshlu8.c: Remove.
+       * gcc.target/arm/neon/vqshluQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshluQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshluQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vqshluQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vqshlu_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshlu_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshlu_ns64.c: Remove.
+       * gcc.target/arm/neon/vqshlu_ns8.c: Remove.
+       * gcc.target/arm/neon/vqshrn_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshrn_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshrn_ns64.c: Remove.
+       * gcc.target/arm/neon/vqshrn_nu16.c: Remove.
+       * gcc.target/arm/neon/vqshrn_nu32.c: Remove.
+       * gcc.target/arm/neon/vqshrn_nu64.c: Remove.
+       * gcc.target/arm/neon/vqshrun_ns16.c: Remove.
+       * gcc.target/arm/neon/vqshrun_ns32.c: Remove.
+       * gcc.target/arm/neon/vqshrun_ns64.c: Remove.
+       * gcc.target/arm/neon/vqsubQs16.c: Remove.
+       * gcc.target/arm/neon/vqsubQs32.c: Remove.
+       * gcc.target/arm/neon/vqsubQs64.c: Remove.
+       * gcc.target/arm/neon/vqsubQs8.c: Remove.
+       * gcc.target/arm/neon/vqsubQu16.c: Remove.
+       * gcc.target/arm/neon/vqsubQu32.c: Remove.
+       * gcc.target/arm/neon/vqsubQu64.c: Remove.
+       * gcc.target/arm/neon/vqsubQu8.c: Remove.
+       * gcc.target/arm/neon/vqsubs16.c: Remove.
+       * gcc.target/arm/neon/vqsubs32.c: Remove.
+       * gcc.target/arm/neon/vqsubs64.c: Remove.
+       * gcc.target/arm/neon/vqsubs8.c: Remove.
+       * gcc.target/arm/neon/vqsubu16.c: Remove.
+       * gcc.target/arm/neon/vqsubu32.c: Remove.
+       * gcc.target/arm/neon/vqsubu64.c: Remove.
+       * gcc.target/arm/neon/vqsubu8.c: Remove.
+       * gcc.target/arm/neon/vrecpeQf32.c: Remove.
+       * gcc.target/arm/neon/vrecpeQu32.c: Remove.
+       * gcc.target/arm/neon/vrecpef32.c: Remove.
+       * gcc.target/arm/neon/vrecpeu32.c: Remove.
+       * gcc.target/arm/neon/vrecpsQf32.c: Remove.
+       * gcc.target/arm/neon/vrecpsf32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQf32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp128_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQp8_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQs8_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_p128.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretQu8_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretf32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretp8_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterprets8_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu16_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_u64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu32_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu64_u8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_f32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_p16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_p64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_p8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_s16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_s32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_s64.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_s8.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_u16.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_u32.c: Remove.
+       * gcc.target/arm/neon/vreinterpretu8_u64.c: Remove.
+       * gcc.target/arm/neon/vrev16Qp8.c: Remove.
+       * gcc.target/arm/neon/vrev16Qs8.c: Remove.
+       * gcc.target/arm/neon/vrev16Qu8.c: Remove.
+       * gcc.target/arm/neon/vrev16p8.c: Remove.
+       * gcc.target/arm/neon/vrev16s8.c: Remove.
+       * gcc.target/arm/neon/vrev16u8.c: Remove.
+       * gcc.target/arm/neon/vrev32Qp16.c: Remove.
+       * gcc.target/arm/neon/vrev32Qp8.c: Remove.
+       * gcc.target/arm/neon/vrev32Qs16.c: Remove.
+       * gcc.target/arm/neon/vrev32Qs8.c: Remove.
+       * gcc.target/arm/neon/vrev32Qu16.c: Remove.
+       * gcc.target/arm/neon/vrev32Qu8.c: Remove.
+       * gcc.target/arm/neon/vrev32p16.c: Remove.
+       * gcc.target/arm/neon/vrev32p8.c: Remove.
+       * gcc.target/arm/neon/vrev32s16.c: Remove.
+       * gcc.target/arm/neon/vrev32s8.c: Remove.
+       * gcc.target/arm/neon/vrev32u16.c: Remove.
+       * gcc.target/arm/neon/vrev32u8.c: Remove.
+       * gcc.target/arm/neon/vrev64Qf32.c: Remove.
+       * gcc.target/arm/neon/vrev64Qp16.c: Remove.
+       * gcc.target/arm/neon/vrev64Qp8.c: Remove.
+       * gcc.target/arm/neon/vrev64Qs16.c: Remove.
+       * gcc.target/arm/neon/vrev64Qs32.c: Remove.
+       * gcc.target/arm/neon/vrev64Qs8.c: Remove.
+       * gcc.target/arm/neon/vrev64Qu16.c: Remove.
+       * gcc.target/arm/neon/vrev64Qu32.c: Remove.
+       * gcc.target/arm/neon/vrev64Qu8.c: Remove.
+       * gcc.target/arm/neon/vrev64f32.c: Remove.
+       * gcc.target/arm/neon/vrev64p16.c: Remove.
+       * gcc.target/arm/neon/vrev64p8.c: Remove.
+       * gcc.target/arm/neon/vrev64s16.c: Remove.
+       * gcc.target/arm/neon/vrev64s32.c: Remove.
+       * gcc.target/arm/neon/vrev64s8.c: Remove.
+       * gcc.target/arm/neon/vrev64u16.c: Remove.
+       * gcc.target/arm/neon/vrev64u32.c: Remove.
+       * gcc.target/arm/neon/vrev64u8.c: Remove.
+       * gcc.target/arm/neon/vrndaf32.c: Remove.
+       * gcc.target/arm/neon/vrndaqf32.c: Remove.
+       * gcc.target/arm/neon/vrndf32.c: Remove.
+       * gcc.target/arm/neon/vrndmf32.c: Remove.
+       * gcc.target/arm/neon/vrndmqf32.c: Remove.
+       * gcc.target/arm/neon/vrndnf32.c: Remove.
+       * gcc.target/arm/neon/vrndnqf32.c: Remove.
+       * gcc.target/arm/neon/vrndpf32.c: Remove.
+       * gcc.target/arm/neon/vrndpqf32.c: Remove.
+       * gcc.target/arm/neon/vrndqf32.c: Remove.
+       * gcc.target/arm/neon/vrsqrteQf32.c: Remove.
+       * gcc.target/arm/neon/vrsqrteQu32.c: Remove.
+       * gcc.target/arm/neon/vrsqrtef32.c: Remove.
+       * gcc.target/arm/neon/vrsqrteu32.c: Remove.
+       * gcc.target/arm/neon/vrsqrtsQf32.c: Remove.
+       * gcc.target/arm/neon/vrsqrtsf32.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanef32.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanep16.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanep8.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanes16.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanes32.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanes64.c: Remove.
+       * gcc.target/arm/neon/vsetQ_lanes8.c: Remove.
+       * gcc.target/arm/neon/vsetQ_laneu16.c: Remove.
+       * gcc.target/arm/neon/vsetQ_laneu32.c: Remove.
+       * gcc.target/arm/neon/vsetQ_laneu64.c: Remove.
+       * gcc.target/arm/neon/vsetQ_laneu8.c: Remove.
+       * gcc.target/arm/neon/vset_lanef32.c: Remove.
+       * gcc.target/arm/neon/vset_lanep16.c: Remove.
+       * gcc.target/arm/neon/vset_lanep8.c: Remove.
+       * gcc.target/arm/neon/vset_lanes16.c: Remove.
+       * gcc.target/arm/neon/vset_lanes32.c: Remove.
+       * gcc.target/arm/neon/vset_lanes64.c: Remove.
+       * gcc.target/arm/neon/vset_lanes8.c: Remove.
+       * gcc.target/arm/neon/vset_laneu16.c: Remove.
+       * gcc.target/arm/neon/vset_laneu32.c: Remove.
+       * gcc.target/arm/neon/vset_laneu64.c: Remove.
+       * gcc.target/arm/neon/vset_laneu8.c: Remove.
+       * gcc.target/arm/neon/vshlQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vshlQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vshlQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vshlQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vshlQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vshlQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vshlQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vshlQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vshlQs16.c: Remove.
+       * gcc.target/arm/neon/vshlQs32.c: Remove.
+       * gcc.target/arm/neon/vshlQs64.c: Remove.
+       * gcc.target/arm/neon/vshlQs8.c: Remove.
+       * gcc.target/arm/neon/vshlQu16.c: Remove.
+       * gcc.target/arm/neon/vshlQu32.c: Remove.
+       * gcc.target/arm/neon/vshlQu64.c: Remove.
+       * gcc.target/arm/neon/vshlQu8.c: Remove.
+       * gcc.target/arm/neon/vshl_ns16.c: Remove.
+       * gcc.target/arm/neon/vshl_ns32.c: Remove.
+       * gcc.target/arm/neon/vshl_ns64.c: Remove.
+       * gcc.target/arm/neon/vshl_ns8.c: Remove.
+       * gcc.target/arm/neon/vshl_nu16.c: Remove.
+       * gcc.target/arm/neon/vshl_nu32.c: Remove.
+       * gcc.target/arm/neon/vshl_nu64.c: Remove.
+       * gcc.target/arm/neon/vshl_nu8.c: Remove.
+       * gcc.target/arm/neon/vshll_ns16.c: Remove.
+       * gcc.target/arm/neon/vshll_ns32.c: Remove.
+       * gcc.target/arm/neon/vshll_ns8.c: Remove.
+       * gcc.target/arm/neon/vshll_nu16.c: Remove.
+       * gcc.target/arm/neon/vshll_nu32.c: Remove.
+       * gcc.target/arm/neon/vshll_nu8.c: Remove.
+       * gcc.target/arm/neon/vshls16.c: Remove.
+       * gcc.target/arm/neon/vshls32.c: Remove.
+       * gcc.target/arm/neon/vshls64.c: Remove.
+       * gcc.target/arm/neon/vshls8.c: Remove.
+       * gcc.target/arm/neon/vshlu16.c: Remove.
+       * gcc.target/arm/neon/vshlu32.c: Remove.
+       * gcc.target/arm/neon/vshlu64.c: Remove.
+       * gcc.target/arm/neon/vshlu8.c: Remove.
+       * gcc.target/arm/neon/vshrQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vshrQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vshrQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vshrQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vshrQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vshrQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vshrQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vshrQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vshr_ns16.c: Remove.
+       * gcc.target/arm/neon/vshr_ns32.c: Remove.
+       * gcc.target/arm/neon/vshr_ns64.c: Remove.
+       * gcc.target/arm/neon/vshr_ns8.c: Remove.
+       * gcc.target/arm/neon/vshr_nu16.c: Remove.
+       * gcc.target/arm/neon/vshr_nu32.c: Remove.
+       * gcc.target/arm/neon/vshr_nu64.c: Remove.
+       * gcc.target/arm/neon/vshr_nu8.c: Remove.
+       * gcc.target/arm/neon/vshrn_ns16.c: Remove.
+       * gcc.target/arm/neon/vshrn_ns32.c: Remove.
+       * gcc.target/arm/neon/vshrn_ns64.c: Remove.
+       * gcc.target/arm/neon/vshrn_nu16.c: Remove.
+       * gcc.target/arm/neon/vshrn_nu32.c: Remove.
+       * gcc.target/arm/neon/vshrn_nu64.c: Remove.
+       * gcc.target/arm/neon/vsliQ_np16.c: Remove.
+       * gcc.target/arm/neon/vsliQ_np64.c: Remove.
+       * gcc.target/arm/neon/vsliQ_np8.c: Remove.
+       * gcc.target/arm/neon/vsliQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vsliQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vsliQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vsliQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vsliQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vsliQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vsliQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vsliQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vsli_np16.c: Remove.
+       * gcc.target/arm/neon/vsli_np64.c: Remove.
+       * gcc.target/arm/neon/vsli_np8.c: Remove.
+       * gcc.target/arm/neon/vsli_ns16.c: Remove.
+       * gcc.target/arm/neon/vsli_ns32.c: Remove.
+       * gcc.target/arm/neon/vsli_ns64.c: Remove.
+       * gcc.target/arm/neon/vsli_ns8.c: Remove.
+       * gcc.target/arm/neon/vsli_nu16.c: Remove.
+       * gcc.target/arm/neon/vsli_nu32.c: Remove.
+       * gcc.target/arm/neon/vsli_nu64.c: Remove.
+       * gcc.target/arm/neon/vsli_nu8.c: Remove.
+       * gcc.target/arm/neon/vsraQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vsraQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vsraQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vsraQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vsraQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vsraQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vsraQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vsraQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vsra_ns16.c: Remove.
+       * gcc.target/arm/neon/vsra_ns32.c: Remove.
+       * gcc.target/arm/neon/vsra_ns64.c: Remove.
+       * gcc.target/arm/neon/vsra_ns8.c: Remove.
+       * gcc.target/arm/neon/vsra_nu16.c: Remove.
+       * gcc.target/arm/neon/vsra_nu32.c: Remove.
+       * gcc.target/arm/neon/vsra_nu64.c: Remove.
+       * gcc.target/arm/neon/vsra_nu8.c: Remove.
+       * gcc.target/arm/neon/vsriQ_np16.c: Remove.
+       * gcc.target/arm/neon/vsriQ_np64.c: Remove.
+       * gcc.target/arm/neon/vsriQ_np8.c: Remove.
+       * gcc.target/arm/neon/vsriQ_ns16.c: Remove.
+       * gcc.target/arm/neon/vsriQ_ns32.c: Remove.
+       * gcc.target/arm/neon/vsriQ_ns64.c: Remove.
+       * gcc.target/arm/neon/vsriQ_ns8.c: Remove.
+       * gcc.target/arm/neon/vsriQ_nu16.c: Remove.
+       * gcc.target/arm/neon/vsriQ_nu32.c: Remove.
+       * gcc.target/arm/neon/vsriQ_nu64.c: Remove.
+       * gcc.target/arm/neon/vsriQ_nu8.c: Remove.
+       * gcc.target/arm/neon/vsri_np16.c: Remove.
+       * gcc.target/arm/neon/vsri_np64.c: Remove.
+       * gcc.target/arm/neon/vsri_np8.c: Remove.
+       * gcc.target/arm/neon/vsri_ns16.c: Remove.
+       * gcc.target/arm/neon/vsri_ns32.c: Remove.
+       * gcc.target/arm/neon/vsri_ns64.c: Remove.
+       * gcc.target/arm/neon/vsri_ns8.c: Remove.
+       * gcc.target/arm/neon/vsri_nu16.c: Remove.
+       * gcc.target/arm/neon/vsri_nu32.c: Remove.
+       * gcc.target/arm/neon/vsri_nu64.c: Remove.
+       * gcc.target/arm/neon/vsri_nu8.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanep64.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanep8.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanes64.c: Remove.
+       * gcc.target/arm/neon/vst1Q_lanes8.c: Remove.
+       * gcc.target/arm/neon/vst1Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst1Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst1Q_laneu64.c: Remove.
+       * gcc.target/arm/neon/vst1Q_laneu8.c: Remove.
+       * gcc.target/arm/neon/vst1Qf32.c: Remove.
+       * gcc.target/arm/neon/vst1Qp16.c: Remove.
+       * gcc.target/arm/neon/vst1Qp64.c: Remove.
+       * gcc.target/arm/neon/vst1Qp8.c: Remove.
+       * gcc.target/arm/neon/vst1Qs16.c: Remove.
+       * gcc.target/arm/neon/vst1Qs32.c: Remove.
+       * gcc.target/arm/neon/vst1Qs64.c: Remove.
+       * gcc.target/arm/neon/vst1Qs8.c: Remove.
+       * gcc.target/arm/neon/vst1Qu16.c: Remove.
+       * gcc.target/arm/neon/vst1Qu32.c: Remove.
+       * gcc.target/arm/neon/vst1Qu64.c: Remove.
+       * gcc.target/arm/neon/vst1Qu8.c: Remove.
+       * gcc.target/arm/neon/vst1_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst1_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst1_lanep64.c: Remove.
+       * gcc.target/arm/neon/vst1_lanep8.c: Remove.
+       * gcc.target/arm/neon/vst1_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst1_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst1_lanes64.c: Remove.
+       * gcc.target/arm/neon/vst1_lanes8.c: Remove.
+       * gcc.target/arm/neon/vst1_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst1_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst1_laneu64.c: Remove.
+       * gcc.target/arm/neon/vst1_laneu8.c: Remove.
+       * gcc.target/arm/neon/vst1f32.c: Remove.
+       * gcc.target/arm/neon/vst1p16.c: Remove.
+       * gcc.target/arm/neon/vst1p64.c: Remove.
+       * gcc.target/arm/neon/vst1p8.c: Remove.
+       * gcc.target/arm/neon/vst1s16.c: Remove.
+       * gcc.target/arm/neon/vst1s32.c: Remove.
+       * gcc.target/arm/neon/vst1s64.c: Remove.
+       * gcc.target/arm/neon/vst1s8.c: Remove.
+       * gcc.target/arm/neon/vst1u16.c: Remove.
+       * gcc.target/arm/neon/vst1u32.c: Remove.
+       * gcc.target/arm/neon/vst1u64.c: Remove.
+       * gcc.target/arm/neon/vst1u8.c: Remove.
+       * gcc.target/arm/neon/vst2Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst2Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst2Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst2Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst2Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst2Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst2Qf32.c: Remove.
+       * gcc.target/arm/neon/vst2Qp16.c: Remove.
+       * gcc.target/arm/neon/vst2Qp8.c: Remove.
+       * gcc.target/arm/neon/vst2Qs16.c: Remove.
+       * gcc.target/arm/neon/vst2Qs32.c: Remove.
+       * gcc.target/arm/neon/vst2Qs8.c: Remove.
+       * gcc.target/arm/neon/vst2Qu16.c: Remove.
+       * gcc.target/arm/neon/vst2Qu32.c: Remove.
+       * gcc.target/arm/neon/vst2Qu8.c: Remove.
+       * gcc.target/arm/neon/vst2_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst2_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst2_lanep8.c: Remove.
+       * gcc.target/arm/neon/vst2_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst2_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst2_lanes8.c: Remove.
+       * gcc.target/arm/neon/vst2_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst2_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst2_laneu8.c: Remove.
+       * gcc.target/arm/neon/vst2f32.c: Remove.
+       * gcc.target/arm/neon/vst2p16.c: Remove.
+       * gcc.target/arm/neon/vst2p64.c: Remove.
+       * gcc.target/arm/neon/vst2p8.c: Remove.
+       * gcc.target/arm/neon/vst2s16.c: Remove.
+       * gcc.target/arm/neon/vst2s32.c: Remove.
+       * gcc.target/arm/neon/vst2s64.c: Remove.
+       * gcc.target/arm/neon/vst2s8.c: Remove.
+       * gcc.target/arm/neon/vst2u16.c: Remove.
+       * gcc.target/arm/neon/vst2u32.c: Remove.
+       * gcc.target/arm/neon/vst2u64.c: Remove.
+       * gcc.target/arm/neon/vst2u8.c: Remove.
+       * gcc.target/arm/neon/vst3Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst3Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst3Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst3Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst3Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst3Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst3Qf32.c: Remove.
+       * gcc.target/arm/neon/vst3Qp16.c: Remove.
+       * gcc.target/arm/neon/vst3Qp8.c: Remove.
+       * gcc.target/arm/neon/vst3Qs16.c: Remove.
+       * gcc.target/arm/neon/vst3Qs32.c: Remove.
+       * gcc.target/arm/neon/vst3Qs8.c: Remove.
+       * gcc.target/arm/neon/vst3Qu16.c: Remove.
+       * gcc.target/arm/neon/vst3Qu32.c: Remove.
+       * gcc.target/arm/neon/vst3Qu8.c: Remove.
+       * gcc.target/arm/neon/vst3_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst3_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst3_lanep8.c: Remove.
+       * gcc.target/arm/neon/vst3_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst3_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst3_lanes8.c: Remove.
+       * gcc.target/arm/neon/vst3_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst3_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst3_laneu8.c: Remove.
+       * gcc.target/arm/neon/vst3f32.c: Remove.
+       * gcc.target/arm/neon/vst3p16.c: Remove.
+       * gcc.target/arm/neon/vst3p64.c: Remove.
+       * gcc.target/arm/neon/vst3p8.c: Remove.
+       * gcc.target/arm/neon/vst3s16.c: Remove.
+       * gcc.target/arm/neon/vst3s32.c: Remove.
+       * gcc.target/arm/neon/vst3s64.c: Remove.
+       * gcc.target/arm/neon/vst3s8.c: Remove.
+       * gcc.target/arm/neon/vst3u16.c: Remove.
+       * gcc.target/arm/neon/vst3u32.c: Remove.
+       * gcc.target/arm/neon/vst3u64.c: Remove.
+       * gcc.target/arm/neon/vst3u8.c: Remove.
+       * gcc.target/arm/neon/vst4Q_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst4Q_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst4Q_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst4Q_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst4Q_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst4Q_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst4Qf32.c: Remove.
+       * gcc.target/arm/neon/vst4Qp16.c: Remove.
+       * gcc.target/arm/neon/vst4Qp8.c: Remove.
+       * gcc.target/arm/neon/vst4Qs16.c: Remove.
+       * gcc.target/arm/neon/vst4Qs32.c: Remove.
+       * gcc.target/arm/neon/vst4Qs8.c: Remove.
+       * gcc.target/arm/neon/vst4Qu16.c: Remove.
+       * gcc.target/arm/neon/vst4Qu32.c: Remove.
+       * gcc.target/arm/neon/vst4Qu8.c: Remove.
+       * gcc.target/arm/neon/vst4_lanef32.c: Remove.
+       * gcc.target/arm/neon/vst4_lanep16.c: Remove.
+       * gcc.target/arm/neon/vst4_lanep8.c: Remove.
+       * gcc.target/arm/neon/vst4_lanes16.c: Remove.
+       * gcc.target/arm/neon/vst4_lanes32.c: Remove.
+       * gcc.target/arm/neon/vst4_lanes8.c: Remove.
+       * gcc.target/arm/neon/vst4_laneu16.c: Remove.
+       * gcc.target/arm/neon/vst4_laneu32.c: Remove.
+       * gcc.target/arm/neon/vst4_laneu8.c: Remove.
+       * gcc.target/arm/neon/vst4f32.c: Remove.
+       * gcc.target/arm/neon/vst4p16.c: Remove.
+       * gcc.target/arm/neon/vst4p64.c: Remove.
+       * gcc.target/arm/neon/vst4p8.c: Remove.
+       * gcc.target/arm/neon/vst4s16.c: Remove.
+       * gcc.target/arm/neon/vst4s32.c: Remove.
+       * gcc.target/arm/neon/vst4s64.c: Remove.
+       * gcc.target/arm/neon/vst4s8.c: Remove.
+       * gcc.target/arm/neon/vst4u16.c: Remove.
+       * gcc.target/arm/neon/vst4u32.c: Remove.
+       * gcc.target/arm/neon/vst4u64.c: Remove.
+       * gcc.target/arm/neon/vst4u8.c: Remove.
+       * gcc.target/arm/neon/vsubQf32.c: Remove.
+       * gcc.target/arm/neon/vsubQs16.c: Remove.
+       * gcc.target/arm/neon/vsubQs32.c: Remove.
+       * gcc.target/arm/neon/vsubQs64.c: Remove.
+       * gcc.target/arm/neon/vsubQs8.c: Remove.
+       * gcc.target/arm/neon/vsubQu16.c: Remove.
+       * gcc.target/arm/neon/vsubQu32.c: Remove.
+       * gcc.target/arm/neon/vsubQu64.c: Remove.
+       * gcc.target/arm/neon/vsubQu8.c: Remove.
+       * gcc.target/arm/neon/vsubf32.c: Remove.
+       * gcc.target/arm/neon/vsubhns16.c: Remove.
+       * gcc.target/arm/neon/vsubhns32.c: Remove.
+       * gcc.target/arm/neon/vsubhns64.c: Remove.
+       * gcc.target/arm/neon/vsubhnu16.c: Remove.
+       * gcc.target/arm/neon/vsubhnu32.c: Remove.
+       * gcc.target/arm/neon/vsubhnu64.c: Remove.
+       * gcc.target/arm/neon/vsubls16.c: Remove.
+       * gcc.target/arm/neon/vsubls32.c: Remove.
+       * gcc.target/arm/neon/vsubls8.c: Remove.
+       * gcc.target/arm/neon/vsublu16.c: Remove.
+       * gcc.target/arm/neon/vsublu32.c: Remove.
+       * gcc.target/arm/neon/vsublu8.c: Remove.
+       * gcc.target/arm/neon/vsubs16.c: Remove.
+       * gcc.target/arm/neon/vsubs32.c: Remove.
+       * gcc.target/arm/neon/vsubs64.c: Remove.
+       * gcc.target/arm/neon/vsubs8.c: Remove.
+       * gcc.target/arm/neon/vsubu16.c: Remove.
+       * gcc.target/arm/neon/vsubu32.c: Remove.
+       * gcc.target/arm/neon/vsubu64.c: Remove.
+       * gcc.target/arm/neon/vsubu8.c: Remove.
+       * gcc.target/arm/neon/vsubws16.c: Remove.
+       * gcc.target/arm/neon/vsubws32.c: Remove.
+       * gcc.target/arm/neon/vsubws8.c: Remove.
+       * gcc.target/arm/neon/vsubwu16.c: Remove.
+       * gcc.target/arm/neon/vsubwu32.c: Remove.
+       * gcc.target/arm/neon/vsubwu8.c: Remove.
+       * gcc.target/arm/neon/vtbl1p8.c: Remove.
+       * gcc.target/arm/neon/vtbl1s8.c: Remove.
+       * gcc.target/arm/neon/vtbl1u8.c: Remove.
+       * gcc.target/arm/neon/vtbl2p8.c: Remove.
+       * gcc.target/arm/neon/vtbl2s8.c: Remove.
+       * gcc.target/arm/neon/vtbl2u8.c: Remove.
+       * gcc.target/arm/neon/vtbl3p8.c: Remove.
+       * gcc.target/arm/neon/vtbl3s8.c: Remove.
+       * gcc.target/arm/neon/vtbl3u8.c: Remove.
+       * gcc.target/arm/neon/vtbl4p8.c: Remove.
+       * gcc.target/arm/neon/vtbl4s8.c: Remove.
+       * gcc.target/arm/neon/vtbl4u8.c: Remove.
+       * gcc.target/arm/neon/vtbx1p8.c: Remove.
+       * gcc.target/arm/neon/vtbx1s8.c: Remove.
+       * gcc.target/arm/neon/vtbx1u8.c: Remove.
+       * gcc.target/arm/neon/vtbx2p8.c: Remove.
+       * gcc.target/arm/neon/vtbx2s8.c: Remove.
+       * gcc.target/arm/neon/vtbx2u8.c: Remove.
+       * gcc.target/arm/neon/vtbx3p8.c: Remove.
+       * gcc.target/arm/neon/vtbx3s8.c: Remove.
+       * gcc.target/arm/neon/vtbx3u8.c: Remove.
+       * gcc.target/arm/neon/vtbx4p8.c: Remove.
+       * gcc.target/arm/neon/vtbx4s8.c: Remove.
+       * gcc.target/arm/neon/vtbx4u8.c: Remove.
+       * gcc.target/arm/neon/vtrnQf32.c: Remove.
+       * gcc.target/arm/neon/vtrnQp16.c: Remove.
+       * gcc.target/arm/neon/vtrnQp8.c: Remove.
+       * gcc.target/arm/neon/vtrnQs16.c: Remove.
+       * gcc.target/arm/neon/vtrnQs32.c: Remove.
+       * gcc.target/arm/neon/vtrnQs8.c: Remove.
+       * gcc.target/arm/neon/vtrnQu16.c: Remove.
+       * gcc.target/arm/neon/vtrnQu32.c: Remove.
+       * gcc.target/arm/neon/vtrnQu8.c: Remove.
+       * gcc.target/arm/neon/vtrnf32.c: Remove.
+       * gcc.target/arm/neon/vtrnp16.c: Remove.
+       * gcc.target/arm/neon/vtrnp8.c: Remove.
+       * gcc.target/arm/neon/vtrns16.c: Remove.
+       * gcc.target/arm/neon/vtrns32.c: Remove.
+       * gcc.target/arm/neon/vtrns8.c: Remove.
+       * gcc.target/arm/neon/vtrnu16.c: Remove.
+       * gcc.target/arm/neon/vtrnu32.c: Remove.
+       * gcc.target/arm/neon/vtrnu8.c: Remove.
+       * gcc.target/arm/neon/vtstQp8.c: Remove.
+       * gcc.target/arm/neon/vtstQs16.c: Remove.
+       * gcc.target/arm/neon/vtstQs32.c: Remove.
+       * gcc.target/arm/neon/vtstQs8.c: Remove.
+       * gcc.target/arm/neon/vtstQu16.c: Remove.
+       * gcc.target/arm/neon/vtstQu32.c: Remove.
+       * gcc.target/arm/neon/vtstQu8.c: Remove.
+       * gcc.target/arm/neon/vtstp8.c: Remove.
+       * gcc.target/arm/neon/vtsts16.c: Remove.
+       * gcc.target/arm/neon/vtsts32.c: Remove.
+       * gcc.target/arm/neon/vtsts8.c: Remove.
+       * gcc.target/arm/neon/vtstu16.c: Remove.
+       * gcc.target/arm/neon/vtstu32.c: Remove.
+       * gcc.target/arm/neon/vtstu8.c: Remove.
+       * gcc.target/arm/neon/vuzpQf32.c: Remove.
+       * gcc.target/arm/neon/vuzpQp16.c: Remove.
+       * gcc.target/arm/neon/vuzpQp8.c: Remove.
+       * gcc.target/arm/neon/vuzpQs16.c: Remove.
+       * gcc.target/arm/neon/vuzpQs32.c: Remove.
+       * gcc.target/arm/neon/vuzpQs8.c: Remove.
+       * gcc.target/arm/neon/vuzpQu16.c: Remove.
+       * gcc.target/arm/neon/vuzpQu32.c: Remove.
+       * gcc.target/arm/neon/vuzpQu8.c: Remove.
+       * gcc.target/arm/neon/vuzpf32.c: Remove.
+       * gcc.target/arm/neon/vuzpp16.c: Remove.
+       * gcc.target/arm/neon/vuzpp8.c: Remove.
+       * gcc.target/arm/neon/vuzps16.c: Remove.
+       * gcc.target/arm/neon/vuzps32.c: Remove.
+       * gcc.target/arm/neon/vuzps8.c: Remove.
+       * gcc.target/arm/neon/vuzpu16.c: Remove.
+       * gcc.target/arm/neon/vuzpu32.c: Remove.
+       * gcc.target/arm/neon/vuzpu8.c: Remove.
+       * gcc.target/arm/neon/vzipQf32.c: Remove.
+       * gcc.target/arm/neon/vzipQp16.c: Remove.
+       * gcc.target/arm/neon/vzipQp8.c: Remove.
+       * gcc.target/arm/neon/vzipQs16.c: Remove.
+       * gcc.target/arm/neon/vzipQs32.c: Remove.
+       * gcc.target/arm/neon/vzipQs8.c: Remove.
+       * gcc.target/arm/neon/vzipQu16.c: Remove.
+       * gcc.target/arm/neon/vzipQu32.c: Remove.
+       * gcc.target/arm/neon/vzipQu8.c: Remove.
+       * gcc.target/arm/neon/vzipf32.c: Remove.
+       * gcc.target/arm/neon/vzipp16.c: Remove.
+       * gcc.target/arm/neon/vzipp8.c: Remove.
+       * gcc.target/arm/neon/vzips16.c: Remove.
+       * gcc.target/arm/neon/vzips32.c: Remove.
+       * gcc.target/arm/neon/vzips8.c: Remove.
+       * gcc.target/arm/neon/vzipu16.c: Remove.
+       * gcc.target/arm/neon/vzipu32.c: Remove.
+       * gcc.target/arm/neon/vzipu8.c: Remove.
+
 2015-11-13  Ilya Enkovich  <enkovich.gnu@gmail.com>
 
        * g++.dg/vect/simd-mask-store-bool.cc: New test.

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
new file mode 100644 (file)
index 0000000..d2424d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
new file mode 100644 (file)
index 0000000..a787bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
new file mode 100644 (file)
index 0000000..dde572c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
new file mode 100644 (file)
index 0000000..74098a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
new file mode 100644 (file)
index 0000000..4795f44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
new file mode 100644 (file)
index 0000000..d3a7e0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
new file mode 100644 (file)
index 0000000..d8da627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
new file mode 100644 (file)
index 0000000..6281ade
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
new file mode 100644 (file)
index 0000000..a558ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
new file mode 100644 (file)
index 0000000..06822c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
new file mode 100644 (file)
index 0000000..713e70a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
new file mode 100644 (file)
index 0000000..64a912f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
new file mode 100644 (file)
index 0000000..8eb5504
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
new file mode 100644 (file)
index 0000000..a1acebd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
new file mode 100644 (file)
index 0000000..df7f58c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
new file mode 100644 (file)
index 0000000..215eb15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
new file mode 100644 (file)
index 0000000..2d8d5fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
new file mode 100644 (file)
index 0000000..362a546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
new file mode 100644 (file)
index 0000000..74bd3aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
new file mode 100644 (file)
index 0000000..a6a9e4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
new file mode 100644 (file)
index 0000000..8201a04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
new file mode 100644 (file)
index 0000000..28d281f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
new file mode 100644 (file)
index 0000000..66d2788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
new file mode 100644 (file)
index 0000000..4185fbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
new file mode 100644 (file)
index 0000000..fb0eddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
new file mode 100644 (file)
index 0000000..cee1b9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
new file mode 100644 (file)
index 0000000..ac7158a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
new file mode 100644 (file)
index 0000000..8da5918
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
new file mode 100644 (file)
index 0000000..2e732ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
new file mode 100644 (file)
index 0000000..f0c351d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
new file mode 100644 (file)
index 0000000..1a7751b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
new file mode 100644 (file)
index 0000000..198b13c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
new file mode 100644 (file)
index 0000000..3f67aaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
new file mode 100644 (file)
index 0000000..4399482
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
new file mode 100644 (file)
index 0000000..a89842b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
new file mode 100644 (file)
index 0000000..00ec911
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
new file mode 100644 (file)
index 0000000..0b1851e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
new file mode 100644 (file)
index 0000000..80084d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
new file mode 100644 (file)
index 0000000..a24ea19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
new file mode 100644 (file)
index 0000000..fa4e20d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
new file mode 100644 (file)
index 0000000..9e61a69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
new file mode 100644 (file)
index 0000000..3445c8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
new file mode 100644 (file)
index 0000000..5445d59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
new file mode 100644 (file)
index 0000000..8b3f60d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
new file mode 100644 (file)
index 0000000..1d3735a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
new file mode 100644 (file)
index 0000000..dc011d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
new file mode 100644 (file)
index 0000000..890c886
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
new file mode 100644 (file)
index 0000000..5994f6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
new file mode 100644 (file)
index 0000000..0304770
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
new file mode 100644 (file)
index 0000000..4df95c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
new file mode 100644 (file)
index 0000000..7f42303
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
new file mode 100644 (file)
index 0000000..6c0559f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
new file mode 100644 (file)
index 0000000..0f223c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
new file mode 100644 (file)
index 0000000..12ba625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
new file mode 100644 (file)
index 0000000..8b2014f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
new file mode 100644 (file)
index 0000000..f3bf756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
new file mode 100644 (file)
index 0000000..66e2ea0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
new file mode 100644 (file)
index 0000000..b6c3cb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
new file mode 100644 (file)
index 0000000..8d68b1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
new file mode 100644 (file)
index 0000000..413f49e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
new file mode 100644 (file)
index 0000000..d9e6680
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
new file mode 100644 (file)
index 0000000..56ae886
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
new file mode 100644 (file)
index 0000000..2ce4af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
new file mode 100644 (file)
index 0000000..53078a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
new file mode 100644 (file)
index 0000000..bc68117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
new file mode 100644 (file)
index 0000000..caeb45b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
new file mode 100644 (file)
index 0000000..b9ea8c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
new file mode 100644 (file)
index 0000000..f32ae16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
new file mode 100644 (file)
index 0000000..b6d2cce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
new file mode 100644 (file)
index 0000000..99c217b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
new file mode 100644 (file)
index 0000000..6eaa2ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
new file mode 100644 (file)
index 0000000..6ae17f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
new file mode 100644 (file)
index 0000000..b0a5cb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
new file mode 100644 (file)
index 0000000..31e01e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
new file mode 100644 (file)
index 0000000..e1c8c9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
new file mode 100644 (file)
index 0000000..58368f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
new file mode 100644 (file)
index 0000000..edb7b4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
new file mode 100644 (file)
index 0000000..2b1c77f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
new file mode 100644 (file)
index 0000000..f0c6971
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
new file mode 100644 (file)
index 0000000..cc68f6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
new file mode 100644 (file)
index 0000000..7b1bfeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
new file mode 100644 (file)
index 0000000..3b5ba07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
new file mode 100644 (file)
index 0000000..cf526e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
new file mode 100644 (file)
index 0000000..484fb7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc/testsuite/gcc.target/arm/neon/vabals16.c
new file mode 100644 (file)
index 0000000..6617e2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals16.c
@@ -0,0 +1,21 @@
+/* Test the `vabals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc/testsuite/gcc.target/arm/neon/vabals32.c
new file mode 100644 (file)
index 0000000..2110dee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals32.c
@@ -0,0 +1,21 @@
+/* Test the `vabals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc/testsuite/gcc.target/arm/neon/vabals8.c
new file mode 100644 (file)
index 0000000..c313a11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabals8.c
@@ -0,0 +1,21 @@
+/* Test the `vabals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
new file mode 100644 (file)
index 0000000..f43c8ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
new file mode 100644 (file)
index 0000000..12af072
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
new file mode 100644 (file)
index 0000000..05ba747
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc/testsuite/gcc.target/arm/neon/vabas16.c
new file mode 100644 (file)
index 0000000..9094ecb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas16.c
@@ -0,0 +1,21 @@
+/* Test the `vabas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc/testsuite/gcc.target/arm/neon/vabas32.c
new file mode 100644 (file)
index 0000000..184fc95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas32.c
@@ -0,0 +1,21 @@
+/* Test the `vabas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc/testsuite/gcc.target/arm/neon/vabas8.c
new file mode 100644 (file)
index 0000000..b9bc813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabas8.c
@@ -0,0 +1,21 @@
+/* Test the `vabas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc/testsuite/gcc.target/arm/neon/vabau16.c
new file mode 100644 (file)
index 0000000..d3b8c4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau16.c
@@ -0,0 +1,21 @@
+/* Test the `vabau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc/testsuite/gcc.target/arm/neon/vabau32.c
new file mode 100644 (file)
index 0000000..2c65f1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau32.c
@@ -0,0 +1,21 @@
+/* Test the `vabau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc/testsuite/gcc.target/arm/neon/vabau8.c
new file mode 100644 (file)
index 0000000..665410c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabau8.c
@@ -0,0 +1,21 @@
+/* Test the `vabau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
new file mode 100644 (file)
index 0000000..682736f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
new file mode 100644 (file)
index 0000000..37349e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
new file mode 100644 (file)
index 0000000..961b4ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
new file mode 100644 (file)
index 0000000..b6d6eaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
new file mode 100644 (file)
index 0000000..1c86be1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
new file mode 100644 (file)
index 0000000..a263b65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
new file mode 100644 (file)
index 0000000..d217f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
new file mode 100644 (file)
index 0000000..9454282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
new file mode 100644 (file)
index 0000000..63ac7e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
new file mode 100644 (file)
index 0000000..7d51343
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
new file mode 100644 (file)
index 0000000..0d9ac62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
new file mode 100644 (file)
index 0000000..6f19e67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
new file mode 100644 (file)
index 0000000..0ec3f93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
new file mode 100644 (file)
index 0000000..0d981fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc/testsuite/gcc.target/arm/neon/vabds16.c
new file mode 100644 (file)
index 0000000..a13ee88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds16.c
@@ -0,0 +1,20 @@
+/* Test the `vabds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc/testsuite/gcc.target/arm/neon/vabds32.c
new file mode 100644 (file)
index 0000000..fdbfdb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds32.c
@@ -0,0 +1,20 @@
+/* Test the `vabds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc/testsuite/gcc.target/arm/neon/vabds8.c
new file mode 100644 (file)
index 0000000..2b0fe0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabds8.c
@@ -0,0 +1,20 @@
+/* Test the `vabds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
new file mode 100644 (file)
index 0000000..ca599ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
new file mode 100644 (file)
index 0000000..cdd8342
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
new file mode 100644 (file)
index 0000000..1d93918
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
new file mode 100644 (file)
index 0000000..f77af2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
new file mode 100644 (file)
index 0000000..5b3a357
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
new file mode 100644 (file)
index 0000000..a0ad403
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
new file mode 100644 (file)
index 0000000..786d200
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
new file mode 100644 (file)
index 0000000..b1845da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc/testsuite/gcc.target/arm/neon/vabss16.c
new file mode 100644 (file)
index 0000000..ad37064
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc/testsuite/gcc.target/arm/neon/vabss32.c
new file mode 100644 (file)
index 0000000..3806698
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc/testsuite/gcc.target/arm/neon/vabss8.c
new file mode 100644 (file)
index 0000000..a36a2a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
new file mode 100644 (file)
index 0000000..dd2c06a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
new file mode 100644 (file)
index 0000000..ec000fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
new file mode 100644 (file)
index 0000000..34ead8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
new file mode 100644 (file)
index 0000000..77942de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
new file mode 100644 (file)
index 0000000..42bcdf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
new file mode 100644 (file)
index 0000000..983bb35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
new file mode 100644 (file)
index 0000000..c98772e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
new file mode 100644 (file)
index 0000000..95756c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
new file mode 100644 (file)
index 0000000..e52524e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
new file mode 100644 (file)
index 0000000..6afb8c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
new file mode 100644 (file)
index 0000000..f3f35e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
new file mode 100644 (file)
index 0000000..028f431
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
new file mode 100644 (file)
index 0000000..f139a6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
new file mode 100644 (file)
index 0000000..6c77062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
new file mode 100644 (file)
index 0000000..5315f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
new file mode 100644 (file)
index 0000000..6aa2560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
new file mode 100644 (file)
index 0000000..4b84ae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
new file mode 100644 (file)
index 0000000..3f267cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
new file mode 100644 (file)
index 0000000..c213610
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
new file mode 100644 (file)
index 0000000..6e5341c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
new file mode 100644 (file)
index 0000000..bc4359b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
new file mode 100644 (file)
index 0000000..9ec110e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc/testsuite/gcc.target/arm/neon/vadds16.c
new file mode 100644 (file)
index 0000000..1c2f70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc/testsuite/gcc.target/arm/neon/vadds32.c
new file mode 100644 (file)
index 0000000..8889228
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc/testsuite/gcc.target/arm/neon/vadds64.c
new file mode 100644 (file)
index 0000000..8b6bb5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds64.c
@@ -0,0 +1,19 @@
+/* Test the `vadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc/testsuite/gcc.target/arm/neon/vadds8.c
new file mode 100644 (file)
index 0000000..6165e62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
new file mode 100644 (file)
index 0000000..c346915
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
new file mode 100644 (file)
index 0000000..8436c12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
new file mode 100644 (file)
index 0000000..4cf9fcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
@@ -0,0 +1,19 @@
+/* Test the `vaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
new file mode 100644 (file)
index 0000000..8435a7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
new file mode 100644 (file)
index 0000000..8021483
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
new file mode 100644 (file)
index 0000000..5691af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
new file mode 100644 (file)
index 0000000..0a774c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
new file mode 100644 (file)
index 0000000..a7cfc65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
new file mode 100644 (file)
index 0000000..40f86f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
new file mode 100644 (file)
index 0000000..bb6d0fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
new file mode 100644 (file)
index 0000000..bfc9a21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
new file mode 100644 (file)
index 0000000..feeca56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
new file mode 100644 (file)
index 0000000..6c67c14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
new file mode 100644 (file)
index 0000000..7411c33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
new file mode 100644 (file)
index 0000000..710312d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
new file mode 100644 (file)
index 0000000..64a956d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
new file mode 100644 (file)
index 0000000..832d83c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
new file mode 100644 (file)
index 0000000..4820aa4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc/testsuite/gcc.target/arm/neon/vands16.c
new file mode 100644 (file)
index 0000000..0e17817
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands16.c
@@ -0,0 +1,20 @@
+/* Test the `vands16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc/testsuite/gcc.target/arm/neon/vands32.c
new file mode 100644 (file)
index 0000000..d56529e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands32.c
@@ -0,0 +1,20 @@
+/* Test the `vands32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc/testsuite/gcc.target/arm/neon/vands64.c
new file mode 100644 (file)
index 0000000..1641594
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands64.c
@@ -0,0 +1,19 @@
+/* Test the `vands64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc/testsuite/gcc.target/arm/neon/vands8.c
new file mode 100644 (file)
index 0000000..961e3d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vands8.c
@@ -0,0 +1,20 @@
+/* Test the `vands8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc/testsuite/gcc.target/arm/neon/vandu16.c
new file mode 100644 (file)
index 0000000..d60a0a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc/testsuite/gcc.target/arm/neon/vandu32.c
new file mode 100644 (file)
index 0000000..79f5773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc/testsuite/gcc.target/arm/neon/vandu64.c
new file mode 100644 (file)
index 0000000..40172e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu64.c
@@ -0,0 +1,19 @@
+/* Test the `vandu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc/testsuite/gcc.target/arm/neon/vandu8.c
new file mode 100644 (file)
index 0000000..1244eca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vandu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
new file mode 100644 (file)
index 0000000..ff66255
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int16x8_t out_int16x8_t;
+int16x8_t arg0_int16x8_t;
+int16x8_t arg1_int16x8_t;
+void test_vbicQs16 (void)
+{
+
+  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
new file mode 100644 (file)
index 0000000..4a691bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int32x4_t out_int32x4_t;
+int32x4_t arg0_int32x4_t;
+int32x4_t arg1_int32x4_t;
+void test_vbicQs32 (void)
+{
+
+  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
new file mode 100644 (file)
index 0000000..403098f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int64x2_t out_int64x2_t;
+int64x2_t arg0_int64x2_t;
+int64x2_t arg1_int64x2_t;
+void test_vbicQs64 (void)
+{
+
+  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
new file mode 100644 (file)
index 0000000..576769c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int8x16_t out_int8x16_t;
+int8x16_t arg0_int8x16_t;
+int8x16_t arg1_int8x16_t;
+void test_vbicQs8 (void)
+{
+
+  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
new file mode 100644 (file)
index 0000000..3504a26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint16x8_t out_uint16x8_t;
+uint16x8_t arg0_uint16x8_t;
+uint16x8_t arg1_uint16x8_t;
+void test_vbicQu16 (void)
+{
+
+  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
new file mode 100644 (file)
index 0000000..993280b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32x4_t out_uint32x4_t;
+uint32x4_t arg0_uint32x4_t;
+uint32x4_t arg1_uint32x4_t;
+void test_vbicQu32 (void)
+{
+
+  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
new file mode 100644 (file)
index 0000000..fb27c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint64x2_t out_uint64x2_t;
+uint64x2_t arg0_uint64x2_t;
+uint64x2_t arg1_uint64x2_t;
+void test_vbicQu64 (void)
+{
+
+  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
new file mode 100644 (file)
index 0000000..65f0e40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x16_t out_uint8x16_t;
+uint8x16_t arg0_uint8x16_t;
+uint8x16_t arg1_uint8x16_t;
+void test_vbicQu8 (void)
+{
+
+  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc/testsuite/gcc.target/arm/neon/vbics16.c
new file mode 100644 (file)
index 0000000..95aed5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics16.c
@@ -0,0 +1,20 @@
+/* Test the `vbics16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int16x4_t out_int16x4_t;
+int16x4_t arg0_int16x4_t;
+int16x4_t arg1_int16x4_t;
+void test_vbics16 (void)
+{
+
+  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc/testsuite/gcc.target/arm/neon/vbics32.c
new file mode 100644 (file)
index 0000000..925d748
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics32.c
@@ -0,0 +1,20 @@
+/* Test the `vbics32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int32x2_t out_int32x2_t;
+int32x2_t arg0_int32x2_t;
+int32x2_t arg1_int32x2_t;
+void test_vbics32 (void)
+{
+
+  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc/testsuite/gcc.target/arm/neon/vbics64.c
new file mode 100644 (file)
index 0000000..c7ab6cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics64.c
@@ -0,0 +1,19 @@
+/* Test the `vbics64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int64x1_t out_int64x1_t;
+int64x1_t arg0_int64x1_t;
+int64x1_t arg1_int64x1_t;
+void test_vbics64 (void)
+{
+
+  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc/testsuite/gcc.target/arm/neon/vbics8.c
new file mode 100644 (file)
index 0000000..22e2a12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbics8.c
@@ -0,0 +1,20 @@
+/* Test the `vbics8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int8x8_t out_int8x8_t;
+int8x8_t arg0_int8x8_t;
+int8x8_t arg1_int8x8_t;
+void test_vbics8 (void)
+{
+
+  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
new file mode 100644 (file)
index 0000000..cfa96c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint16x4_t out_uint16x4_t;
+uint16x4_t arg0_uint16x4_t;
+uint16x4_t arg1_uint16x4_t;
+void test_vbicu16 (void)
+{
+
+  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
new file mode 100644 (file)
index 0000000..65f49a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32x2_t out_uint32x2_t;
+uint32x2_t arg0_uint32x2_t;
+uint32x2_t arg1_uint32x2_t;
+void test_vbicu32 (void)
+{
+
+  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
new file mode 100644 (file)
index 0000000..89c8a5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
@@ -0,0 +1,19 @@
+/* Test the `vbicu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint64x1_t out_uint64x1_t;
+uint64x1_t arg0_uint64x1_t;
+uint64x1_t arg1_uint64x1_t;
+void test_vbicu64 (void)
+{
+
+  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
new file mode 100644 (file)
index 0000000..930eb36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x8_t out_uint8x8_t;
+uint8x8_t arg0_uint8x8_t;
+uint8x8_t arg1_uint8x8_t;
+void test_vbicu8 (void)
+{
+
+  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
new file mode 100644 (file)
index 0000000..6db03f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
new file mode 100644 (file)
index 0000000..0c0c88d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+  poly16x8_t arg2_poly16x8_t;
+
+  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
new file mode 100644 (file)
index 0000000..50d8180
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+  poly64x2_t arg2_poly64x2_t;
+
+  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
new file mode 100644 (file)
index 0000000..2d09700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+  poly8x16_t arg2_poly8x16_t;
+
+  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
new file mode 100644 (file)
index 0000000..2803194
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
new file mode 100644 (file)
index 0000000..637895d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
new file mode 100644 (file)
index 0000000..d329d19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+  int64x2_t arg2_int64x2_t;
+
+  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
new file mode 100644 (file)
index 0000000..5e78bbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
new file mode 100644 (file)
index 0000000..2446349
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
new file mode 100644 (file)
index 0000000..a8c32a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
new file mode 100644 (file)
index 0000000..fd00ae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+  uint64x2_t arg2_uint64x2_t;
+
+  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
new file mode 100644 (file)
index 0000000..1235843
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
new file mode 100644 (file)
index 0000000..345f1c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
new file mode 100644 (file)
index 0000000..6ce42b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+  poly16x4_t arg2_poly16x4_t;
+
+  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
new file mode 100644 (file)
index 0000000..0ff4cfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+  poly64x1_t arg2_poly64x1_t;
+
+  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
new file mode 100644 (file)
index 0000000..6e1f187
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  poly8x8_t arg2_poly8x8_t;
+
+  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
new file mode 100644 (file)
index 0000000..3368f99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
new file mode 100644 (file)
index 0000000..40bc0ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
new file mode 100644 (file)
index 0000000..8249a62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+  int64x1_t arg2_int64x1_t;
+
+  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
new file mode 100644 (file)
index 0000000..914a1d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
new file mode 100644 (file)
index 0000000..7106ffc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
new file mode 100644 (file)
index 0000000..f6922e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
new file mode 100644 (file)
index 0000000..724fdb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+  uint64x1_t arg2_uint64x1_t;
+
+  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
new file mode 100644 (file)
index 0000000..a27bc64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[       \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
new file mode 100644 (file)
index 0000000..48e8e79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcageQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcageQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
new file mode 100644 (file)
index 0000000..52084e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
new file mode 100644 (file)
index 0000000..e7290ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
new file mode 100644 (file)
index 0000000..ce8969b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
new file mode 100644 (file)
index 0000000..b429bba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
new file mode 100644 (file)
index 0000000..a834065
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcalef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcalef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
new file mode 100644 (file)
index 0000000..dbebe48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
new file mode 100644 (file)
index 0000000..004edc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
new file mode 100644 (file)
index 0000000..6a53721
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
new file mode 100644 (file)
index 0000000..556fbdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
new file mode 100644 (file)
index 0000000..cfbf64a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
new file mode 100644 (file)
index 0000000..1b75729
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
new file mode 100644 (file)
index 0000000..d6d6d30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
new file mode 100644 (file)
index 0000000..6f33d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
new file mode 100644 (file)
index 0000000..df2d47b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
new file mode 100644 (file)
index 0000000..80d56ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
new file mode 100644 (file)
index 0000000..046a505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
new file mode 100644 (file)
index 0000000..5758eba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
new file mode 100644 (file)
index 0000000..11337b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
new file mode 100644 (file)
index 0000000..506c980
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
new file mode 100644 (file)
index 0000000..c76e2b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
new file mode 100644 (file)
index 0000000..dda7ab7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
new file mode 100644 (file)
index 0000000..4ee8c5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
new file mode 100644 (file)
index 0000000..60134cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
new file mode 100644 (file)
index 0000000..93a5e3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
new file mode 100644 (file)
index 0000000..f60344f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
new file mode 100644 (file)
index 0000000..1d8cacc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
new file mode 100644 (file)
index 0000000..b5bb84e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
new file mode 100644 (file)
index 0000000..62f060f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
new file mode 100644 (file)
index 0000000..a86dfa2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
new file mode 100644 (file)
index 0000000..fbf678c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
new file mode 100644 (file)
index 0000000..f12259a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc/testsuite/gcc.target/arm/neon/vcges16.c
new file mode 100644 (file)
index 0000000..d420dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges16.c
@@ -0,0 +1,20 @@
+/* Test the `vcges16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc/testsuite/gcc.target/arm/neon/vcges32.c
new file mode 100644 (file)
index 0000000..c4e7315
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges32.c
@@ -0,0 +1,20 @@
+/* Test the `vcges32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc/testsuite/gcc.target/arm/neon/vcges8.c
new file mode 100644 (file)
index 0000000..0484e24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcges8.c
@@ -0,0 +1,20 @@
+/* Test the `vcges8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
new file mode 100644 (file)
index 0000000..89874e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
new file mode 100644 (file)
index 0000000..cb907fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
new file mode 100644 (file)
index 0000000..01af809
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
new file mode 100644 (file)
index 0000000..ab5f92d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
new file mode 100644 (file)
index 0000000..5e966f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
new file mode 100644 (file)
index 0000000..3db4176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
new file mode 100644 (file)
index 0000000..a092e21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
new file mode 100644 (file)
index 0000000..2239331
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
new file mode 100644 (file)
index 0000000..430f3ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
new file mode 100644 (file)
index 0000000..bb38a0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
new file mode 100644 (file)
index 0000000..1717807
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
new file mode 100644 (file)
index 0000000..0508883
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
new file mode 100644 (file)
index 0000000..09dc2b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
new file mode 100644 (file)
index 0000000..1cb6b02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
new file mode 100644 (file)
index 0000000..0c76d53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
new file mode 100644 (file)
index 0000000..ae6aae5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
new file mode 100644 (file)
index 0000000..3ed6bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
new file mode 100644 (file)
index 0000000..cc24025
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
new file mode 100644 (file)
index 0000000..e4efae9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
new file mode 100644 (file)
index 0000000..a432421
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
new file mode 100644 (file)
index 0000000..a6d2d77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
new file mode 100644 (file)
index 0000000..72dccdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
new file mode 100644 (file)
index 0000000..c057a4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
new file mode 100644 (file)
index 0000000..618232e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc/testsuite/gcc.target/arm/neon/vclef32.c
new file mode 100644 (file)
index 0000000..e4ef973
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclef32.c
@@ -0,0 +1,20 @@
+/* Test the `vclef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc/testsuite/gcc.target/arm/neon/vcles16.c
new file mode 100644 (file)
index 0000000..8b835b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles16.c
@@ -0,0 +1,20 @@
+/* Test the `vcles16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc/testsuite/gcc.target/arm/neon/vcles32.c
new file mode 100644 (file)
index 0000000..f5035d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles32.c
@@ -0,0 +1,20 @@
+/* Test the `vcles32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc/testsuite/gcc.target/arm/neon/vcles8.c
new file mode 100644 (file)
index 0000000..65b5962
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcles8.c
@@ -0,0 +1,20 @@
+/* Test the `vcles8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
new file mode 100644 (file)
index 0000000..a518241
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
new file mode 100644 (file)
index 0000000..f1d83e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
new file mode 100644 (file)
index 0000000..3a39454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
new file mode 100644 (file)
index 0000000..5c87852
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
new file mode 100644 (file)
index 0000000..c44d5a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
new file mode 100644 (file)
index 0000000..a4c7cfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc/testsuite/gcc.target/arm/neon/vclss16.c
new file mode 100644 (file)
index 0000000..5b43fae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss16.c
@@ -0,0 +1,19 @@
+/* Test the `vclss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc/testsuite/gcc.target/arm/neon/vclss32.c
new file mode 100644 (file)
index 0000000..e60c1c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss32.c
@@ -0,0 +1,19 @@
+/* Test the `vclss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc/testsuite/gcc.target/arm/neon/vclss8.c
new file mode 100644 (file)
index 0000000..272ef8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclss8.c
@@ -0,0 +1,19 @@
+/* Test the `vclss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
new file mode 100644 (file)
index 0000000..9523412
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
new file mode 100644 (file)
index 0000000..fc67ae1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
new file mode 100644 (file)
index 0000000..58da373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
new file mode 100644 (file)
index 0000000..800a502
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
new file mode 100644 (file)
index 0000000..b6435de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
new file mode 100644 (file)
index 0000000..43205b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
new file mode 100644 (file)
index 0000000..d65a825
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
new file mode 100644 (file)
index 0000000..f18e000
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc/testsuite/gcc.target/arm/neon/vclts16.c
new file mode 100644 (file)
index 0000000..115675e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts16.c
@@ -0,0 +1,20 @@
+/* Test the `vclts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc/testsuite/gcc.target/arm/neon/vclts32.c
new file mode 100644 (file)
index 0000000..99771d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts32.c
@@ -0,0 +1,20 @@
+/* Test the `vclts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc/testsuite/gcc.target/arm/neon/vclts8.c
new file mode 100644 (file)
index 0000000..372b4af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclts8.c
@@ -0,0 +1,20 @@
+/* Test the `vclts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
new file mode 100644 (file)
index 0000000..2a3012e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
new file mode 100644 (file)
index 0000000..51426a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
new file mode 100644 (file)
index 0000000..0606a32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
new file mode 100644 (file)
index 0000000..6652d3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
new file mode 100644 (file)
index 0000000..8eb1f6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
new file mode 100644 (file)
index 0000000..e1bc052
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
new file mode 100644 (file)
index 0000000..4f92e4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
new file mode 100644 (file)
index 0000000..67936cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
new file mode 100644 (file)
index 0000000..b889cb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
new file mode 100644 (file)
index 0000000..4c9cee3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
new file mode 100644 (file)
index 0000000..9827d90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
new file mode 100644 (file)
index 0000000..bb262c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
new file mode 100644 (file)
index 0000000..ee8dd30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
new file mode 100644 (file)
index 0000000..963248d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
new file mode 100644 (file)
index 0000000..a71042f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
new file mode 100644 (file)
index 0000000..5598f4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
new file mode 100644 (file)
index 0000000..5e0710e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
new file mode 100644 (file)
index 0000000..a654148
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
new file mode 100644 (file)
index 0000000..a75dfa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
new file mode 100644 (file)
index 0000000..348221e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
@@ -0,0 +1,19 @@
+/* Test the `vcnts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcnts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
new file mode 100644 (file)
index 0000000..cb4428d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
new file mode 100644 (file)
index 0000000..8c280bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
new file mode 100644 (file)
index 0000000..59a840f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
new file mode 100644 (file)
index 0000000..5d1aef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcombinep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
new file mode 100644 (file)
index 0000000..9784f58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
new file mode 100644 (file)
index 0000000..520c013
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
new file mode 100644 (file)
index 0000000..b2a49ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
new file mode 100644 (file)
index 0000000..292a892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
new file mode 100644 (file)
index 0000000..b3bf943
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
new file mode 100644 (file)
index 0000000..053944b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
new file mode 100644 (file)
index 0000000..18aa30c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
new file mode 100644 (file)
index 0000000..8e4881c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
new file mode 100644 (file)
index 0000000..9d4989c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
new file mode 100644 (file)
index 0000000..f921357
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
new file mode 100644 (file)
index 0000000..4e1363b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
new file mode 100644 (file)
index 0000000..0ad84d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcreatep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
new file mode 100644 (file)
index 0000000..79b70f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
new file mode 100644 (file)
index 0000000..c9f652e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
new file mode 100644 (file)
index 0000000..fd21c4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
new file mode 100644 (file)
index 0000000..d5e8187
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
new file mode 100644 (file)
index 0000000..79280e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
new file mode 100644 (file)
index 0000000..a36258d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
new file mode 100644 (file)
index 0000000..94d8252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
new file mode 100644 (file)
index 0000000..dc3e151
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
new file mode 100644 (file)
index 0000000..397fddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
new file mode 100644 (file)
index 0000000..4bb0b65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
new file mode 100644 (file)
index 0000000..6e24051
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
new file mode 100644 (file)
index 0000000..5f906ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_ns32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
new file mode 100644 (file)
index 0000000..29f2c5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
new file mode 100644 (file)
index 0000000..de3d1b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
new file mode 100644 (file)
index 0000000..64b462d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
new file mode 100644 (file)
index 0000000..97cb7e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
new file mode 100644 (file)
index 0000000..c7aa7a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
new file mode 100644 (file)
index 0000000..f86b4de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
new file mode 100644 (file)
index 0000000..fa3bf17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
new file mode 100644 (file)
index 0000000..de253e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_ns32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
new file mode 100644 (file)
index 0000000..23bdbdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
new file mode 100644 (file)
index 0000000..45b3a72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vcvtf16_f32 (void)
+{
+  float16x4_t out_float16x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f16.f32\[        \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
new file mode 100644 (file)
index 0000000..6bade54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_f16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_f16 (void)
+{
+  float32x4_t out_float32x4_t;
+  float16x4_t arg0_float16x4_t;
+
+  out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.f16\[        \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
new file mode 100644 (file)
index 0000000..2871523
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
new file mode 100644 (file)
index 0000000..1680271
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
new file mode 100644 (file)
index 0000000..f3b4912
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvts32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
new file mode 100644 (file)
index 0000000..c60cd06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
new file mode 100644 (file)
index 0000000..2b2c7f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
new file mode 100644 (file)
index 0000000..8b73edb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
new file mode 100644 (file)
index 0000000..8518168
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
new file mode 100644 (file)
index 0000000..6c03564
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
new file mode 100644 (file)
index 0000000..54c278c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
new file mode 100644 (file)
index 0000000..eb6b05b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
new file mode 100644 (file)
index 0000000..99551d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
new file mode 100644 (file)
index 0000000..5840142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
new file mode 100644 (file)
index 0000000..6bc5e3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
new file mode 100644 (file)
index 0000000..f8cdeb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
new file mode 100644 (file)
index 0000000..2f39703
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
new file mode 100644 (file)
index 0000000..e581efa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
new file mode 100644 (file)
index 0000000..c817c61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
new file mode 100644 (file)
index 0000000..57f8c2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
new file mode 100644 (file)
index 0000000..1f8527c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
new file mode 100644 (file)
index 0000000..4b67c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
new file mode 100644 (file)
index 0000000..2e30bc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
new file mode 100644 (file)
index 0000000..9b6a004
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
new file mode 100644 (file)
index 0000000..221c85f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
new file mode 100644 (file)
index 0000000..931300c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
new file mode 100644 (file)
index 0000000..f70a188
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
new file mode 100644 (file)
index 0000000..312efd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
new file mode 100644 (file)
index 0000000..0bf62cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
new file mode 100644 (file)
index 0000000..3493dcb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
new file mode 100644 (file)
index 0000000..3fd980a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
new file mode 100644 (file)
index 0000000..7f6d4aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
new file mode 100644 (file)
index 0000000..f0d46d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
new file mode 100644 (file)
index 0000000..a1396d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
new file mode 100644 (file)
index 0000000..deb0160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
new file mode 100644 (file)
index 0000000..e0b2d07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
new file mode 100644 (file)
index 0000000..9bec51a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
new file mode 100644 (file)
index 0000000..a442fd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
new file mode 100644 (file)
index 0000000..d9b5fd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
new file mode 100644 (file)
index 0000000..db14a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
new file mode 100644 (file)
index 0000000..6a65eb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
new file mode 100644 (file)
index 0000000..99fb193
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
new file mode 100644 (file)
index 0000000..448894b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
new file mode 100644 (file)
index 0000000..9b56707
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
new file mode 100644 (file)
index 0000000..25552dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
new file mode 100644 (file)
index 0000000..ad8a0a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
new file mode 100644 (file)
index 0000000..c3cc4d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
new file mode 100644 (file)
index 0000000..ddfeaec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
new file mode 100644 (file)
index 0000000..3056088
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
new file mode 100644 (file)
index 0000000..38017a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
new file mode 100644 (file)
index 0000000..6150b61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
new file mode 100644 (file)
index 0000000..404c8b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
new file mode 100644 (file)
index 0000000..c89072d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
new file mode 100644 (file)
index 0000000..09db0eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
new file mode 100644 (file)
index 0000000..b246900
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
new file mode 100644 (file)
index 0000000..d9cd2f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
new file mode 100644 (file)
index 0000000..926b1e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
new file mode 100644 (file)
index 0000000..272c6ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
new file mode 100644 (file)
index 0000000..dcd3921
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
new file mode 100644 (file)
index 0000000..9b34d9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
new file mode 100644 (file)
index 0000000..b98db78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
new file mode 100644 (file)
index 0000000..c985acd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc/testsuite/gcc.target/arm/neon/veors16.c
new file mode 100644 (file)
index 0000000..2b83903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors16.c
@@ -0,0 +1,20 @@
+/* Test the `veors16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc/testsuite/gcc.target/arm/neon/veors32.c
new file mode 100644 (file)
index 0000000..45403b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors32.c
@@ -0,0 +1,20 @@
+/* Test the `veors32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc/testsuite/gcc.target/arm/neon/veors64.c
new file mode 100644 (file)
index 0000000..b102c7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors64.c
@@ -0,0 +1,19 @@
+/* Test the `veors64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc/testsuite/gcc.target/arm/neon/veors8.c
new file mode 100644 (file)
index 0000000..0ae7a66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veors8.c
@@ -0,0 +1,20 @@
+/* Test the `veors8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc/testsuite/gcc.target/arm/neon/veoru16.c
new file mode 100644 (file)
index 0000000..f3b4192
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru16.c
@@ -0,0 +1,20 @@
+/* Test the `veoru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc/testsuite/gcc.target/arm/neon/veoru32.c
new file mode 100644 (file)
index 0000000..8b6be9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru32.c
@@ -0,0 +1,20 @@
+/* Test the `veoru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc/testsuite/gcc.target/arm/neon/veoru64.c
new file mode 100644 (file)
index 0000000..3b865fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru64.c
@@ -0,0 +1,19 @@
+/* Test the `veoru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc/testsuite/gcc.target/arm/neon/veoru8.c
new file mode 100644 (file)
index 0000000..3511a77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/veoru8.c
@@ -0,0 +1,20 @@
+/* Test the `veoru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
new file mode 100644 (file)
index 0000000..0b5239d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
new file mode 100644 (file)
index 0000000..f2e6879
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
new file mode 100644 (file)
index 0000000..2ae223a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
new file mode 100644 (file)
index 0000000..fbfde39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
new file mode 100644 (file)
index 0000000..2b0ae86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
new file mode 100644 (file)
index 0000000..cca2053
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
new file mode 100644 (file)
index 0000000..a489638
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
new file mode 100644 (file)
index 0000000..0e3b8a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
new file mode 100644 (file)
index 0000000..c21c482
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
new file mode 100644 (file)
index 0000000..a19950d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
new file mode 100644 (file)
index 0000000..d52e37f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
new file mode 100644 (file)
index 0000000..49e4de6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc/testsuite/gcc.target/arm/neon/vextf32.c
new file mode 100644 (file)
index 0000000..012dd48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc/testsuite/gcc.target/arm/neon/vextp16.c
new file mode 100644 (file)
index 0000000..94f601a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
new file mode 100644 (file)
index 0000000..abf5c0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp64.c
@@ -0,0 +1,20 @@
+/* Test the `vextp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc/testsuite/gcc.target/arm/neon/vextp8.c
new file mode 100644 (file)
index 0000000..58728cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc/testsuite/gcc.target/arm/neon/vexts16.c
new file mode 100644 (file)
index 0000000..032055e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts16.c
@@ -0,0 +1,20 @@
+/* Test the `vexts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc/testsuite/gcc.target/arm/neon/vexts32.c
new file mode 100644 (file)
index 0000000..a3c7dce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts32.c
@@ -0,0 +1,20 @@
+/* Test the `vexts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc/testsuite/gcc.target/arm/neon/vexts64.c
new file mode 100644 (file)
index 0000000..534c8b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts64.c
@@ -0,0 +1,20 @@
+/* Test the `vexts64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc/testsuite/gcc.target/arm/neon/vexts8.c
new file mode 100644 (file)
index 0000000..7c5dafd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vexts8.c
@@ -0,0 +1,20 @@
+/* Test the `vexts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc/testsuite/gcc.target/arm/neon/vextu16.c
new file mode 100644 (file)
index 0000000..2b8e44c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc/testsuite/gcc.target/arm/neon/vextu32.c
new file mode 100644 (file)
index 0000000..fad2ee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc/testsuite/gcc.target/arm/neon/vextu64.c
new file mode 100644 (file)
index 0000000..7313c26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc/testsuite/gcc.target/arm/neon/vextu8.c
new file mode 100644 (file)
index 0000000..caab02b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vextu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
new file mode 100644 (file)
index 0000000..30b4c99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vfmaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
new file mode 100644 (file)
index 0000000..8c55a0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
@@ -0,0 +1,21 @@
+/* Test the `vfmaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
new file mode 100644 (file)
index 0000000..37a0c64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vfmsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
new file mode 100644 (file)
index 0000000..d66e51c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vfmsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
new file mode 100644 (file)
index 0000000..2ff33ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
new file mode 100644 (file)
index 0000000..1245a3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
new file mode 100644 (file)
index 0000000..900b3b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
new file mode 100644 (file)
index 0000000..f2cbd8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
new file mode 100644 (file)
index 0000000..25c6a52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
new file mode 100644 (file)
index 0000000..ef815cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes64 (void)
+{
+  register int64_t out_int64_t asm ("r0");
+  int64x2_t arg0_int64x2_t;
+
+  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[     \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
new file mode 100644 (file)
index 0000000..c4a7659
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
new file mode 100644 (file)
index 0000000..cb10ca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
new file mode 100644 (file)
index 0000000..a6c4ca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
new file mode 100644 (file)
index 0000000..0f02e51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu64 (void)
+{
+  register uint64_t out_uint64_t asm ("r0");
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[     \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
new file mode 100644 (file)
index 0000000..0bc72e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
new file mode 100644 (file)
index 0000000..cc7382c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
new file mode 100644 (file)
index 0000000..6bb2a6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
new file mode 100644 (file)
index 0000000..c69abdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_highp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
new file mode 100644 (file)
index 0000000..75cfbd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
new file mode 100644 (file)
index 0000000..e655eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
new file mode 100644 (file)
index 0000000..c8c2661
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
new file mode 100644 (file)
index 0000000..f2d11c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
new file mode 100644 (file)
index 0000000..ecff213
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
new file mode 100644 (file)
index 0000000..1a7f002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
new file mode 100644 (file)
index 0000000..4899be4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
new file mode 100644 (file)
index 0000000..3ff2a2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
new file mode 100644 (file)
index 0000000..132ccca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
new file mode 100644 (file)
index 0000000..300e85c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
new file mode 100644 (file)
index 0000000..5d9f80b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
new file mode 100644 (file)
index 0000000..a172bd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
new file mode 100644 (file)
index 0000000..f8a9b02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
new file mode 100644 (file)
index 0000000..3cea0bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
new file mode 100644 (file)
index 0000000..f360fe3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
new file mode 100644 (file)
index 0000000..064c9cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
new file mode 100644 (file)
index 0000000..756b589
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[    \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
new file mode 100644 (file)
index 0000000..3f59e6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
new file mode 100644 (file)
index 0000000..75cef5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
new file mode 100644 (file)
index 0000000..bb461a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[     \]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
new file mode 100644 (file)
index 0000000..970ef76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowf32 (void)
+{
+  register float32x2_t out_float32x2_t asm ("d18");
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
new file mode 100644 (file)
index 0000000..ab42125
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp16 (void)
+{
+  register poly16x4_t out_poly16x4_t asm ("d18");
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
new file mode 100644 (file)
index 0000000..378310f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
new file mode 100644 (file)
index 0000000..462ce05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp8 (void)
+{
+  register poly8x8_t out_poly8x8_t asm ("d18");
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
new file mode 100644 (file)
index 0000000..3ee2cf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows16 (void)
+{
+  register int16x4_t out_int16x4_t asm ("d18");
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
new file mode 100644 (file)
index 0000000..27d8e72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows32 (void)
+{
+  register int32x2_t out_int32x2_t asm ("d18");
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
new file mode 100644 (file)
index 0000000..6b32548
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_lows64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
new file mode 100644 (file)
index 0000000..077ffd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows8 (void)
+{
+  register int8x8_t out_int8x8_t asm ("d18");
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
new file mode 100644 (file)
index 0000000..df93c32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu16 (void)
+{
+  register uint16x4_t out_uint16x4_t asm ("d18");
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
new file mode 100644 (file)
index 0000000..3fdd5b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu32 (void)
+{
+  register uint32x2_t out_uint32x2_t asm ("d18");
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
new file mode 100644 (file)
index 0000000..0732d7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
new file mode 100644 (file)
index 0000000..0f59277
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu8 (void)
+{
+  register uint8x8_t out_uint8x8_t asm ("d18");
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
new file mode 100644 (file)
index 0000000..bcd6a22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
new file mode 100644 (file)
index 0000000..1f8128a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
new file mode 100644 (file)
index 0000000..e7dd131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
new file mode 100644 (file)
index 0000000..f01237f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
new file mode 100644 (file)
index 0000000..65d2b8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
new file mode 100644 (file)
index 0000000..3fd5143
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
new file mode 100644 (file)
index 0000000..a36a6ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
new file mode 100644 (file)
index 0000000..20876ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
new file mode 100644 (file)
index 0000000..53fcd9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
new file mode 100644 (file)
index 0000000..3d18e9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
new file mode 100644 (file)
index 0000000..e0b64d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
new file mode 100644 (file)
index 0000000..9212d5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
new file mode 100644 (file)
index 0000000..71e9afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
new file mode 100644 (file)
index 0000000..f26f7ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
new file mode 100644 (file)
index 0000000..b2a5515
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
new file mode 100644 (file)
index 0000000..2d822cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
new file mode 100644 (file)
index 0000000..0ff6d4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
new file mode 100644 (file)
index 0000000..520d337
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
new file mode 100644 (file)
index 0000000..72c9816
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
new file mode 100644 (file)
index 0000000..0e6fdc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
new file mode 100644 (file)
index 0000000..7b3220b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
new file mode 100644 (file)
index 0000000..15beda2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
new file mode 100644 (file)
index 0000000..a4201ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
new file mode 100644 (file)
index 0000000..92dbeab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
new file mode 100644 (file)
index 0000000..58c33d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
new file mode 100644 (file)
index 0000000..66c72ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
new file mode 100644 (file)
index 0000000..8c5b28e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
new file mode 100644 (file)
index 0000000..90a3388
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
new file mode 100644 (file)
index 0000000..d4cfada
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
new file mode 100644 (file)
index 0000000..2d16b12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
new file mode 100644 (file)
index 0000000..41974a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
new file mode 100644 (file)
index 0000000..99475fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
new file mode 100644 (file)
index 0000000..5840189
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
new file mode 100644 (file)
index 0000000..31981ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
new file mode 100644 (file)
index 0000000..5cfa03a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
new file mode 100644 (file)
index 0000000..240ad56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
new file mode 100644 (file)
index 0000000..da17545
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
new file mode 100644 (file)
index 0000000..546e5e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
new file mode 100644 (file)
index 0000000..18a28f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
new file mode 100644 (file)
index 0000000..290a115
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
new file mode 100644 (file)
index 0000000..06c4b9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
new file mode 100644 (file)
index 0000000..58433ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
new file mode 100644 (file)
index 0000000..bfe0dd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
new file mode 100644 (file)
index 0000000..ee7026d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
new file mode 100644 (file)
index 0000000..0361b4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
new file mode 100644 (file)
index 0000000..6317455
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
new file mode 100644 (file)
index 0000000..918e0df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
new file mode 100644 (file)
index 0000000..e96ad29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
new file mode 100644 (file)
index 0000000..2a5fec1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
new file mode 100644 (file)
index 0000000..1b0deee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
new file mode 100644 (file)
index 0000000..cd43706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
new file mode 100644 (file)
index 0000000..24a186b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
new file mode 100644 (file)
index 0000000..b146b78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
new file mode 100644 (file)
index 0000000..d1d0386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
new file mode 100644 (file)
index 0000000..be53cf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
new file mode 100644 (file)
index 0000000..58b97a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
new file mode 100644 (file)
index 0000000..5c299f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
new file mode 100644 (file)
index 0000000..6b4d0b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
new file mode 100644 (file)
index 0000000..018bac7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
new file mode 100644 (file)
index 0000000..06726db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
new file mode 100644 (file)
index 0000000..699d77b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupf32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
new file mode 100644 (file)
index 0000000..baee8e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
new file mode 100644 (file)
index 0000000..fa40f84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
new file mode 100644 (file)
index 0000000..adde412
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
new file mode 100644 (file)
index 0000000..f7c3447
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
new file mode 100644 (file)
index 0000000..4039804
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
new file mode 100644 (file)
index 0000000..6784123
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
new file mode 100644 (file)
index 0000000..d6a3a8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
new file mode 100644 (file)
index 0000000..2cd76b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
new file mode 100644 (file)
index 0000000..85e5122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
new file mode 100644 (file)
index 0000000..7ccb05f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
new file mode 100644 (file)
index 0000000..8f6734a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
new file mode 100644 (file)
index 0000000..809866b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
new file mode 100644 (file)
index 0000000..5cc3b75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
new file mode 100644 (file)
index 0000000..874b5d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
new file mode 100644 (file)
index 0000000..3349ed0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
new file mode 100644 (file)
index 0000000..fbb4c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
new file mode 100644 (file)
index 0000000..c623f3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
new file mode 100644 (file)
index 0000000..a26cc2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
new file mode 100644 (file)
index 0000000..f5b3ae2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
new file mode 100644 (file)
index 0000000..cf97ef5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
new file mode 100644 (file)
index 0000000..e5f19ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
new file mode 100644 (file)
index 0000000..64e353e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
new file mode 100644 (file)
index 0000000..d938596
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
new file mode 100644 (file)
index 0000000..acca854
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1f32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
new file mode 100644 (file)
index 0000000..59b8dc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
new file mode 100644 (file)
index 0000000..8322dd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1p64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
new file mode 100644 (file)
index 0000000..96fda65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
new file mode 100644 (file)
index 0000000..d95113e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
new file mode 100644 (file)
index 0000000..6ed2a96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
new file mode 100644 (file)
index 0000000..03c6cf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
new file mode 100644 (file)
index 0000000..b3bdbba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
new file mode 100644 (file)
index 0000000..7ec9828
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
new file mode 100644 (file)
index 0000000..8039822
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
new file mode 100644 (file)
index 0000000..f4e4cc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
new file mode 100644 (file)
index 0000000..3133ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
new file mode 100644 (file)
index 0000000..0cccd0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanef32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
new file mode 100644 (file)
index 0000000..2187a7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanep16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
new file mode 100644 (file)
index 0000000..1872088
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
new file mode 100644 (file)
index 0000000..953b518
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
new file mode 100644 (file)
index 0000000..6f0f45f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
new file mode 100644 (file)
index 0000000..3f65654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
new file mode 100644 (file)
index 0000000..a112ea2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
new file mode 100644 (file)
index 0000000..bb75b7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
new file mode 100644 (file)
index 0000000..5f4307d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+
+  out_poly8x16x2_t = vld2q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
new file mode 100644 (file)
index 0000000..2b53903
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
new file mode 100644 (file)
index 0000000..53bc98b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
new file mode 100644 (file)
index 0000000..d056fb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+
+  out_int8x16x2_t = vld2q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
new file mode 100644 (file)
index 0000000..1a69ee5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
new file mode 100644 (file)
index 0000000..45fe749
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
new file mode 100644 (file)
index 0000000..99c935f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+
+  out_uint8x16x2_t = vld2q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
new file mode 100644 (file)
index 0000000..e33dad9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
new file mode 100644 (file)
index 0000000..2b9cf43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
new file mode 100644 (file)
index 0000000..acebb9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
new file mode 100644 (file)
index 0000000..00cfd9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
new file mode 100644 (file)
index 0000000..9db5388
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
new file mode 100644 (file)
index 0000000..80f186d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
new file mode 100644 (file)
index 0000000..d6b06ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
new file mode 100644 (file)
index 0000000..5062928
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
new file mode 100644 (file)
index 0000000..9380195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
new file mode 100644 (file)
index 0000000..d469691
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
new file mode 100644 (file)
index 0000000..bb92ec7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
new file mode 100644 (file)
index 0000000..72dc31b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
new file mode 100644 (file)
index 0000000..7379d3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanef32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
new file mode 100644 (file)
index 0000000..186a1c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
new file mode 100644 (file)
index 0000000..3a8201d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
new file mode 100644 (file)
index 0000000..0881359
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
new file mode 100644 (file)
index 0000000..8ad919c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
new file mode 100644 (file)
index 0000000..d4a6307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
new file mode 100644 (file)
index 0000000..f0c7fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
new file mode 100644 (file)
index 0000000..f61fb51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
new file mode 100644 (file)
index 0000000..8def913
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
new file mode 100644 (file)
index 0000000..db3ff7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2f32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
new file mode 100644 (file)
index 0000000..7181dbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2p16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
new file mode 100644 (file)
index 0000000..e92c414
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2p64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
new file mode 100644 (file)
index 0000000..9e97b59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2p8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
new file mode 100644 (file)
index 0000000..268b62b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
new file mode 100644 (file)
index 0000000..c65d931
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
new file mode 100644 (file)
index 0000000..136df05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
new file mode 100644 (file)
index 0000000..c812b19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
new file mode 100644 (file)
index 0000000..a089a6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
new file mode 100644 (file)
index 0000000..5d5875e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
new file mode 100644 (file)
index 0000000..6124db8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
new file mode 100644 (file)
index 0000000..fb62755
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
new file mode 100644 (file)
index 0000000..0b36c4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanef32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
new file mode 100644 (file)
index 0000000..88123f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanep16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
new file mode 100644 (file)
index 0000000..3349522
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
new file mode 100644 (file)
index 0000000..a669441
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
new file mode 100644 (file)
index 0000000..68cb436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
new file mode 100644 (file)
index 0000000..0392513
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
new file mode 100644 (file)
index 0000000..c45e1b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qf32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
new file mode 100644 (file)
index 0000000..9658954
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
new file mode 100644 (file)
index 0000000..bb54693
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp8 (void)
+{
+  poly8x16x3_t out_poly8x16x3_t;
+
+  out_poly8x16x3_t = vld3q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
new file mode 100644 (file)
index 0000000..8864f68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
new file mode 100644 (file)
index 0000000..d33e882
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
new file mode 100644 (file)
index 0000000..1df9c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs8 (void)
+{
+  int8x16x3_t out_int8x16x3_t;
+
+  out_int8x16x3_t = vld3q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
new file mode 100644 (file)
index 0000000..c6422ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
new file mode 100644 (file)
index 0000000..0632ef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
new file mode 100644 (file)
index 0000000..d41c469
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu8 (void)
+{
+  uint8x16x3_t out_uint8x16x3_t;
+
+  out_uint8x16x3_t = vld3q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
new file mode 100644 (file)
index 0000000..0f0c420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupf32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
new file mode 100644 (file)
index 0000000..9d794da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
new file mode 100644 (file)
index 0000000..ab34f1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
new file mode 100644 (file)
index 0000000..0132d40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
new file mode 100644 (file)
index 0000000..c5ba768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
new file mode 100644 (file)
index 0000000..6d069b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
new file mode 100644 (file)
index 0000000..31267b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
new file mode 100644 (file)
index 0000000..c6c0935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
new file mode 100644 (file)
index 0000000..ed49e0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
new file mode 100644 (file)
index 0000000..04eb017
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
new file mode 100644 (file)
index 0000000..7bb5b62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
new file mode 100644 (file)
index 0000000..f315786
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
new file mode 100644 (file)
index 0000000..4d78353
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanef32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
new file mode 100644 (file)
index 0000000..6a3b87a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
new file mode 100644 (file)
index 0000000..41ac97d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
new file mode 100644 (file)
index 0000000..f74ffce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
new file mode 100644 (file)
index 0000000..bc41477
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
new file mode 100644 (file)
index 0000000..995db24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
new file mode 100644 (file)
index 0000000..63d22ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
new file mode 100644 (file)
index 0000000..486db6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
new file mode 100644 (file)
index 0000000..b5ea2fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
new file mode 100644 (file)
index 0000000..79e1a4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3f32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
new file mode 100644 (file)
index 0000000..5e053a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3p16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
new file mode 100644 (file)
index 0000000..8fbc95e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3p64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
new file mode 100644 (file)
index 0000000..f15b968
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3p8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
new file mode 100644 (file)
index 0000000..ed5e24d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
new file mode 100644 (file)
index 0000000..6ad2b9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
new file mode 100644 (file)
index 0000000..14f8aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
new file mode 100644 (file)
index 0000000..2192499
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
new file mode 100644 (file)
index 0000000..5fd1a01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
new file mode 100644 (file)
index 0000000..4ae8217
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
new file mode 100644 (file)
index 0000000..c6d7626
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
new file mode 100644 (file)
index 0000000..e336339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
new file mode 100644 (file)
index 0000000..dfac627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanef32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
new file mode 100644 (file)
index 0000000..6ed339d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanep16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
new file mode 100644 (file)
index 0000000..3683e7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
new file mode 100644 (file)
index 0000000..1d25eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
new file mode 100644 (file)
index 0000000..75848c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
new file mode 100644 (file)
index 0000000..9201bdc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
new file mode 100644 (file)
index 0000000..199c4bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qf32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
new file mode 100644 (file)
index 0000000..f6638a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
new file mode 100644 (file)
index 0000000..a9a8c52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp8 (void)
+{
+  poly8x16x4_t out_poly8x16x4_t;
+
+  out_poly8x16x4_t = vld4q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
new file mode 100644 (file)
index 0000000..6f7e84d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
new file mode 100644 (file)
index 0000000..e71d6fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
new file mode 100644 (file)
index 0000000..30d4dea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs8 (void)
+{
+  int8x16x4_t out_int8x16x4_t;
+
+  out_int8x16x4_t = vld4q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
new file mode 100644 (file)
index 0000000..9d737ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
new file mode 100644 (file)
index 0000000..7d46e2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
new file mode 100644 (file)
index 0000000..4484cda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu8 (void)
+{
+  uint8x16x4_t out_uint8x16x4_t;
+
+  out_uint8x16x4_t = vld4q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
new file mode 100644 (file)
index 0000000..e59fb12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupf32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
new file mode 100644 (file)
index 0000000..4426298
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
new file mode 100644 (file)
index 0000000..da06911
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
new file mode 100644 (file)
index 0000000..936c91e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
new file mode 100644 (file)
index 0000000..f7a35e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
new file mode 100644 (file)
index 0000000..7ead80c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
new file mode 100644 (file)
index 0000000..4420628
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
new file mode 100644 (file)
index 0000000..03f3d88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
new file mode 100644 (file)
index 0000000..3d08493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
new file mode 100644 (file)
index 0000000..0f61908
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
new file mode 100644 (file)
index 0000000..c2f00ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
new file mode 100644 (file)
index 0000000..ee4c674
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
new file mode 100644 (file)
index 0000000..3f293d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanef32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
new file mode 100644 (file)
index 0000000..94d24af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
new file mode 100644 (file)
index 0000000..1bcb3e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
new file mode 100644 (file)
index 0000000..fbaeadb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
new file mode 100644 (file)
index 0000000..7f9cc0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
new file mode 100644 (file)
index 0000000..637361c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
new file mode 100644 (file)
index 0000000..a0d98a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
new file mode 100644 (file)
index 0000000..a691398
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
new file mode 100644 (file)
index 0000000..48a60b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
new file mode 100644 (file)
index 0000000..c3de78f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4f32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
new file mode 100644 (file)
index 0000000..8909bd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4p16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
new file mode 100644 (file)
index 0000000..eda3bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4p64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
new file mode 100644 (file)
index 0000000..c77b223
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4p8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
new file mode 100644 (file)
index 0000000..052a843
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
new file mode 100644 (file)
index 0000000..ce9bbaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
new file mode 100644 (file)
index 0000000..537ece0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
new file mode 100644 (file)
index 0000000..c7c33e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
new file mode 100644 (file)
index 0000000..bb602fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
new file mode 100644 (file)
index 0000000..680d1f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
new file mode 100644 (file)
index 0000000..304aff0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
new file mode 100644 (file)
index 0000000..8972de1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
new file mode 100644 (file)
index 0000000..c39fef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
new file mode 100644 (file)
index 0000000..57359f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
new file mode 100644 (file)
index 0000000..bf2853f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
new file mode 100644 (file)
index 0000000..f25da01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
new file mode 100644 (file)
index 0000000..58707fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
new file mode 100644 (file)
index 0000000..3b9a02e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
new file mode 100644 (file)
index 0000000..1543c94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
new file mode 100644 (file)
index 0000000..c9edda1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
new file mode 100644 (file)
index 0000000..cb262e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
new file mode 100644 (file)
index 0000000..0078e3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
new file mode 100644 (file)
index 0000000..b60efd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
new file mode 100644 (file)
index 0000000..0c31be4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
new file mode 100644 (file)
index 0000000..6ed09a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
new file mode 100644 (file)
index 0000000..4041d87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
new file mode 100644 (file)
index 0000000..a813893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
new file mode 100644 (file)
index 0000000..56b3dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
new file mode 100644 (file)
index 0000000..6a4b9ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
new file mode 100644 (file)
index 0000000..aa4269c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
new file mode 100644 (file)
index 0000000..81c4578
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
new file mode 100644 (file)
index 0000000..7bd31af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
new file mode 100644 (file)
index 0000000..aeb5d44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc/testsuite/gcc.target/arm/neon/vminf32.c
new file mode 100644 (file)
index 0000000..ded40aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc/testsuite/gcc.target/arm/neon/vmins16.c
new file mode 100644 (file)
index 0000000..0cc8401
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc/testsuite/gcc.target/arm/neon/vmins32.c
new file mode 100644 (file)
index 0000000..c8f86af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc/testsuite/gcc.target/arm/neon/vmins8.c
new file mode 100644 (file)
index 0000000..6ed9d82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc/testsuite/gcc.target/arm/neon/vminu16.c
new file mode 100644 (file)
index 0000000..f971658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc/testsuite/gcc.target/arm/neon/vminu32.c
new file mode 100644 (file)
index 0000000..a1c8455
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc/testsuite/gcc.target/arm/neon/vminu8.c
new file mode 100644 (file)
index 0000000..b810e86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
new file mode 100644 (file)
index 0000000..ba2b0eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
new file mode 100644 (file)
index 0000000..81b14d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
new file mode 100644 (file)
index 0000000..f1373c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
new file mode 100644 (file)
index 0000000..b8ec20a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
new file mode 100644 (file)
index 0000000..03f9465
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
new file mode 100644 (file)
index 0000000..0fa53da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
new file mode 100644 (file)
index 0000000..da3ae94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
new file mode 100644 (file)
index 0000000..1f206f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
new file mode 100644 (file)
index 0000000..4f8da83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
new file mode 100644 (file)
index 0000000..0af4c20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
new file mode 100644 (file)
index 0000000..2c4a6e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
new file mode 100644 (file)
index 0000000..b28d1ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
new file mode 100644 (file)
index 0000000..9c02573
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
new file mode 100644 (file)
index 0000000..6a2deca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
new file mode 100644 (file)
index 0000000..7f795f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
new file mode 100644 (file)
index 0000000..e976526
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
new file mode 100644 (file)
index 0000000..ebfcd7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
new file mode 100644 (file)
index 0000000..a58bb70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
new file mode 100644 (file)
index 0000000..0a98e64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
new file mode 100644 (file)
index 0000000..7ce690c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
new file mode 100644 (file)
index 0000000..c44e70f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
new file mode 100644 (file)
index 0000000..20f637f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
new file mode 100644 (file)
index 0000000..7c88491
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
new file mode 100644 (file)
index 0000000..1e6681e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
new file mode 100644 (file)
index 0000000..fe44375
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
new file mode 100644 (file)
index 0000000..c39c7b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
new file mode 100644 (file)
index 0000000..b87366f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
new file mode 100644 (file)
index 0000000..827d4db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
new file mode 100644 (file)
index 0000000..f4bbe55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
new file mode 100644 (file)
index 0000000..24b581c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
new file mode 100644 (file)
index 0000000..ea828b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
new file mode 100644 (file)
index 0000000..4641f9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
new file mode 100644 (file)
index 0000000..96f1429
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
new file mode 100644 (file)
index 0000000..24f1016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
new file mode 100644 (file)
index 0000000..54bbdea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
new file mode 100644 (file)
index 0000000..02909bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
new file mode 100644 (file)
index 0000000..777078d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
new file mode 100644 (file)
index 0000000..65d964e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
new file mode 100644 (file)
index 0000000..806a449
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
new file mode 100644 (file)
index 0000000..a7cb797
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
new file mode 100644 (file)
index 0000000..bb71b9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
new file mode 100644 (file)
index 0000000..0a191d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
new file mode 100644 (file)
index 0000000..e36c5be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
new file mode 100644 (file)
index 0000000..c2d1fe6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
new file mode 100644 (file)
index 0000000..9ec2001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
new file mode 100644 (file)
index 0000000..7f4bd11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
new file mode 100644 (file)
index 0000000..12e524f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
new file mode 100644 (file)
index 0000000..f55e11b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
new file mode 100644 (file)
index 0000000..24a20cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
new file mode 100644 (file)
index 0000000..feb4178
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
new file mode 100644 (file)
index 0000000..eb15872
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
new file mode 100644 (file)
index 0000000..8a432ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
new file mode 100644 (file)
index 0000000..2aa122f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
new file mode 100644 (file)
index 0000000..4124463
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
new file mode 100644 (file)
index 0000000..0c76e04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
new file mode 100644 (file)
index 0000000..62d13ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
new file mode 100644 (file)
index 0000000..cf31a92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
new file mode 100644 (file)
index 0000000..9788edc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
new file mode 100644 (file)
index 0000000..db405ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
new file mode 100644 (file)
index 0000000..5830224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
new file mode 100644 (file)
index 0000000..a331c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
new file mode 100644 (file)
index 0000000..ab6844f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
new file mode 100644 (file)
index 0000000..f7c160e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
new file mode 100644 (file)
index 0000000..37b0bc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
new file mode 100644 (file)
index 0000000..ea4b5fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
new file mode 100644 (file)
index 0000000..9b1d38a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
new file mode 100644 (file)
index 0000000..312d6ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
new file mode 100644 (file)
index 0000000..21645d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
new file mode 100644 (file)
index 0000000..8f78c0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
new file mode 100644 (file)
index 0000000..c947edd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
new file mode 100644 (file)
index 0000000..b99b497
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
new file mode 100644 (file)
index 0000000..97dda12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
new file mode 100644 (file)
index 0000000..d0cd7f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
new file mode 100644 (file)
index 0000000..bee00e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
new file mode 100644 (file)
index 0000000..94d6c04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
new file mode 100644 (file)
index 0000000..4965231
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
new file mode 100644 (file)
index 0000000..fb065e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
new file mode 100644 (file)
index 0000000..e89cd11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
new file mode 100644 (file)
index 0000000..c22f00b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
new file mode 100644 (file)
index 0000000..1bb52ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
new file mode 100644 (file)
index 0000000..65644f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
new file mode 100644 (file)
index 0000000..4268862
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
new file mode 100644 (file)
index 0000000..841ab44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
new file mode 100644 (file)
index 0000000..2595b71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
new file mode 100644 (file)
index 0000000..cec5695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
new file mode 100644 (file)
index 0000000..f5fe87a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
new file mode 100644 (file)
index 0000000..39754df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
new file mode 100644 (file)
index 0000000..e5bebde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
new file mode 100644 (file)
index 0000000..90f342d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
new file mode 100644 (file)
index 0000000..08a8e17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
new file mode 100644 (file)
index 0000000..f2e3c3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
new file mode 100644 (file)
index 0000000..49f0a4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
new file mode 100644 (file)
index 0000000..049d046
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
new file mode 100644 (file)
index 0000000..e8ff816
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
new file mode 100644 (file)
index 0000000..31b24b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
new file mode 100644 (file)
index 0000000..2221aa2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
new file mode 100644 (file)
index 0000000..bc72ec4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
new file mode 100644 (file)
index 0000000..13566e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
new file mode 100644 (file)
index 0000000..eacd0ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
new file mode 100644 (file)
index 0000000..2a21439
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
new file mode 100644 (file)
index 0000000..ede6b15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
new file mode 100644 (file)
index 0000000..8cfd2d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
@@ -0,0 +1,18 @@
+/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
new file mode 100644 (file)
index 0000000..1fb2af8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
new file mode 100644 (file)
index 0000000..0e33945
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
new file mode 100644 (file)
index 0000000..fe7bef1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
new file mode 100644 (file)
index 0000000..6092b32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
@@ -0,0 +1,18 @@
+/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
new file mode 100644 (file)
index 0000000..ce2f299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
new file mode 100644 (file)
index 0000000..3b3368c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
new file mode 100644 (file)
index 0000000..1a3ae25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
new file mode 100644 (file)
index 0000000..8d4347b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
new file mode 100644 (file)
index 0000000..b0e1b09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
new file mode 100644 (file)
index 0000000..cb1ae87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
new file mode 100644 (file)
index 0000000..2a11d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
@@ -0,0 +1,18 @@
+/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
new file mode 100644 (file)
index 0000000..c825eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
new file mode 100644 (file)
index 0000000..f17f837
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
new file mode 100644 (file)
index 0000000..80f948f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[     \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
new file mode 100644 (file)
index 0000000..d9b9e60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
@@ -0,0 +1,18 @@
+/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
new file mode 100644 (file)
index 0000000..d3e3780
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[      \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[        \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
new file mode 100644 (file)
index 0000000..a9de06b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
new file mode 100644 (file)
index 0000000..cf9572e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
new file mode 100644 (file)
index 0000000..156a81d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
new file mode 100644 (file)
index 0000000..d19e416
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
new file mode 100644 (file)
index 0000000..decb3a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
new file mode 100644 (file)
index 0000000..7623ad6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
new file mode 100644 (file)
index 0000000..91a30d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
new file mode 100644 (file)
index 0000000..66c5f87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
new file mode 100644 (file)
index 0000000..03e10ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
new file mode 100644 (file)
index 0000000..c391e88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
new file mode 100644 (file)
index 0000000..f0105da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
new file mode 100644 (file)
index 0000000..9809fec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
new file mode 100644 (file)
index 0000000..1cc15bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
new file mode 100644 (file)
index 0000000..a78b272
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
new file mode 100644 (file)
index 0000000..7b953cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
new file mode 100644 (file)
index 0000000..4b9a050
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
new file mode 100644 (file)
index 0000000..f1ff8d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
new file mode 100644 (file)
index 0000000..f55bb7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32_t arg1_float32_t;
+
+  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
new file mode 100644 (file)
index 0000000..e98e23c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
new file mode 100644 (file)
index 0000000..0c5d582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
new file mode 100644 (file)
index 0000000..3ee2fee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
new file mode 100644 (file)
index 0000000..fb60d59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
new file mode 100644 (file)
index 0000000..f23e081
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
new file mode 100644 (file)
index 0000000..104f296
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
new file mode 100644 (file)
index 0000000..9c8c42f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
new file mode 100644 (file)
index 0000000..c775f2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
new file mode 100644 (file)
index 0000000..bc9ff89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
new file mode 100644 (file)
index 0000000..02df722
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
new file mode 100644 (file)
index 0000000..003fcf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
new file mode 100644 (file)
index 0000000..cf6f980
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
new file mode 100644 (file)
index 0000000..8270c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
new file mode 100644 (file)
index 0000000..676bd96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
new file mode 100644 (file)
index 0000000..dd16c21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
new file mode 100644 (file)
index 0000000..79a1c75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
new file mode 100644 (file)
index 0000000..cd27886
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
new file mode 100644 (file)
index 0000000..bd60e74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32_t arg1_float32_t;
+
+  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
new file mode 100644 (file)
index 0000000..eb0c768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
new file mode 100644 (file)
index 0000000..ba74d4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
new file mode 100644 (file)
index 0000000..4048ff5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
new file mode 100644 (file)
index 0000000..58f7e95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
new file mode 100644 (file)
index 0000000..14a7ad4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
new file mode 100644 (file)
index 0000000..8a58638
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
new file mode 100644 (file)
index 0000000..6f19bd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
new file mode 100644 (file)
index 0000000..97a723b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
new file mode 100644 (file)
index 0000000..c70fdd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
new file mode 100644 (file)
index 0000000..7ee4335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
new file mode 100644 (file)
index 0000000..7a7673c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
new file mode 100644 (file)
index 0000000..8e4f3f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
new file mode 100644 (file)
index 0000000..1af7c55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
new file mode 100644 (file)
index 0000000..7d16061
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullp8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.p8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
new file mode 100644 (file)
index 0000000..dcbcf26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
new file mode 100644 (file)
index 0000000..7b00149
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
new file mode 100644 (file)
index 0000000..926549c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
new file mode 100644 (file)
index 0000000..0867792
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
new file mode 100644 (file)
index 0000000..e2ff112
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
new file mode 100644 (file)
index 0000000..1e893ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
new file mode 100644 (file)
index 0000000..3b7505a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
new file mode 100644 (file)
index 0000000..9eea7a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
new file mode 100644 (file)
index 0000000..fd53ac7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
new file mode 100644 (file)
index 0000000..4359a20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
new file mode 100644 (file)
index 0000000..be19227
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
new file mode 100644 (file)
index 0000000..476b9ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
new file mode 100644 (file)
index 0000000..0252b8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
new file mode 100644 (file)
index 0000000..1166597
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
new file mode 100644 (file)
index 0000000..d8f5e1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
new file mode 100644 (file)
index 0000000..f737af5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
new file mode 100644 (file)
index 0000000..126c74d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
new file mode 100644 (file)
index 0000000..a0cc6be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
new file mode 100644 (file)
index 0000000..0c2881b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
new file mode 100644 (file)
index 0000000..d973064
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
new file mode 100644 (file)
index 0000000..a113996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
new file mode 100644 (file)
index 0000000..c9399c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
new file mode 100644 (file)
index 0000000..fe3e522
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
new file mode 100644 (file)
index 0000000..3c394a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
new file mode 100644 (file)
index 0000000..5b71863
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
new file mode 100644 (file)
index 0000000..58413f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
new file mode 100644 (file)
index 0000000..44b2e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
new file mode 100644 (file)
index 0000000..66e6729
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
new file mode 100644 (file)
index 0000000..cddcab6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
new file mode 100644 (file)
index 0000000..439bf1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
new file mode 100644 (file)
index 0000000..95db560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
new file mode 100644 (file)
index 0000000..f2423dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
new file mode 100644 (file)
index 0000000..4c9bec2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
new file mode 100644 (file)
index 0000000..91f311a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
new file mode 100644 (file)
index 0000000..45a7a9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
new file mode 100644 (file)
index 0000000..aad2966
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int16x8_t out_int16x8_t;
+int16x8_t arg0_int16x8_t;
+int16x8_t arg1_int16x8_t;
+void test_vornQs16 (void)
+{
+
+  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
new file mode 100644 (file)
index 0000000..61e22a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int32x4_t out_int32x4_t;
+int32x4_t arg0_int32x4_t;
+int32x4_t arg1_int32x4_t;
+void test_vornQs32 (void)
+{
+
+  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
new file mode 100644 (file)
index 0000000..0d5d62d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int64x2_t out_int64x2_t;
+int64x2_t arg0_int64x2_t;
+int64x2_t arg1_int64x2_t;
+void test_vornQs64 (void)
+{
+
+  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
new file mode 100644 (file)
index 0000000..e68f760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int8x16_t out_int8x16_t;
+int8x16_t arg0_int8x16_t;
+int8x16_t arg1_int8x16_t;
+void test_vornQs8 (void)
+{
+
+  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
new file mode 100644 (file)
index 0000000..fe52b81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint16x8_t out_uint16x8_t;
+uint16x8_t arg0_uint16x8_t;
+uint16x8_t arg1_uint16x8_t;
+void test_vornQu16 (void)
+{
+
+  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
new file mode 100644 (file)
index 0000000..f311b77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32x4_t out_uint32x4_t;
+uint32x4_t arg0_uint32x4_t;
+uint32x4_t arg1_uint32x4_t;
+void test_vornQu32 (void)
+{
+
+  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
new file mode 100644 (file)
index 0000000..f5bfdac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint64x2_t out_uint64x2_t;
+uint64x2_t arg0_uint64x2_t;
+uint64x2_t arg1_uint64x2_t;
+void test_vornQu64 (void)
+{
+
+  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
new file mode 100644 (file)
index 0000000..cb318c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x16_t out_uint8x16_t;
+uint8x16_t arg0_uint8x16_t;
+uint8x16_t arg1_uint8x16_t;
+void test_vornQu8 (void)
+{
+
+  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc/testsuite/gcc.target/arm/neon/vorns16.c
new file mode 100644 (file)
index 0000000..a47fcf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns16.c
@@ -0,0 +1,20 @@
+/* Test the `vorns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int16x4_t out_int16x4_t;
+int16x4_t arg0_int16x4_t;
+int16x4_t arg1_int16x4_t;
+void test_vorns16 (void)
+{
+
+  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc/testsuite/gcc.target/arm/neon/vorns32.c
new file mode 100644 (file)
index 0000000..dd86cab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns32.c
@@ -0,0 +1,20 @@
+/* Test the `vorns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int32x2_t out_int32x2_t;
+int32x2_t arg0_int32x2_t;
+int32x2_t arg1_int32x2_t;
+void test_vorns32 (void)
+{
+
+  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc/testsuite/gcc.target/arm/neon/vorns64.c
new file mode 100644 (file)
index 0000000..0419574
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns64.c
@@ -0,0 +1,19 @@
+/* Test the `vorns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int64x1_t out_int64x1_t;
+int64x1_t arg0_int64x1_t;
+int64x1_t arg1_int64x1_t;
+void test_vorns64 (void)
+{
+
+  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc/testsuite/gcc.target/arm/neon/vorns8.c
new file mode 100644 (file)
index 0000000..76fd7e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorns8.c
@@ -0,0 +1,20 @@
+/* Test the `vorns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+int8x8_t out_int8x8_t;
+int8x8_t arg0_int8x8_t;
+int8x8_t arg1_int8x8_t;
+void test_vorns8 (void)
+{
+
+  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc/testsuite/gcc.target/arm/neon/vornu16.c
new file mode 100644 (file)
index 0000000..a3a33ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint16x4_t out_uint16x4_t;
+uint16x4_t arg0_uint16x4_t;
+uint16x4_t arg1_uint16x4_t;
+void test_vornu16 (void)
+{
+
+  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc/testsuite/gcc.target/arm/neon/vornu32.c
new file mode 100644 (file)
index 0000000..649b26c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32x2_t out_uint32x2_t;
+uint32x2_t arg0_uint32x2_t;
+uint32x2_t arg1_uint32x2_t;
+void test_vornu32 (void)
+{
+
+  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc/testsuite/gcc.target/arm/neon/vornu64.c
new file mode 100644 (file)
index 0000000..9bf3936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu64.c
@@ -0,0 +1,19 @@
+/* Test the `vornu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint64x1_t out_uint64x1_t;
+uint64x1_t arg0_uint64x1_t;
+uint64x1_t arg1_uint64x1_t;
+void test_vornu64 (void)
+{
+
+  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc/testsuite/gcc.target/arm/neon/vornu8.c
new file mode 100644 (file)
index 0000000..6a04641
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vornu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x8_t out_uint8x8_t;
+uint8x8_t arg0_uint8x8_t;
+uint8x8_t arg1_uint8x8_t;
+void test_vornu8 (void)
+{
+
+  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
new file mode 100644 (file)
index 0000000..b7318d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
new file mode 100644 (file)
index 0000000..3b0ffb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
new file mode 100644 (file)
index 0000000..e0fde9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
new file mode 100644 (file)
index 0000000..bd1e411
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
new file mode 100644 (file)
index 0000000..7df1c16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
new file mode 100644 (file)
index 0000000..1846888
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
new file mode 100644 (file)
index 0000000..a3b6897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
new file mode 100644 (file)
index 0000000..43850cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
new file mode 100644 (file)
index 0000000..7b6ec0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
new file mode 100644 (file)
index 0000000..4220159
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
new file mode 100644 (file)
index 0000000..4823779
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
@@ -0,0 +1,19 @@
+/* Test the `vorrs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
new file mode 100644 (file)
index 0000000..fc0c7b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc/testsuite/gcc.target/arm/neon/vorru16.c
new file mode 100644 (file)
index 0000000..c9e4cba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru16.c
@@ -0,0 +1,20 @@
+/* Test the `vorru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc/testsuite/gcc.target/arm/neon/vorru32.c
new file mode 100644 (file)
index 0000000..8683e21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru32.c
@@ -0,0 +1,20 @@
+/* Test the `vorru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc/testsuite/gcc.target/arm/neon/vorru64.c
new file mode 100644 (file)
index 0000000..d044713
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru64.c
@@ -0,0 +1,19 @@
+/* Test the `vorru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc/testsuite/gcc.target/arm/neon/vorru8.c
new file mode 100644 (file)
index 0000000..7422b5f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vorru8.c
@@ -0,0 +1,20 @@
+/* Test the `vorru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
new file mode 100644 (file)
index 0000000..2a69afc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
new file mode 100644 (file)
index 0000000..76d0b6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
new file mode 100644 (file)
index 0000000..4d3bf1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
new file mode 100644 (file)
index 0000000..f7ef536
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
new file mode 100644 (file)
index 0000000..2a0f821
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
new file mode 100644 (file)
index 0000000..d4c233b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
new file mode 100644 (file)
index 0000000..d49c2ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
new file mode 100644 (file)
index 0000000..b79746e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
new file mode 100644 (file)
index 0000000..cfde849
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
new file mode 100644 (file)
index 0000000..4b1777d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
new file mode 100644 (file)
index 0000000..772f0cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
new file mode 100644 (file)
index 0000000..700bf26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
new file mode 100644 (file)
index 0000000..d6f7846
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
new file mode 100644 (file)
index 0000000..f08fa83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
new file mode 100644 (file)
index 0000000..06305eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
new file mode 100644 (file)
index 0000000..ef17b07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
new file mode 100644 (file)
index 0000000..b301c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
new file mode 100644 (file)
index 0000000..77eaf83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
new file mode 100644 (file)
index 0000000..06a9902
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
new file mode 100644 (file)
index 0000000..28e0cfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
new file mode 100644 (file)
index 0000000..32de704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
new file mode 100644 (file)
index 0000000..c31ce4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
new file mode 100644 (file)
index 0000000..575b93e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
new file mode 100644 (file)
index 0000000..58f7b56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
new file mode 100644 (file)
index 0000000..458a4ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
new file mode 100644 (file)
index 0000000..962f827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
new file mode 100644 (file)
index 0000000..983f67c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
new file mode 100644 (file)
index 0000000..4985bd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
new file mode 100644 (file)
index 0000000..aa8942d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
new file mode 100644 (file)
index 0000000..84b8573
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
new file mode 100644 (file)
index 0000000..c59f99e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
new file mode 100644 (file)
index 0000000..4f329f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
new file mode 100644 (file)
index 0000000..42c06c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
new file mode 100644 (file)
index 0000000..3f8b31e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
new file mode 100644 (file)
index 0000000..3162b49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
new file mode 100644 (file)
index 0000000..195a0ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
new file mode 100644 (file)
index 0000000..263b9be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
new file mode 100644 (file)
index 0000000..ba4202e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
new file mode 100644 (file)
index 0000000..f754a16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.f32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
new file mode 100644 (file)
index 0000000..14da695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
new file mode 100644 (file)
index 0000000..324c524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
new file mode 100644 (file)
index 0000000..f8fecaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
new file mode 100644 (file)
index 0000000..06e18d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
new file mode 100644 (file)
index 0000000..b256311
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
new file mode 100644 (file)
index 0000000..04a3afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
new file mode 100644 (file)
index 0000000..e4b3b2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
new file mode 100644 (file)
index 0000000..9191d33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
new file mode 100644 (file)
index 0000000..fb30e26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
new file mode 100644 (file)
index 0000000..827b323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
new file mode 100644 (file)
index 0000000..30f71f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
new file mode 100644 (file)
index 0000000..467b0c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
new file mode 100644 (file)
index 0000000..5b303ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
new file mode 100644 (file)
index 0000000..3e8149a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
new file mode 100644 (file)
index 0000000..1495e40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
new file mode 100644 (file)
index 0000000..7ecd731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
new file mode 100644 (file)
index 0000000..be260b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
new file mode 100644 (file)
index 0000000..5b24353
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[        \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
new file mode 100644 (file)
index 0000000..366269e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
new file mode 100644 (file)
index 0000000..084e760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
new file mode 100644 (file)
index 0000000..e74623f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
new file mode 100644 (file)
index 0000000..b347ab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
new file mode 100644 (file)
index 0000000..34c3c14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
new file mode 100644 (file)
index 0000000..7006ce0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
new file mode 100644 (file)
index 0000000..d335402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
new file mode 100644 (file)
index 0000000..5252754
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
new file mode 100644 (file)
index 0000000..498c788
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
new file mode 100644 (file)
index 0000000..b46fd76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
new file mode 100644 (file)
index 0000000..844f2ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
new file mode 100644 (file)
index 0000000..c238d5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
new file mode 100644 (file)
index 0000000..24a2967
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
new file mode 100644 (file)
index 0000000..10df112
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
new file mode 100644 (file)
index 0000000..a0ef539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
new file mode 100644 (file)
index 0000000..b9fefe7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
new file mode 100644 (file)
index 0000000..a6b9f88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
new file mode 100644 (file)
index 0000000..30393e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
new file mode 100644 (file)
index 0000000..1ce5f77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
new file mode 100644 (file)
index 0000000..d869ff9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
new file mode 100644 (file)
index 0000000..7281f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
new file mode 100644 (file)
index 0000000..f7e6913
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
new file mode 100644 (file)
index 0000000..f1355be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s16\[        \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
new file mode 100644 (file)
index 0000000..55991a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s32\[        \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
new file mode 100644 (file)
index 0000000..80830ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[        \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
new file mode 100644 (file)
index 0000000..dbf857b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
new file mode 100644 (file)
index 0000000..ccad63a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
new file mode 100644 (file)
index 0000000..128d930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
new file mode 100644 (file)
index 0000000..9f503f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
new file mode 100644 (file)
index 0000000..4d80b1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
new file mode 100644 (file)
index 0000000..28e4583
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
new file mode 100644 (file)
index 0000000..d47b572
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
new file mode 100644 (file)
index 0000000..5d86a1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
new file mode 100644 (file)
index 0000000..39c11cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
new file mode 100644 (file)
index 0000000..494ba88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
new file mode 100644 (file)
index 0000000..5c99991
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
new file mode 100644 (file)
index 0000000..9e006a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
new file mode 100644 (file)
index 0000000..e52000a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
new file mode 100644 (file)
index 0000000..b587875
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
new file mode 100644 (file)
index 0000000..ddfbb2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
new file mode 100644 (file)
index 0000000..9155ca6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
new file mode 100644 (file)
index 0000000..11121d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
new file mode 100644 (file)
index 0000000..dff10c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
new file mode 100644 (file)
index 0000000..5d140c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
new file mode 100644 (file)
index 0000000..bd1678c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
new file mode 100644 (file)
index 0000000..9d57f74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
new file mode 100644 (file)
index 0000000..abf7c9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
new file mode 100644 (file)
index 0000000..a8fa442
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
new file mode 100644 (file)
index 0000000..d145a42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
new file mode 100644 (file)
index 0000000..ce94549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
new file mode 100644 (file)
index 0000000..c950629
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
new file mode 100644 (file)
index 0000000..a55c391
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
new file mode 100644 (file)
index 0000000..e91ef3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
new file mode 100644 (file)
index 0000000..362e63a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
new file mode 100644 (file)
index 0000000..3d8700f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
new file mode 100644 (file)
index 0000000..39b54ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
new file mode 100644 (file)
index 0000000..440c9e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
new file mode 100644 (file)
index 0000000..d4a9d37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
new file mode 100644 (file)
index 0000000..fb20e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
new file mode 100644 (file)
index 0000000..8067154
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
new file mode 100644 (file)
index 0000000..41902bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
new file mode 100644 (file)
index 0000000..fe0c768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
new file mode 100644 (file)
index 0000000..7070654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
new file mode 100644 (file)
index 0000000..ddc6b08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
new file mode 100644 (file)
index 0000000..3ae8af1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
new file mode 100644 (file)
index 0000000..648515a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
new file mode 100644 (file)
index 0000000..075e85e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
new file mode 100644 (file)
index 0000000..d33cc6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
new file mode 100644 (file)
index 0000000..4ff7e93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
new file mode 100644 (file)
index 0000000..57403bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
new file mode 100644 (file)
index 0000000..6ae9d34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
new file mode 100644 (file)
index 0000000..4257793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
new file mode 100644 (file)
index 0000000..874f890
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
new file mode 100644 (file)
index 0000000..aa60ce3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
new file mode 100644 (file)
index 0000000..7734d76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
new file mode 100644 (file)
index 0000000..876bc78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
new file mode 100644 (file)
index 0000000..ebc2062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[         \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
new file mode 100644 (file)
index 0000000..56d1764
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
new file mode 100644 (file)
index 0000000..086290c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
new file mode 100644 (file)
index 0000000..4f61c28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
new file mode 100644 (file)
index 0000000..294963c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
new file mode 100644 (file)
index 0000000..a580dd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
new file mode 100644 (file)
index 0000000..e07cd88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
new file mode 100644 (file)
index 0000000..82fdc20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
new file mode 100644 (file)
index 0000000..e56d890
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
new file mode 100644 (file)
index 0000000..06ad7e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
new file mode 100644 (file)
index 0000000..9a6c854
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
new file mode 100644 (file)
index 0000000..a93366f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
new file mode 100644 (file)
index 0000000..c566b49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
new file mode 100644 (file)
index 0000000..dbff5c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
new file mode 100644 (file)
index 0000000..2000358
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
new file mode 100644 (file)
index 0000000..beb3d55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
new file mode 100644 (file)
index 0000000..480ead6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
new file mode 100644 (file)
index 0000000..1a0c61a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
new file mode 100644 (file)
index 0000000..a6723ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
new file mode 100644 (file)
index 0000000..6767817
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
new file mode 100644 (file)
index 0000000..565b965
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
new file mode 100644 (file)
index 0000000..5d31d8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
new file mode 100644 (file)
index 0000000..4d5f88d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
new file mode 100644 (file)
index 0000000..2dacefe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
new file mode 100644 (file)
index 0000000..7868197
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
new file mode 100644 (file)
index 0000000..6de5599
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
new file mode 100644 (file)
index 0000000..395fd1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
new file mode 100644 (file)
index 0000000..58e2a51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
new file mode 100644 (file)
index 0000000..080ce27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
new file mode 100644 (file)
index 0000000..cc47ed5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
new file mode 100644 (file)
index 0000000..98cfb55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
new file mode 100644 (file)
index 0000000..1ff3dfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
new file mode 100644 (file)
index 0000000..4aa5760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
new file mode 100644 (file)
index 0000000..f42085d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
new file mode 100644 (file)
index 0000000..45c9b61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
new file mode 100644 (file)
index 0000000..2263fd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
new file mode 100644 (file)
index 0000000..926c91d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
new file mode 100644 (file)
index 0000000..3a43427
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
new file mode 100644 (file)
index 0000000..992b15c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
new file mode 100644 (file)
index 0000000..e0cfa5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
new file mode 100644 (file)
index 0000000..bd41202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
new file mode 100644 (file)
index 0000000..487f603
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
new file mode 100644 (file)
index 0000000..2d2ebae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
new file mode 100644 (file)
index 0000000..f9df74e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
new file mode 100644 (file)
index 0000000..75c98ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
new file mode 100644 (file)
index 0000000..3304981
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
new file mode 100644 (file)
index 0000000..e4ff98f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
new file mode 100644 (file)
index 0000000..9b61f4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
new file mode 100644 (file)
index 0000000..6fe5890
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
new file mode 100644 (file)
index 0000000..78ae2f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
new file mode 100644 (file)
index 0000000..45f5ba0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
new file mode 100644 (file)
index 0000000..47e1e85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
new file mode 100644 (file)
index 0000000..a168eb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
new file mode 100644 (file)
index 0000000..f625652
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
new file mode 100644 (file)
index 0000000..a7bd8e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
new file mode 100644 (file)
index 0000000..f8deec1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
new file mode 100644 (file)
index 0000000..887ed43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
new file mode 100644 (file)
index 0000000..3256226
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
new file mode 100644 (file)
index 0000000..949ad14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
new file mode 100644 (file)
index 0000000..944dcc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
new file mode 100644 (file)
index 0000000..ef9665e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
new file mode 100644 (file)
index 0000000..20da1cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
new file mode 100644 (file)
index 0000000..686c4e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s16\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
new file mode 100644 (file)
index 0000000..fcf370f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s32\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
new file mode 100644 (file)
index 0000000..e7f336e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s64\[         \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
new file mode 100644 (file)
index 0000000..2e555f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
new file mode 100644 (file)
index 0000000..f496cfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
new file mode 100644 (file)
index 0000000..d650235
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
new file mode 100644 (file)
index 0000000..3dddbec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
new file mode 100644 (file)
index 0000000..32cae60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
new file mode 100644 (file)
index 0000000..c6e90e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
new file mode 100644 (file)
index 0000000..59cf588
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
new file mode 100644 (file)
index 0000000..50478cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
new file mode 100644 (file)
index 0000000..b5ce2f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
new file mode 100644 (file)
index 0000000..c9290a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
new file mode 100644 (file)
index 0000000..2fee028
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
new file mode 100644 (file)
index 0000000..53b1add
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
new file mode 100644 (file)
index 0000000..68ecff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
new file mode 100644 (file)
index 0000000..bcb9db1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
new file mode 100644 (file)
index 0000000..1ca317b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
new file mode 100644 (file)
index 0000000..7946d1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
new file mode 100644 (file)
index 0000000..0883d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
new file mode 100644 (file)
index 0000000..5520989
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
new file mode 100644 (file)
index 0000000..d31cc86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
new file mode 100644 (file)
index 0000000..21ab98d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
new file mode 100644 (file)
index 0000000..aefe626
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
new file mode 100644 (file)
index 0000000..8dac29c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
new file mode 100644 (file)
index 0000000..240c1d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p128 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
new file mode 100644 (file)
index 0000000..6e76ba6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p16 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
new file mode 100644 (file)
index 0000000..ba66ff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p64 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
new file mode 100644 (file)
index 0000000..d13e01f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p8 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
new file mode 100644 (file)
index 0000000..70c48e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s16 (void)
+{
+  float32x4_t out_float32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
new file mode 100644 (file)
index 0000000..546139e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
new file mode 100644 (file)
index 0000000..a87ccff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s64 (void)
+{
+  float32x4_t out_float32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
new file mode 100644 (file)
index 0000000..3d46bec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s8 (void)
+{
+  float32x4_t out_float32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
new file mode 100644 (file)
index 0000000..3b0b189
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u16 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
new file mode 100644 (file)
index 0000000..bc54aa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
new file mode 100644 (file)
index 0000000..d582c5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u64 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
new file mode 100644 (file)
index 0000000..956db9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u8 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
new file mode 100644 (file)
index 0000000..72732da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_f32 (void)
+{
+  poly128_t out_poly128_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
new file mode 100644 (file)
index 0000000..52c3365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p16 (void)
+{
+  poly128_t out_poly128_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
new file mode 100644 (file)
index 0000000..2f86cfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p64 (void)
+{
+  poly128_t out_poly128_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
new file mode 100644 (file)
index 0000000..6964e39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p8 (void)
+{
+  poly128_t out_poly128_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
new file mode 100644 (file)
index 0000000..a6f162b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s16 (void)
+{
+  poly128_t out_poly128_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
new file mode 100644 (file)
index 0000000..66f4893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s32 (void)
+{
+  poly128_t out_poly128_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
new file mode 100644 (file)
index 0000000..5437f31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s64 (void)
+{
+  poly128_t out_poly128_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
new file mode 100644 (file)
index 0000000..a4006ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s8 (void)
+{
+  poly128_t out_poly128_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
new file mode 100644 (file)
index 0000000..00aaf3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u16 (void)
+{
+  poly128_t out_poly128_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
new file mode 100644 (file)
index 0000000..bf70c55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u32 (void)
+{
+  poly128_t out_poly128_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
new file mode 100644 (file)
index 0000000..092d18a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u64 (void)
+{
+  poly128_t out_poly128_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
new file mode 100644 (file)
index 0000000..39671d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u8 (void)
+{
+  poly128_t out_poly128_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
new file mode 100644 (file)
index 0000000..5862926
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_f32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
new file mode 100644 (file)
index 0000000..8bdd6aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p128 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
new file mode 100644 (file)
index 0000000..8073d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
new file mode 100644 (file)
index 0000000..71ea56d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
new file mode 100644 (file)
index 0000000..8073ad1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
new file mode 100644 (file)
index 0000000..08c3c44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
new file mode 100644 (file)
index 0000000..8c82181
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
new file mode 100644 (file)
index 0000000..dd3bad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
new file mode 100644 (file)
index 0000000..bb3557c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
new file mode 100644 (file)
index 0000000..ede90f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
new file mode 100644 (file)
index 0000000..51692b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
new file mode 100644 (file)
index 0000000..020f6cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
new file mode 100644 (file)
index 0000000..97a64f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_f32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
new file mode 100644 (file)
index 0000000..50db979
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p128 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
new file mode 100644 (file)
index 0000000..4395794
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
new file mode 100644 (file)
index 0000000..0bf635c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
new file mode 100644 (file)
index 0000000..13320e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
new file mode 100644 (file)
index 0000000..3377d50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
new file mode 100644 (file)
index 0000000..c5fd29e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
new file mode 100644 (file)
index 0000000..b85ce4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
new file mode 100644 (file)
index 0000000..a46231c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
new file mode 100644 (file)
index 0000000..be0f4d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
new file mode 100644 (file)
index 0000000..1c141b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
new file mode 100644 (file)
index 0000000..25cd2e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
new file mode 100644 (file)
index 0000000..017fd16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_f32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
new file mode 100644 (file)
index 0000000..3c12a5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p128 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
new file mode 100644 (file)
index 0000000..9fb4fa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
new file mode 100644 (file)
index 0000000..2b5b815
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
new file mode 100644 (file)
index 0000000..91ad505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
new file mode 100644 (file)
index 0000000..0ab4eff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
new file mode 100644 (file)
index 0000000..946b824
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
new file mode 100644 (file)
index 0000000..f07c24a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
new file mode 100644 (file)
index 0000000..b776ef0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
new file mode 100644 (file)
index 0000000..b74c757
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
new file mode 100644 (file)
index 0000000..fc89c81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
new file mode 100644 (file)
index 0000000..82f02fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
new file mode 100644 (file)
index 0000000..e74ca76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_f32 (void)
+{
+  int16x8_t out_int16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
new file mode 100644 (file)
index 0000000..da932d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p128 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
new file mode 100644 (file)
index 0000000..e643ed9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p16 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
new file mode 100644 (file)
index 0000000..ce15357
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p64 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
new file mode 100644 (file)
index 0000000..e3b28f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p8 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
new file mode 100644 (file)
index 0000000..8ffa8a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s32 (void)
+{
+  int16x8_t out_int16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
new file mode 100644 (file)
index 0000000..caa23fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s64 (void)
+{
+  int16x8_t out_int16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
new file mode 100644 (file)
index 0000000..57e03d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
new file mode 100644 (file)
index 0000000..03497b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
new file mode 100644 (file)
index 0000000..1d264b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u32 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
new file mode 100644 (file)
index 0000000..355a0aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u64 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
new file mode 100644 (file)
index 0000000..339ed27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u8 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
new file mode 100644 (file)
index 0000000..857db63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
new file mode 100644 (file)
index 0000000..eb1d7ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p128 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
new file mode 100644 (file)
index 0000000..0dc4d48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p16 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
new file mode 100644 (file)
index 0000000..00e3a61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p64 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
new file mode 100644 (file)
index 0000000..07c7870
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p8 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
new file mode 100644 (file)
index 0000000..5d72da9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
new file mode 100644 (file)
index 0000000..c1d8593
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s64 (void)
+{
+  int32x4_t out_int32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
new file mode 100644 (file)
index 0000000..0ba13b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s8 (void)
+{
+  int32x4_t out_int32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
new file mode 100644 (file)
index 0000000..35ed106
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u16 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
new file mode 100644 (file)
index 0000000..dc6082f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
new file mode 100644 (file)
index 0000000..c0083bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u64 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
new file mode 100644 (file)
index 0000000..7cba3e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u8 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
new file mode 100644 (file)
index 0000000..e4f1de3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_f32 (void)
+{
+  int64x2_t out_int64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
new file mode 100644 (file)
index 0000000..e4cb353
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p128 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
new file mode 100644 (file)
index 0000000..35b36c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p16 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
new file mode 100644 (file)
index 0000000..384bde6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p64 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
new file mode 100644 (file)
index 0000000..434ad4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p8 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
new file mode 100644 (file)
index 0000000..b03138e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s16 (void)
+{
+  int64x2_t out_int64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
new file mode 100644 (file)
index 0000000..efe19b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
new file mode 100644 (file)
index 0000000..3d62931
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s8 (void)
+{
+  int64x2_t out_int64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
new file mode 100644 (file)
index 0000000..2155784
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u16 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
new file mode 100644 (file)
index 0000000..aa9bf07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u32 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
new file mode 100644 (file)
index 0000000..20c9b78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
new file mode 100644 (file)
index 0000000..28baec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u8 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
new file mode 100644 (file)
index 0000000..c3830d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_f32 (void)
+{
+  int8x16_t out_int8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
new file mode 100644 (file)
index 0000000..ee60845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p128 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
new file mode 100644 (file)
index 0000000..739f0ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p16 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
new file mode 100644 (file)
index 0000000..3c8b458
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p64 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
new file mode 100644 (file)
index 0000000..1702e8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p8 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
new file mode 100644 (file)
index 0000000..593209e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s16 (void)
+{
+  int8x16_t out_int8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
new file mode 100644 (file)
index 0000000..ecd67ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s32 (void)
+{
+  int8x16_t out_int8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
new file mode 100644 (file)
index 0000000..eea205c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s64 (void)
+{
+  int8x16_t out_int8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
new file mode 100644 (file)
index 0000000..ca8c856
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u16 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
new file mode 100644 (file)
index 0000000..714567a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u32 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
new file mode 100644 (file)
index 0000000..2471b81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u64 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
new file mode 100644 (file)
index 0000000..816c645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
new file mode 100644 (file)
index 0000000..0d9218e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_f32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
new file mode 100644 (file)
index 0000000..6f45c3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p128 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
new file mode 100644 (file)
index 0000000..cbc19e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
new file mode 100644 (file)
index 0000000..f11a751
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
new file mode 100644 (file)
index 0000000..ff38614
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
new file mode 100644 (file)
index 0000000..8842c47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
new file mode 100644 (file)
index 0000000..dc23a4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
new file mode 100644 (file)
index 0000000..92179de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
new file mode 100644 (file)
index 0000000..ceff877
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
new file mode 100644 (file)
index 0000000..c0f49ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
new file mode 100644 (file)
index 0000000..a80bea2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
new file mode 100644 (file)
index 0000000..bcf28c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
new file mode 100644 (file)
index 0000000..95608e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
new file mode 100644 (file)
index 0000000..83254ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p128 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
new file mode 100644 (file)
index 0000000..6a55e7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
new file mode 100644 (file)
index 0000000..b0c446d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
new file mode 100644 (file)
index 0000000..b8d4905
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
new file mode 100644 (file)
index 0000000..85a1ec8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
new file mode 100644 (file)
index 0000000..60c1750
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
new file mode 100644 (file)
index 0000000..bf02d09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
new file mode 100644 (file)
index 0000000..8bd7760
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
new file mode 100644 (file)
index 0000000..2326bc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
new file mode 100644 (file)
index 0000000..0386681
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
new file mode 100644 (file)
index 0000000..14f63d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
new file mode 100644 (file)
index 0000000..6a8559d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_f32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
new file mode 100644 (file)
index 0000000..1dc0309
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p128 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
new file mode 100644 (file)
index 0000000..f4a31ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
new file mode 100644 (file)
index 0000000..187da75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
new file mode 100644 (file)
index 0000000..1980714
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
new file mode 100644 (file)
index 0000000..93673de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
new file mode 100644 (file)
index 0000000..60c0042
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
new file mode 100644 (file)
index 0000000..da88b54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
new file mode 100644 (file)
index 0000000..b5322aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
new file mode 100644 (file)
index 0000000..06bf44e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
new file mode 100644 (file)
index 0000000..2d71f71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
new file mode 100644 (file)
index 0000000..f870e92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
new file mode 100644 (file)
index 0000000..8aaffda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_f32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
new file mode 100644 (file)
index 0000000..eff6df5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p128 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
new file mode 100644 (file)
index 0000000..ac9b586
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
new file mode 100644 (file)
index 0000000..e75b8a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
new file mode 100644 (file)
index 0000000..0d49f7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
new file mode 100644 (file)
index 0000000..37f3fed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
new file mode 100644 (file)
index 0000000..0ed46fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
new file mode 100644 (file)
index 0000000..73dc999
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
new file mode 100644 (file)
index 0000000..a243537
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
new file mode 100644 (file)
index 0000000..57e4053
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
new file mode 100644 (file)
index 0000000..98b998f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
new file mode 100644 (file)
index 0000000..0cebf4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
new file mode 100644 (file)
index 0000000..6bec08e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p16 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
new file mode 100644 (file)
index 0000000..bb7ea60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p64 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
new file mode 100644 (file)
index 0000000..05a4eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p8 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
new file mode 100644 (file)
index 0000000..dbf514b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s16 (void)
+{
+  float32x2_t out_float32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
new file mode 100644 (file)
index 0000000..133bade
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
new file mode 100644 (file)
index 0000000..7a9045e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s64 (void)
+{
+  float32x2_t out_float32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
new file mode 100644 (file)
index 0000000..256f6a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s8 (void)
+{
+  float32x2_t out_float32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
new file mode 100644 (file)
index 0000000..319c0f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u16 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
new file mode 100644 (file)
index 0000000..3e4b1d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
new file mode 100644 (file)
index 0000000..880ab42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u64 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
new file mode 100644 (file)
index 0000000..0f25f6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u8 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
new file mode 100644 (file)
index 0000000..276b8c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_f32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
new file mode 100644 (file)
index 0000000..67799cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
new file mode 100644 (file)
index 0000000..837d731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
new file mode 100644 (file)
index 0000000..099ed52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
new file mode 100644 (file)
index 0000000..027c156
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
new file mode 100644 (file)
index 0000000..2fdc5e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
new file mode 100644 (file)
index 0000000..1b6828f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
new file mode 100644 (file)
index 0000000..f661317
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
new file mode 100644 (file)
index 0000000..b59d492
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
new file mode 100644 (file)
index 0000000..fcebd51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
new file mode 100644 (file)
index 0000000..c6a6f2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
new file mode 100644 (file)
index 0000000..1905a99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_f32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
new file mode 100644 (file)
index 0000000..546d7ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
new file mode 100644 (file)
index 0000000..0a36a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
new file mode 100644 (file)
index 0000000..9487559
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
new file mode 100644 (file)
index 0000000..ffca4cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
new file mode 100644 (file)
index 0000000..c3a0173
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
new file mode 100644 (file)
index 0000000..ba12a05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
new file mode 100644 (file)
index 0000000..9a60595
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
new file mode 100644 (file)
index 0000000..cb61d53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
new file mode 100644 (file)
index 0000000..1459a49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
new file mode 100644 (file)
index 0000000..4e8fcf6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
new file mode 100644 (file)
index 0000000..e128056
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_f32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
new file mode 100644 (file)
index 0000000..736741c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
new file mode 100644 (file)
index 0000000..3516626
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
new file mode 100644 (file)
index 0000000..6a065c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
new file mode 100644 (file)
index 0000000..90a8b77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
new file mode 100644 (file)
index 0000000..3893ba2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
new file mode 100644 (file)
index 0000000..5fb4c7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
new file mode 100644 (file)
index 0000000..398470f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
new file mode 100644 (file)
index 0000000..f60d7cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
new file mode 100644 (file)
index 0000000..c874eb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
new file mode 100644 (file)
index 0000000..cead64b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
new file mode 100644 (file)
index 0000000..904fcb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_f32 (void)
+{
+  int16x4_t out_int16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
new file mode 100644 (file)
index 0000000..d03a724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p16 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
new file mode 100644 (file)
index 0000000..87f02b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p64 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
new file mode 100644 (file)
index 0000000..a54b2c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p8 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
new file mode 100644 (file)
index 0000000..c395ad2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
new file mode 100644 (file)
index 0000000..41b75d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s64 (void)
+{
+  int16x4_t out_int16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
new file mode 100644 (file)
index 0000000..9746bda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
new file mode 100644 (file)
index 0000000..f7bd522
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
new file mode 100644 (file)
index 0000000..db7ef6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u32 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
new file mode 100644 (file)
index 0000000..b36ad0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u64 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
new file mode 100644 (file)
index 0000000..c5af74d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u8 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
new file mode 100644 (file)
index 0000000..10f41dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
new file mode 100644 (file)
index 0000000..0f29b7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p16 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
new file mode 100644 (file)
index 0000000..f670990
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p64 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
new file mode 100644 (file)
index 0000000..ba21615
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p8 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
new file mode 100644 (file)
index 0000000..c0142ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
new file mode 100644 (file)
index 0000000..e1499a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
new file mode 100644 (file)
index 0000000..311a708
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s8 (void)
+{
+  int32x2_t out_int32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
new file mode 100644 (file)
index 0000000..eaf5eb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u16 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
new file mode 100644 (file)
index 0000000..65ab858
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
new file mode 100644 (file)
index 0000000..4338d10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u64 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
new file mode 100644 (file)
index 0000000..74f7899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u8 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
new file mode 100644 (file)
index 0000000..3510bed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_f32 (void)
+{
+  int64x1_t out_int64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
new file mode 100644 (file)
index 0000000..e239a96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p16 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
new file mode 100644 (file)
index 0000000..d20075c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p64 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
new file mode 100644 (file)
index 0000000..5219607
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p8 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
new file mode 100644 (file)
index 0000000..cfcbc7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s16 (void)
+{
+  int64x1_t out_int64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
new file mode 100644 (file)
index 0000000..7467413
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
new file mode 100644 (file)
index 0000000..5cb98ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s8 (void)
+{
+  int64x1_t out_int64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
new file mode 100644 (file)
index 0000000..5135100
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u16 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
new file mode 100644 (file)
index 0000000..1536b5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u32 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
new file mode 100644 (file)
index 0000000..ae8f710
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
new file mode 100644 (file)
index 0000000..86eb6fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u8 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
new file mode 100644 (file)
index 0000000..f582e5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_f32 (void)
+{
+  int8x8_t out_int8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
new file mode 100644 (file)
index 0000000..9959252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p16 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
new file mode 100644 (file)
index 0000000..c61f6b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p64 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
new file mode 100644 (file)
index 0000000..4b1d366
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p8 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
new file mode 100644 (file)
index 0000000..3d797d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
new file mode 100644 (file)
index 0000000..ab9755b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s32 (void)
+{
+  int8x8_t out_int8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
new file mode 100644 (file)
index 0000000..3b56bc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s64 (void)
+{
+  int8x8_t out_int8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
new file mode 100644 (file)
index 0000000..4daf409
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u16 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
new file mode 100644 (file)
index 0000000..2c10e40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u32 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
new file mode 100644 (file)
index 0000000..3395f57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u64 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
new file mode 100644 (file)
index 0000000..d9b7c58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
new file mode 100644 (file)
index 0000000..761d6cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_f32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
new file mode 100644 (file)
index 0000000..da0604d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
new file mode 100644 (file)
index 0000000..d7d6665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
new file mode 100644 (file)
index 0000000..46c87d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
new file mode 100644 (file)
index 0000000..58d4611
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
new file mode 100644 (file)
index 0000000..e833a2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
new file mode 100644 (file)
index 0000000..78c964b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
new file mode 100644 (file)
index 0000000..862589d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
new file mode 100644 (file)
index 0000000..df8fdbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
new file mode 100644 (file)
index 0000000..c9b64f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
new file mode 100644 (file)
index 0000000..41b9c25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
new file mode 100644 (file)
index 0000000..c8f91b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
new file mode 100644 (file)
index 0000000..8cf8f78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
new file mode 100644 (file)
index 0000000..f1303d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
new file mode 100644 (file)
index 0000000..5cf6cb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
new file mode 100644 (file)
index 0000000..9a968fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
new file mode 100644 (file)
index 0000000..f9f701f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
new file mode 100644 (file)
index 0000000..4eee1fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
new file mode 100644 (file)
index 0000000..e6afe8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
new file mode 100644 (file)
index 0000000..a2813b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
new file mode 100644 (file)
index 0000000..8de7e2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
new file mode 100644 (file)
index 0000000..df329a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
new file mode 100644 (file)
index 0000000..1da62f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_f32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
new file mode 100644 (file)
index 0000000..9de7986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
new file mode 100644 (file)
index 0000000..86304b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
new file mode 100644 (file)
index 0000000..6a807f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
new file mode 100644 (file)
index 0000000..d752efa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
new file mode 100644 (file)
index 0000000..362a83e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
new file mode 100644 (file)
index 0000000..cb19d47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
new file mode 100644 (file)
index 0000000..d0ff42b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
new file mode 100644 (file)
index 0000000..8d00c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
new file mode 100644 (file)
index 0000000..e0fb4f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
new file mode 100644 (file)
index 0000000..27cd543
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
new file mode 100644 (file)
index 0000000..8b3d207
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_f32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
new file mode 100644 (file)
index 0000000..c98b963
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
new file mode 100644 (file)
index 0000000..ecfa9f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
new file mode 100644 (file)
index 0000000..a666f3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
new file mode 100644 (file)
index 0000000..e33579b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
new file mode 100644 (file)
index 0000000..c572728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
new file mode 100644 (file)
index 0000000..726b6ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
new file mode 100644 (file)
index 0000000..df58c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
new file mode 100644 (file)
index 0000000..00bf9a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
new file mode 100644 (file)
index 0000000..8670b08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
new file mode 100644 (file)
index 0000000..509ece7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
new file mode 100644 (file)
index 0000000..b31084f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
new file mode 100644 (file)
index 0000000..dfb3531
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
new file mode 100644 (file)
index 0000000..f3b1861
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
new file mode 100644 (file)
index 0000000..6d76ab0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
new file mode 100644 (file)
index 0000000..f2d79c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
new file mode 100644 (file)
index 0000000..9e70e66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
new file mode 100644 (file)
index 0000000..3d24c0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
new file mode 100644 (file)
index 0000000..50bd272
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
new file mode 100644 (file)
index 0000000..c65ae15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
new file mode 100644 (file)
index 0000000..80bfddf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
new file mode 100644 (file)
index 0000000..2974371
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
new file mode 100644 (file)
index 0000000..0d0beab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
new file mode 100644 (file)
index 0000000..65fb8c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
new file mode 100644 (file)
index 0000000..f307819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
new file mode 100644 (file)
index 0000000..8f8daa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
new file mode 100644 (file)
index 0000000..da69ab4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
new file mode 100644 (file)
index 0000000..6798acf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
new file mode 100644 (file)
index 0000000..1dce99d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
new file mode 100644 (file)
index 0000000..2db0016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
new file mode 100644 (file)
index 0000000..1dffde9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
new file mode 100644 (file)
index 0000000..37b629b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
new file mode 100644 (file)
index 0000000..1e37eb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
new file mode 100644 (file)
index 0000000..c71a8b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
new file mode 100644 (file)
index 0000000..f6a6b5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
new file mode 100644 (file)
index 0000000..94ca3a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
new file mode 100644 (file)
index 0000000..0840b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
new file mode 100644 (file)
index 0000000..11177e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
new file mode 100644 (file)
index 0000000..d2766d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64f32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
new file mode 100644 (file)
index 0000000..359ba0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
new file mode 100644 (file)
index 0000000..e4621d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
new file mode 100644 (file)
index 0000000..b6d7545
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
new file mode 100644 (file)
index 0000000..8e85e84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
new file mode 100644 (file)
index 0000000..63b9c19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
new file mode 100644 (file)
index 0000000..250ade5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
new file mode 100644 (file)
index 0000000..1028ec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[   \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
new file mode 100644 (file)
index 0000000..4145a59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
new file mode 100644 (file)
index 0000000..6bec8fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrnda_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrinta\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c
new file mode 100644 (file)
index 0000000..a29a71d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndaq_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndaqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndaq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrinta\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
new file mode 100644 (file)
index 0000000..fa97603
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrnd_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintz\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
new file mode 100644 (file)
index 0000000..2155224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndmf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndmf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndm_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintm\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c
new file mode 100644 (file)
index 0000000..3dc0422
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndmq_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndmqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndmq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintm\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
new file mode 100644 (file)
index 0000000..bd159eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndnf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndn_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintn\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c
new file mode 100644 (file)
index 0000000..628488f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndnq_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndnqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndnq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintn\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
new file mode 100644 (file)
index 0000000..baa2ca9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndpf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndp_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintp\.f32\[  \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c
new file mode 100644 (file)
index 0000000..5c26956
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndpq_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndpqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndpq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintp\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
new file mode 100644 (file)
index 0000000..13365c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrndqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintz\.f32\[  \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
new file mode 100644 (file)
index 0000000..1ee3793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
new file mode 100644 (file)
index 0000000..db9ab28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
new file mode 100644 (file)
index 0000000..0abcd7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
new file mode 100644 (file)
index 0000000..f133dc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
new file mode 100644 (file)
index 0000000..8b141c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[         \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
new file mode 100644 (file)
index 0000000..c400847
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[         \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
new file mode 100644 (file)
index 0000000..b7a5512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
new file mode 100644 (file)
index 0000000..0469323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
new file mode 100644 (file)
index 0000000..90c1c2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
new file mode 100644 (file)
index 0000000..38cdf11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
new file mode 100644 (file)
index 0000000..d4edb56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
new file mode 100644 (file)
index 0000000..37bf0b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
new file mode 100644 (file)
index 0000000..5b46085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
new file mode 100644 (file)
index 0000000..6ba9251
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
new file mode 100644 (file)
index 0000000..4cb1e9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
new file mode 100644 (file)
index 0000000..9cf4dc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[         \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
new file mode 100644 (file)
index 0000000..0265d0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
new file mode 100644 (file)
index 0000000..4ce2e44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
new file mode 100644 (file)
index 0000000..788ddd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
new file mode 100644 (file)
index 0000000..5ea5199
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
new file mode 100644 (file)
index 0000000..95a6a90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
new file mode 100644 (file)
index 0000000..340412b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
new file mode 100644 (file)
index 0000000..e137338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
new file mode 100644 (file)
index 0000000..b905d9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
new file mode 100644 (file)
index 0000000..1ba3682
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
new file mode 100644 (file)
index 0000000..820dd95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[     \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
new file mode 100644 (file)
index 0000000..40c2fad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
new file mode 100644 (file)
index 0000000..f15725f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[      \]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
new file mode 100644 (file)
index 0000000..d184325
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
new file mode 100644 (file)
index 0000000..f3f8080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
new file mode 100644 (file)
index 0000000..7f10e0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
new file mode 100644 (file)
index 0000000..18656a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
new file mode 100644 (file)
index 0000000..d4f8f5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
new file mode 100644 (file)
index 0000000..304ece8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
new file mode 100644 (file)
index 0000000..4f3bd4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
new file mode 100644 (file)
index 0000000..254eb20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
new file mode 100644 (file)
index 0000000..a497786
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
new file mode 100644 (file)
index 0000000..2fee8ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
new file mode 100644 (file)
index 0000000..5565b8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
new file mode 100644 (file)
index 0000000..f825f29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
new file mode 100644 (file)
index 0000000..268d8e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
new file mode 100644 (file)
index 0000000..489d6cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
new file mode 100644 (file)
index 0000000..936824c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
new file mode 100644 (file)
index 0000000..b683eda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
new file mode 100644 (file)
index 0000000..75fac2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
new file mode 100644 (file)
index 0000000..358f6d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
new file mode 100644 (file)
index 0000000..a36aba0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
new file mode 100644 (file)
index 0000000..27454e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
new file mode 100644 (file)
index 0000000..27745fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
new file mode 100644 (file)
index 0000000..feead55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
new file mode 100644 (file)
index 0000000..c76fab0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
new file mode 100644 (file)
index 0000000..cbf2409
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
new file mode 100644 (file)
index 0000000..2173f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
new file mode 100644 (file)
index 0000000..c9e44d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
new file mode 100644 (file)
index 0000000..2c7220a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
new file mode 100644 (file)
index 0000000..03eea9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
new file mode 100644 (file)
index 0000000..6c162b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
new file mode 100644 (file)
index 0000000..5c1bfcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc/testsuite/gcc.target/arm/neon/vshls16.c
new file mode 100644 (file)
index 0000000..b7812ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc/testsuite/gcc.target/arm/neon/vshls32.c
new file mode 100644 (file)
index 0000000..1d2b849
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc/testsuite/gcc.target/arm/neon/vshls64.c
new file mode 100644 (file)
index 0000000..02b3c36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc/testsuite/gcc.target/arm/neon/vshls8.c
new file mode 100644 (file)
index 0000000..dfe9db4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
new file mode 100644 (file)
index 0000000..2ad9a50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
new file mode 100644 (file)
index 0000000..dfa5524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
new file mode 100644 (file)
index 0000000..457ae42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
new file mode 100644 (file)
index 0000000..6438ed3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
new file mode 100644 (file)
index 0000000..499ba2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
new file mode 100644 (file)
index 0000000..1c5341e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
new file mode 100644 (file)
index 0000000..ad72b6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
new file mode 100644 (file)
index 0000000..ba6efab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
new file mode 100644 (file)
index 0000000..99c566a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
new file mode 100644 (file)
index 0000000..7f51823
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
new file mode 100644 (file)
index 0000000..ff5a270
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
new file mode 100644 (file)
index 0000000..5cde269
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
new file mode 100644 (file)
index 0000000..b49a0e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
new file mode 100644 (file)
index 0000000..a5809bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
new file mode 100644 (file)
index 0000000..5c6f493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
new file mode 100644 (file)
index 0000000..1fa24b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
new file mode 100644 (file)
index 0000000..5b8e454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
new file mode 100644 (file)
index 0000000..28a7695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
new file mode 100644 (file)
index 0000000..435466b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
new file mode 100644 (file)
index 0000000..8d67a42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
new file mode 100644 (file)
index 0000000..6dc485d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
new file mode 100644 (file)
index 0000000..b7c9336
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
new file mode 100644 (file)
index 0000000..7d0156a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
new file mode 100644 (file)
index 0000000..1c8b720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
new file mode 100644 (file)
index 0000000..6797a96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
new file mode 100644 (file)
index 0000000..ee66e03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[   \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
new file mode 100644 (file)
index 0000000..19cc7a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
new file mode 100644 (file)
index 0000000..b7ca823
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
new file mode 100644 (file)
index 0000000..52658e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
new file mode 100644 (file)
index 0000000..6bf2424
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
new file mode 100644 (file)
index 0000000..8b61de4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
new file mode 100644 (file)
index 0000000..00a3b1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
new file mode 100644 (file)
index 0000000..7c8cd8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
new file mode 100644 (file)
index 0000000..e5df31e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
new file mode 100644 (file)
index 0000000..4e18c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
new file mode 100644 (file)
index 0000000..cf88f62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
new file mode 100644 (file)
index 0000000..510a992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
new file mode 100644 (file)
index 0000000..0b3015b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
new file mode 100644 (file)
index 0000000..c22a201
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsli_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
new file mode 100644 (file)
index 0000000..4db6073
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
new file mode 100644 (file)
index 0000000..c2e7d7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
new file mode 100644 (file)
index 0000000..11a10d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
new file mode 100644 (file)
index 0000000..b062ea8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
new file mode 100644 (file)
index 0000000..d9408ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
new file mode 100644 (file)
index 0000000..5bfb4b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
new file mode 100644 (file)
index 0000000..d91a2bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
new file mode 100644 (file)
index 0000000..cc27d52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
new file mode 100644 (file)
index 0000000..937dd91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
new file mode 100644 (file)
index 0000000..97e1c4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
new file mode 100644 (file)
index 0000000..7d45a3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
new file mode 100644 (file)
index 0000000..b4069ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
new file mode 100644 (file)
index 0000000..a849cae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
new file mode 100644 (file)
index 0000000..ed25820
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
new file mode 100644 (file)
index 0000000..1be7cff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
new file mode 100644 (file)
index 0000000..79c4fac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
new file mode 100644 (file)
index 0000000..e095fae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
new file mode 100644 (file)
index 0000000..b112bbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
new file mode 100644 (file)
index 0000000..9ebcf6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
new file mode 100644 (file)
index 0000000..132da31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
new file mode 100644 (file)
index 0000000..97f62ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
new file mode 100644 (file)
index 0000000..3dcb487
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
new file mode 100644 (file)
index 0000000..63dea5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
new file mode 100644 (file)
index 0000000..2751a68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
new file mode 100644 (file)
index 0000000..49909b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
new file mode 100644 (file)
index 0000000..8413d07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
new file mode 100644 (file)
index 0000000..ca3a9f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
new file mode 100644 (file)
index 0000000..1683fe6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
new file mode 100644 (file)
index 0000000..8e1bcbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
new file mode 100644 (file)
index 0000000..41c611c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
new file mode 100644 (file)
index 0000000..3a8648a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
new file mode 100644 (file)
index 0000000..41457da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
new file mode 100644 (file)
index 0000000..33f9fa8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
new file mode 100644 (file)
index 0000000..951f28f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
new file mode 100644 (file)
index 0000000..ff8e81c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
new file mode 100644 (file)
index 0000000..6cdf11d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
new file mode 100644 (file)
index 0000000..9e3fe6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
new file mode 100644 (file)
index 0000000..0734b12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsri_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
new file mode 100644 (file)
index 0000000..fd3d55e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
new file mode 100644 (file)
index 0000000..4631cbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
new file mode 100644 (file)
index 0000000..163a3c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
new file mode 100644 (file)
index 0000000..de2b7cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
new file mode 100644 (file)
index 0000000..b9d74b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
new file mode 100644 (file)
index 0000000..f1a7c6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
new file mode 100644 (file)
index 0000000..9d67c31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
new file mode 100644 (file)
index 0000000..4a9da82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
new file mode 100644 (file)
index 0000000..2536746
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
new file mode 100644 (file)
index 0000000..a05612b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
new file mode 100644 (file)
index 0000000..7b74781
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
new file mode 100644 (file)
index 0000000..08060d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
new file mode 100644 (file)
index 0000000..40181c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
new file mode 100644 (file)
index 0000000..a4d7d35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
new file mode 100644 (file)
index 0000000..e0d8ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
new file mode 100644 (file)
index 0000000..6b82ff4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
new file mode 100644 (file)
index 0000000..7266890
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
new file mode 100644 (file)
index 0000000..1281976
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
new file mode 100644 (file)
index 0000000..79b7cbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
new file mode 100644 (file)
index 0000000..84d6250
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
new file mode 100644 (file)
index 0000000..578a2f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
new file mode 100644 (file)
index 0000000..1d13c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
new file mode 100644 (file)
index 0000000..281d8da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
new file mode 100644 (file)
index 0000000..8a4de71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
new file mode 100644 (file)
index 0000000..f1e39ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
new file mode 100644 (file)
index 0000000..73c1e29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
new file mode 100644 (file)
index 0000000..8c7c345
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
new file mode 100644 (file)
index 0000000..ec09003
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
new file mode 100644 (file)
index 0000000..5a2d815
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
new file mode 100644 (file)
index 0000000..a129e66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
new file mode 100644 (file)
index 0000000..e79ab86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
new file mode 100644 (file)
index 0000000..c7c088c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
new file mode 100644 (file)
index 0000000..b9159a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
new file mode 100644 (file)
index 0000000..edbfe1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
new file mode 100644 (file)
index 0000000..d02a234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
new file mode 100644 (file)
index 0000000..74e4519
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
new file mode 100644 (file)
index 0000000..e161933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
new file mode 100644 (file)
index 0000000..d12acba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
new file mode 100644 (file)
index 0000000..5bec595
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
new file mode 100644 (file)
index 0000000..acefe71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
new file mode 100644 (file)
index 0000000..d0557ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
new file mode 100644 (file)
index 0000000..39357ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
new file mode 100644 (file)
index 0000000..8ae372b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
new file mode 100644 (file)
index 0000000..5620876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
new file mode 100644 (file)
index 0000000..0a1f252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
new file mode 100644 (file)
index 0000000..8b9f3f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
new file mode 100644 (file)
index 0000000..4d7b2fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
new file mode 100644 (file)
index 0000000..9fa82b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
new file mode 100644 (file)
index 0000000..b629bfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
new file mode 100644 (file)
index 0000000..554763b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
new file mode 100644 (file)
index 0000000..3261420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
new file mode 100644 (file)
index 0000000..2dcaf33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
new file mode 100644 (file)
index 0000000..f0820f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
new file mode 100644 (file)
index 0000000..e278f56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
new file mode 100644 (file)
index 0000000..29d5ef2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
new file mode 100644 (file)
index 0000000..cde780f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
new file mode 100644 (file)
index 0000000..897b257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[      \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[      \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
new file mode 100644 (file)
index 0000000..b99545e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
new file mode 100644 (file)
index 0000000..a252e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
new file mode 100644 (file)
index 0000000..19ecbd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
new file mode 100644 (file)
index 0000000..6a7d4f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
new file mode 100644 (file)
index 0000000..8559b6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
new file mode 100644 (file)
index 0000000..016eaee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
new file mode 100644 (file)
index 0000000..1717a3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
new file mode 100644 (file)
index 0000000..2ab88bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
new file mode 100644 (file)
index 0000000..feab950
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x2_t arg1_poly8x16x2_t;
+
+  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
new file mode 100644 (file)
index 0000000..294cb21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
new file mode 100644 (file)
index 0000000..9c1bb52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
new file mode 100644 (file)
index 0000000..d473ed2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x2_t arg1_int8x16x2_t;
+
+  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
new file mode 100644 (file)
index 0000000..d74e55d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
new file mode 100644 (file)
index 0000000..d669db2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
new file mode 100644 (file)
index 0000000..82065a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x2_t arg1_uint8x16x2_t;
+
+  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
new file mode 100644 (file)
index 0000000..69d381c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
new file mode 100644 (file)
index 0000000..83fc0fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
new file mode 100644 (file)
index 0000000..ec22388
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
new file mode 100644 (file)
index 0000000..881fbdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
new file mode 100644 (file)
index 0000000..bc928e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
new file mode 100644 (file)
index 0000000..0a05595
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
new file mode 100644 (file)
index 0000000..b1af8ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
new file mode 100644 (file)
index 0000000..ed03bb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
new file mode 100644 (file)
index 0000000..c6c9e14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
new file mode 100644 (file)
index 0000000..e96f78a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
new file mode 100644 (file)
index 0000000..b5af7c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
new file mode 100644 (file)
index 0000000..adb0f70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst2p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x2_t arg1_poly64x1x2_t;
+
+  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
new file mode 100644 (file)
index 0000000..5dee019
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
new file mode 100644 (file)
index 0000000..f640c13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
new file mode 100644 (file)
index 0000000..b2f6ea1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
new file mode 100644 (file)
index 0000000..c88de13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x2_t arg1_int64x1x2_t;
+
+  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
new file mode 100644 (file)
index 0000000..8b7b28d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
new file mode 100644 (file)
index 0000000..9a93b6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
new file mode 100644 (file)
index 0000000..1c8a79d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
new file mode 100644 (file)
index 0000000..7f1539f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x2_t arg1_uint64x1x2_t;
+
+  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
new file mode 100644 (file)
index 0000000..e076239
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
new file mode 100644 (file)
index 0000000..1bd77cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
new file mode 100644 (file)
index 0000000..4626631
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
new file mode 100644 (file)
index 0000000..92c46b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
new file mode 100644 (file)
index 0000000..55190b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
new file mode 100644 (file)
index 0000000..f7a455b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
new file mode 100644 (file)
index 0000000..c91ca46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
new file mode 100644 (file)
index 0000000..2b70996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
new file mode 100644 (file)
index 0000000..969120f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
new file mode 100644 (file)
index 0000000..6f89617
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x3_t arg1_poly8x16x3_t;
+
+  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
new file mode 100644 (file)
index 0000000..872c203
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
new file mode 100644 (file)
index 0000000..4040809
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
new file mode 100644 (file)
index 0000000..ff0d713
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x3_t arg1_int8x16x3_t;
+
+  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
new file mode 100644 (file)
index 0000000..4e45ec9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
new file mode 100644 (file)
index 0000000..b1bbdc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
new file mode 100644 (file)
index 0000000..ccd3b05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x3_t arg1_uint8x16x3_t;
+
+  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
new file mode 100644 (file)
index 0000000..820f196
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
new file mode 100644 (file)
index 0000000..c7db5b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
new file mode 100644 (file)
index 0000000..5732440
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
new file mode 100644 (file)
index 0000000..364f1c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
new file mode 100644 (file)
index 0000000..d48c582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
new file mode 100644 (file)
index 0000000..9bee542
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
new file mode 100644 (file)
index 0000000..c5460d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
new file mode 100644 (file)
index 0000000..1180d1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
new file mode 100644 (file)
index 0000000..006877f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
new file mode 100644 (file)
index 0000000..dcca538
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
new file mode 100644 (file)
index 0000000..769bddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
new file mode 100644 (file)
index 0000000..d0f249c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst3p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x3_t arg1_poly64x1x3_t;
+
+  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
new file mode 100644 (file)
index 0000000..cfdb74c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
new file mode 100644 (file)
index 0000000..e4e0303
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
new file mode 100644 (file)
index 0000000..11389c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
new file mode 100644 (file)
index 0000000..79b5fca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x3_t arg1_int64x1x3_t;
+
+  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
new file mode 100644 (file)
index 0000000..7943f53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
new file mode 100644 (file)
index 0000000..73a0fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
new file mode 100644 (file)
index 0000000..902099b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
new file mode 100644 (file)
index 0000000..49cbd32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x3_t arg1_uint64x1x3_t;
+
+  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
new file mode 100644 (file)
index 0000000..2903877
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
new file mode 100644 (file)
index 0000000..40ef724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
new file mode 100644 (file)
index 0000000..374dcf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
new file mode 100644 (file)
index 0000000..2867706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
new file mode 100644 (file)
index 0000000..375535d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
new file mode 100644 (file)
index 0000000..147a62a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
new file mode 100644 (file)
index 0000000..7974114
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
new file mode 100644 (file)
index 0000000..77f1a52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
new file mode 100644 (file)
index 0000000..20c8a4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
new file mode 100644 (file)
index 0000000..ac01896
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x4_t arg1_poly8x16x4_t;
+
+  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
new file mode 100644 (file)
index 0000000..43a3d64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
new file mode 100644 (file)
index 0000000..1603e94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
new file mode 100644 (file)
index 0000000..b5fe672
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x4_t arg1_int8x16x4_t;
+
+  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
new file mode 100644 (file)
index 0000000..d5edab6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
new file mode 100644 (file)
index 0000000..c47da4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
new file mode 100644 (file)
index 0000000..4ee3460
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x4_t arg1_uint8x16x4_t;
+
+  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
new file mode 100644 (file)
index 0000000..15fb232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
new file mode 100644 (file)
index 0000000..2c6d372
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
new file mode 100644 (file)
index 0000000..088dec9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
new file mode 100644 (file)
index 0000000..c5d5868
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
new file mode 100644 (file)
index 0000000..7a2655d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
new file mode 100644 (file)
index 0000000..1094044
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
new file mode 100644 (file)
index 0000000..8597c41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
new file mode 100644 (file)
index 0000000..e911fff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
new file mode 100644 (file)
index 0000000..0f8c131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
new file mode 100644 (file)
index 0000000..bf061b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
new file mode 100644 (file)
index 0000000..0877c3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
new file mode 100644 (file)
index 0000000..020bb42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst4p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x4_t arg1_poly64x1x4_t;
+
+  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
new file mode 100644 (file)
index 0000000..371705e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
new file mode 100644 (file)
index 0000000..112073c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
new file mode 100644 (file)
index 0000000..4e2cbf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
new file mode 100644 (file)
index 0000000..b1a839a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x4_t arg1_int64x1x4_t;
+
+  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
new file mode 100644 (file)
index 0000000..9d02dba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
new file mode 100644 (file)
index 0000000..434aacb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
new file mode 100644 (file)
index 0000000..4e234d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
new file mode 100644 (file)
index 0000000..225fe7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x4_t arg1_uint64x1x4_t;
+
+  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[     \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
new file mode 100644 (file)
index 0000000..e19cb6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[      \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[       \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
new file mode 100644 (file)
index 0000000..903b43c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
new file mode 100644 (file)
index 0000000..553c9a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
new file mode 100644 (file)
index 0000000..c59d4a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
new file mode 100644 (file)
index 0000000..c2034c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
new file mode 100644 (file)
index 0000000..2b08427
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
new file mode 100644 (file)
index 0000000..e15ecae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
new file mode 100644 (file)
index 0000000..3836901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
new file mode 100644 (file)
index 0000000..e403652
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
new file mode 100644 (file)
index 0000000..4290f48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
new file mode 100644 (file)
index 0000000..4f2f3be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
new file mode 100644 (file)
index 0000000..2721297
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
new file mode 100644 (file)
index 0000000..40d4ffd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
new file mode 100644 (file)
index 0000000..de5b431
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
new file mode 100644 (file)
index 0000000..86ca09a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
new file mode 100644 (file)
index 0000000..7b99f51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
new file mode 100644 (file)
index 0000000..0198b1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[  \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
new file mode 100644 (file)
index 0000000..754d1d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
new file mode 100644 (file)
index 0000000..183e61f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
new file mode 100644 (file)
index 0000000..1f9e939
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
new file mode 100644 (file)
index 0000000..51afdb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u16\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
new file mode 100644 (file)
index 0000000..459f31a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u32\[   \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
new file mode 100644 (file)
index 0000000..5db4319
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u8\[    \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
new file mode 100644 (file)
index 0000000..89618e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
new file mode 100644 (file)
index 0000000..bbe713c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
new file mode 100644 (file)
index 0000000..46694c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
@@ -0,0 +1,19 @@
+/* Test the `vsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
new file mode 100644 (file)
index 0000000..75d990f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
new file mode 100644 (file)
index 0000000..2262e39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
new file mode 100644 (file)
index 0000000..4b651ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[    \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
new file mode 100644 (file)
index 0000000..55581f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
@@ -0,0 +1,19 @@
+/* Test the `vsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
new file mode 100644 (file)
index 0000000..e293de2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
new file mode 100644 (file)
index 0000000..8eab8af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
new file mode 100644 (file)
index 0000000..514ec75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
new file mode 100644 (file)
index 0000000..86a0ecf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
new file mode 100644 (file)
index 0000000..7c48f40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u16\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
new file mode 100644 (file)
index 0000000..3137ec6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
new file mode 100644 (file)
index 0000000..7e40d00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u8\[    \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
new file mode 100644 (file)
index 0000000..52127ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
new file mode 100644 (file)
index 0000000..a155244
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
new file mode 100644 (file)
index 0000000..5a71ed7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
new file mode 100644 (file)
index 0000000..e367dbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x2_t arg0_poly8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
new file mode 100644 (file)
index 0000000..5cf2224
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x2_t arg0_int8x8x2_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
new file mode 100644 (file)
index 0000000..680e930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x2_t arg0_uint8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
new file mode 100644 (file)
index 0000000..2a534d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x3_t arg0_poly8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
new file mode 100644 (file)
index 0000000..aaa9136
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x3_t arg0_int8x8x3_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
new file mode 100644 (file)
index 0000000..7edd405
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x3_t arg0_uint8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
new file mode 100644 (file)
index 0000000..e1469fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x4_t arg0_poly8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
new file mode 100644 (file)
index 0000000..5bb966b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x4_t arg0_int8x8x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
new file mode 100644 (file)
index 0000000..6b3d914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x4_t arg0_uint8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
new file mode 100644 (file)
index 0000000..abac252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
new file mode 100644 (file)
index 0000000..93ee371
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
new file mode 100644 (file)
index 0000000..91e52a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[    \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
new file mode 100644 (file)
index 0000000..65b0435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
new file mode 100644 (file)
index 0000000..7209bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
new file mode 100644 (file)
index 0000000..12f86b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
new file mode 100644 (file)
index 0000000..4acbb55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
new file mode 100644 (file)
index 0000000..b7f7b7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
new file mode 100644 (file)
index 0000000..57f8d64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
new file mode 100644 (file)
index 0000000..0880c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
new file mode 100644 (file)
index 0000000..9f24dee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
new file mode 100644 (file)
index 0000000..4c15ffa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[      \]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[     \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
new file mode 100644 (file)
index 0000000..5098097
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
new file mode 100644 (file)
index 0000000..6ae7f5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
new file mode 100644 (file)
index 0000000..2c0951a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
new file mode 100644 (file)
index 0000000..e9359f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
new file mode 100644 (file)
index 0000000..f19a386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
new file mode 100644 (file)
index 0000000..c5fba76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
new file mode 100644 (file)
index 0000000..4efaef0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
new file mode 100644 (file)
index 0000000..4df963d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
new file mode 100644 (file)
index 0000000..db21e83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
new file mode 100644 (file)
index 0000000..5f25d37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
new file mode 100644 (file)
index 0000000..a5d63f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
new file mode 100644 (file)
index 0000000..3d5ec4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
new file mode 100644 (file)
index 0000000..c37f4fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
new file mode 100644 (file)
index 0000000..707459f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
new file mode 100644 (file)
index 0000000..cfad251
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
new file mode 100644 (file)
index 0000000..8add51b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
new file mode 100644 (file)
index 0000000..de9fc55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
new file mode 100644 (file)
index 0000000..5dc63e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
new file mode 100644 (file)
index 0000000..97ef650
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
new file mode 100644 (file)
index 0000000..d8d6881
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
new file mode 100644 (file)
index 0000000..c9c212e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
new file mode 100644 (file)
index 0000000..a0f791d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
new file mode 100644 (file)
index 0000000..e1f3adc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
new file mode 100644 (file)
index 0000000..215be3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
new file mode 100644 (file)
index 0000000..74a5e59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
new file mode 100644 (file)
index 0000000..e23b719
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
new file mode 100644 (file)
index 0000000..2cac731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
new file mode 100644 (file)
index 0000000..c932fbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
new file mode 100644 (file)
index 0000000..a5acd67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
new file mode 100644 (file)
index 0000000..7869c08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
new file mode 100644 (file)
index 0000000..ca4b5ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
new file mode 100644 (file)
index 0000000..be18756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
new file mode 100644 (file)
index 0000000..4ea4c37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
new file mode 100644 (file)
index 0000000..b93fc3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
new file mode 100644 (file)
index 0000000..2ac259b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
new file mode 100644 (file)
index 0000000..81a69b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
new file mode 100644 (file)
index 0000000..173c30d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
new file mode 100644 (file)
index 0000000..0195009
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
new file mode 100644 (file)
index 0000000..e004a3f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
new file mode 100644 (file)
index 0000000..ed64aa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
new file mode 100644 (file)
index 0000000..b512247
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
new file mode 100644 (file)
index 0000000..067f43e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
new file mode 100644 (file)
index 0000000..01f3c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
new file mode 100644 (file)
index 0000000..b90b421
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
new file mode 100644 (file)
index 0000000..9f69fa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
new file mode 100644 (file)
index 0000000..3cc32cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
new file mode 100644 (file)
index 0000000..4a32e54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
new file mode 100644 (file)
index 0000000..c9e976d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
new file mode 100644 (file)
index 0000000..0998a8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
new file mode 100644 (file)
index 0000000..916c164
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
new file mode 100644 (file)
index 0000000..239e91d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
new file mode 100644 (file)
index 0000000..0687a8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
new file mode 100644 (file)
index 0000000..ff78c69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
new file mode 100644 (file)
index 0000000..079e23e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
new file mode 100644 (file)
index 0000000..842bf06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
new file mode 100644 (file)
index 0000000..fa9bc90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
new file mode 100644 (file)
index 0000000..1295832
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
new file mode 100644 (file)
index 0000000..af18fb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[     \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
new file mode 100644 (file)
index 0000000..fd72ce4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
new file mode 100644 (file)
index 0000000..72fc156
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
new file mode 100644 (file)
index 0000000..fda2705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
new file mode 100644 (file)
index 0000000..14a2af5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc/testsuite/gcc.target/arm/neon/vzips16.c
new file mode 100644 (file)
index 0000000..b47c3bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips16.c
@@ -0,0 +1,20 @@
+/* Test the `vzips16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc/testsuite/gcc.target/arm/neon/vzips32.c
new file mode 100644 (file)
index 0000000..8bb064d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips32.c
@@ -0,0 +1,20 @@
+/* Test the `vzips32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc/testsuite/gcc.target/arm/neon/vzips8.c
new file mode 100644 (file)
index 0000000..4e20646
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzips8.c
@@ -0,0 +1,20 @@
+/* Test the `vzips8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
new file mode 100644 (file)
index 0000000..ce8fe44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
new file mode 100644 (file)
index 0000000..7667efc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[     \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */

diff --git a/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
new file mode 100644 (file)
index 0000000..1229103
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[      \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */