[ARM, x86] add tests to show possible improvement for bool math; NFC

llvm-svn: 299897

diff --git a/llvm/test/CodeGen/ARM/bool-ext-inc.ll b/llvm/test/CodeGen/ARM/bool-ext-inc.ll
new file mode 100644 (file)
index 0000000..fe43f1b
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/bool-ext-inc.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=neon | FileCheck %s
+
+define i32 @sext_inc(i1 zeroext %x) {
+; CHECK-LABEL: sext_inc:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    rsb r0, r0, #1
+; CHECK-NEXT:    mov pc, lr
+  %ext = sext i1 %x to i32
+  %add = add i32 %ext, 1
+  ret i32 %add
+}
+
+define <4 x i32> @sext_inc_vec(<4 x i1> %x) {
+; CHECK-LABEL: sext_inc_vec:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vmov.i32 q9, #0x1f
+; CHECK-NEXT:    vmov.i32 q10, #0x1
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vneg.s32 q9, q9
+; CHECK-NEXT:    vshl.i32 q8, q8, #31
+; CHECK-NEXT:    vshl.s32 q8, q8, q9
+; CHECK-NEXT:    vadd.i32 q8, q8, q10
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
+; CHECK-NEXT:    mov pc, lr
+  %ext = sext <4 x i1> %x to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
+

diff --git a/llvm/test/CodeGen/X86/bool-ext-inc.ll b/llvm/test/CodeGen/X86/bool-ext-inc.ll
new file mode 100644 (file)
index 0000000..d0967c1
--- /dev/null
+++ b/llvm/test/CodeGen/X86/bool-ext-inc.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+; FIXME: add (sext i1 X), 1 -> zext (not i1 X)
+
+define i32 @sext_inc(i1 zeroext %x) nounwind {
+; CHECK-LABEL: sext_inc:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movzbl %dil, %ecx
+; CHECK-NEXT:    movl $1, %eax
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %ext = sext i1 %x to i32
+  %add = add i32 %ext, 1
+  ret i32 %add
+}
+
+; FIXME: add (sext i1 X), 1 -> zext (not i1 X)
+
+define <4 x i32> @sext_inc_vec(<4 x i1> %x) nounwind {
+; CHECK-LABEL: sext_inc_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pslld $31, %xmm0
+; CHECK-NEXT:    psrad $31, %xmm0
+; CHECK-NEXT:    paddd {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    retq
+  %ext = sext <4 x i1> %x to <4 x i32>
+  %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add
+}
+
+