}
vec4_generator g(brw->intelScreen->compiler, brw,
- prog, &vp->Base, &prog_data->base,
+ &prog_data->base,
mem_ctx, INTEL_DEBUG & DEBUG_VS, "vertex", "VS");
- assembly = g.generate_assembly(v.cfg, final_assembly_size);
+ assembly = g.generate_assembly(v.cfg, final_assembly_size, vp->Base.nir);
}
return assembly;
{
public:
vec4_generator(const struct brw_compiler *compiler, void *log_data,
- struct gl_shader_program *shader_prog,
- struct gl_program *prog,
struct brw_vue_prog_data *prog_data,
void *mem_ctx,
bool debug_flag,
const char *stage_abbrev);
~vec4_generator();
- const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
+ const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size,
+ const nir_shader *nir);
private:
- void generate_code(const cfg_t *cfg);
+ void generate_code(const cfg_t *cfg, const nir_shader *nir);
void generate_math1_gen4(vec4_instruction *inst,
struct brw_reg dst,
struct brw_codegen *p;
- struct gl_shader_program *shader_prog;
- const struct gl_program *prog;
-
struct brw_vue_prog_data *prog_data;
void *mem_ctx;
*/
#include <ctype.h>
+#include "glsl/glsl_parser_extras.h"
#include "brw_vec4.h"
#include "brw_cfg.h"
vec4_generator::vec4_generator(const struct brw_compiler *compiler,
void *log_data,
- struct gl_shader_program *shader_prog,
- struct gl_program *prog,
struct brw_vue_prog_data *prog_data,
void *mem_ctx,
bool debug_flag,
const char *stage_name,
const char *stage_abbrev)
: compiler(compiler), log_data(log_data), devinfo(compiler->devinfo),
- shader_prog(shader_prog), prog(prog), prog_data(prog_data),
+ prog_data(prog_data),
mem_ctx(mem_ctx), stage_name(stage_name), stage_abbrev(stage_abbrev),
debug_flag(debug_flag)
{
}
void
-vec4_generator::generate_code(const cfg_t *cfg)
+vec4_generator::generate_code(const cfg_t *cfg, const nir_shader *nir)
{
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
int after_size = p->next_insn_offset;
if (unlikely(debug_flag)) {
- if (shader_prog) {
- fprintf(stderr, "Native code for %s %s shader %d:\n",
- shader_prog->Label ? shader_prog->Label : "unnamed",
- stage_name, shader_prog->Name);
- } else {
- fprintf(stderr, "Native code for %s program %d:\n", stage_name,
- prog->Id);
- }
+ fprintf(stderr, "Native code for %s %s shader %s:\n",
+ nir->info.label ? nir->info.label : "unnamed",
+ _mesa_shader_stage_to_string(nir->stage), nir->info.name);
+
fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. Compacted %d to %d"
" bytes (%.0f%%)\n",
stage_abbrev,
const unsigned *
vec4_generator::generate_assembly(const cfg_t *cfg,
- unsigned *assembly_size)
+ unsigned *assembly_size,
+ const nir_shader *nir)
{
brw_set_default_access_mode(p, BRW_ALIGN_16);
- generate_code(cfg);
+ generate_code(cfg, nir);
return brw_get_program(p, assembly_size);
}
static const unsigned *
generate_assembly(struct brw_context *brw,
- struct gl_shader_program *shader_prog,
- struct gl_program *prog,
+ const nir_shader *nir,
struct brw_vue_prog_data *prog_data,
void *mem_ctx,
const cfg_t *cfg,
unsigned *final_assembly_size)
{
vec4_generator g(brw->intelScreen->compiler, brw,
- shader_prog, prog, prog_data, mem_ctx,
+ prog_data, mem_ctx,
INTEL_DEBUG & DEBUG_GS, "geometry", "GS");
- return g.generate_assembly(cfg, final_assembly_size);
+ return g.generate_assembly(cfg, final_assembly_size, nir);
}
extern "C" const unsigned *
c, shader->Program->nir,
mem_ctx, true /* no_spills */, shader_time_index);
if (v.run()) {
- return generate_assembly(brw, prog, &c->gp->program.Base,
+ return generate_assembly(brw, shader->Program->nir,
&c->prog_data.base, mem_ctx, v.cfg,
final_assembly_size);
}
prog->LinkStatus = false;
ralloc_strcat(&prog->InfoLog, gs->fail_msg);
} else {
- ret = generate_assembly(brw, prog, &c->gp->program.Base,
+ ret = generate_assembly(brw, shader->Program->nir,
&c->prog_data.base, mem_ctx, gs->cfg,
final_assembly_size);
}