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arm64: dts: qcom: sc8180x: switch PCIe QMP PHY to new style of bindings
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sun, 20 Aug 2023 14:20:29 +0000 (17:20 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 25 Jan 2024 23:35:28 +0000 (15:35 -0800)
[ Upstream commit a6546460ca439bade19d64eb63cee2d97c29fb72 ]

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes). While we are at it, rename PHY
nodes to `phy@`.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-13-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stable-dep-of: 78403b37f677 ("arm64: dts: qcom: sc8180x: Fix up PCIe nodes")
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/qcom/sc8180x.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 0d85bde..dfaeb33 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1749,24 +1749,29 @@
                                        <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
                        interconnect-names = "pcie-mem", "cpu-pcie";
 
-                       phys = <&pcie0_lane>;
+                       phys = <&pcie0_phy>;
                        phy-names = "pciephy";
                        dma-coherent;
 
                        status = "disabled";
                };
 
-               pcie0_phy: phy-wrapper@1c06000 {
+               pcie0_phy: phy@1c06000 {
                        compatible = "qcom,sc8180x-qmp-pcie-phy";
-                       reg = <0 0x1c06000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c06000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_0_CLKREF_CLK>,
-                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_0_pipe_clk";
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_0_PHY_BCR>;
                        reset-names = "phy";
@@ -1775,21 +1780,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie0_lane: phy@1c06200 {
-                               reg = <0 0x1c06200 0 0x170>, /* tx0 */
-                                     <0 0x1c06400 0 0x200>, /* rx0 */
-                                     <0 0x1c06a00 0 0x1f0>, /* pcs */
-                                     <0 0x1c06600 0 0x170>, /* tx1 */
-                                     <0 0x1c06800 0 0x200>, /* rx1 */
-                                     <0 0x1c06e00 0 0xf4>; /* pcs_com */
-                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #clock-cells = <0>;
-                               clock-output-names = "pcie_0_pipe_clk";
-                               #phy-cells = <0>;
-                       };
                };
 
                pcie3: pci@1c08000 {
@@ -1857,24 +1847,30 @@
                                        <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
                        interconnect-names = "pcie-mem", "cpu-pcie";
 
-                       phys = <&pcie3_lane>;
+                       phys = <&pcie3_phy>;
                        phy-names = "pciephy";
                        dma-coherent;
 
                        status = "disabled";
                };
 
-               pcie3_phy: phy-wrapper@1c0c000 {
+               pcie3_phy: phy@1c0c000 {
                        compatible = "qcom,sc8180x-qmp-pcie-phy";
-                       reg = <0 0x1c0c000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c0c000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_3_CLKREF_CLK>,
-                                <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_3_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_3_pipe_clk";
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_3_PHY_BCR>;
                        reset-names = "phy";
@@ -1883,21 +1879,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie3_lane: phy@1c0c200 {
-                               reg = <0 0x1c0c200 0 0x170>, /* tx0 */
-                                     <0 0x1c0c400 0 0x200>, /* rx0 */
-                                     <0 0x1c0ca00 0 0x1f0>, /* pcs */
-                                     <0 0x1c0c600 0 0x170>, /* tx1 */
-                                     <0 0x1c0c800 0 0x200>, /* rx1 */
-                                     <0 0x1c0ce00 0 0xf4>; /* pcs_com */
-                               clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #clock-cells = <0>;
-                               clock-output-names = "pcie_3_pipe_clk";
-                               #phy-cells = <0>;
-                       };
                };
 
                pcie1: pci@1c10000 {
@@ -1965,24 +1946,30 @@
                                        <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
                        interconnect-names = "pcie-mem", "cpu-pcie";
 
-                       phys = <&pcie1_lane>;
+                       phys = <&pcie1_phy>;
                        phy-names = "pciephy";
                        dma-coherent;
 
                        status = "disabled";
                };
 
-               pcie1_phy: phy-wrapper@1c16000 {
+               pcie1_phy: phy@1c16000 {
                        compatible = "qcom,sc8180x-qmp-pcie-phy";
-                       reg = <0 0x1c16000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c16000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_1_CLKREF_CLK>,
-                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_1_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_1_pipe_clk";
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_1_PHY_BCR>;
                        reset-names = "phy";
@@ -1991,21 +1978,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie1_lane: phy@1c0e200 {
-                               reg = <0 0x1c16200 0 0x170>, /* tx0 */
-                                     <0 0x1c16400 0 0x200>, /* rx0 */
-                                     <0 0x1c16a00 0 0x1f0>, /* pcs */
-                                     <0 0x1c16600 0 0x170>, /* tx1 */
-                                     <0 0x1c16800 0 0x200>, /* rx1 */
-                                     <0 0x1c16e00 0 0xf4>; /* pcs_com */
-                               clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               #clock-cells = <0>;
-                               clock-output-names = "pcie_1_pipe_clk";
-
-                               #phy-cells = <0>;
-                       };
                };
 
                pcie2: pci@1c18000 {
@@ -2073,24 +2045,30 @@
                                        <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
                        interconnect-names = "pcie-mem", "cpu-pcie";
 
-                       phys = <&pcie2_lane>;
+                       phys = <&pcie2_phy>;
                        phy-names = "pciephy";
                        dma-coherent;
 
                        status = "disabled";
                };
 
-               pcie2_phy: phy-wrapper@1c1c000 {
+               pcie2_phy: phy@1c1c000 {
                        compatible = "qcom,sc8180x-qmp-pcie-phy";
-                       reg = <0 0x1c1c000 0 0x1c0>;
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
+                       reg = <0 0x01c1c000 0 0x1000>;
                        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                                 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
                                 <&gcc GCC_PCIE_2_CLKREF_CLK>,
-                                <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
-                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+                                <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+                                <&gcc GCC_PCIE_2_PIPE_CLK>;
+                       clock-names = "aux",
+                                     "cfg_ahb",
+                                     "ref",
+                                     "refgen",
+                                     "pipe";
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_3_pipe_clk";
+
+                       #phy-cells = <0>;
 
                        resets = <&gcc GCC_PCIE_2_PHY_BCR>;
                        reset-names = "phy";
@@ -2099,22 +2077,6 @@
                        assigned-clock-rates = <100000000>;
 
                        status = "disabled";
-
-                       pcie2_lane: phy@1c0e200 {
-                               reg = <0 0x1c1c200 0 0x170>, /* tx0 */
-                                     <0 0x1c1c400 0 0x200>, /* rx0 */
-                                     <0 0x1c1ca00 0 0x1f0>, /* pcs */
-                                     <0 0x1c1c600 0 0x170>, /* tx1 */
-                                     <0 0x1c1c800 0 0x200>, /* rx1 */
-                                     <0 0x1c1ce00 0 0xf4>; /* pcs_com */
-                               clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
-                               clock-names = "pipe0";
-
-                               #clock-cells = <0>;
-                               clock-output-names = "pcie_2_pipe_clk";
-
-                               #phy-cells = <0>;
-                       };
                };
 
                ufs_mem_hc: ufshc@1d84000 {
Domain: System / Kernel;