static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Remove the clamps on the CPU I/O signals */
static void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
static void enable_cpu_power_rail(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
static const struct gpio_bank gpio_bank_am33xx[4] = {
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#endif
-#ifdef CONFIG_SPL_BUILD
-/* Initialize timer */
-static void init_timer(void)
-{
- /* Reset the Timer */
- writel(0x2, (&timer_base->tscir));
-
- /* Wait until the reset is done */
- while (readl(&timer_base->tiocp_cfg) & 1)
- ;
-
- /* Start the Timer */
- writel(0x1, (&timer_base->tclr));
-}
-#endif
-
/*
* Determine what type of DDR we have.
*/
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
- /* Initialize the Timer */
- init_timer();
-
preloader_console_init();
/* Initalize the board header */
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
puts("Entering RCM...\n");
udelay(50000);
/* UTMIP High Speed Sync Start Delay */
static const u8 utmip_hs_sync_start_delay = 9;
-/* Put the port into host mode (this only works for OTG ports) */
+/* Put the port into host mode */
static void set_host_mode(struct fdt_usb *config)
{
- if (config->dr_mode == DR_MODE_OTG) {
- /* Check whether remote host from USB1 is driving VBus */
- if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
- return;
-
- /*
- * If not driving, we set the GPIO to enable VBUS. We assume
- * that the pinmux is set up correctly for this.
- */
- if (fdt_gpio_isvalid(&config->vbus_gpio)) {
- fdtdec_setup_gpio(&config->vbus_gpio);
- gpio_direction_output(config->vbus_gpio.gpio, 1);
- debug("set_host_mode: GPIO %d high\n",
- config->vbus_gpio.gpio);
- }
+ /*
+ * If we are an OTG port, check if remote host is driving VBus and
+ * bail out in this case.
+ */
+ if (config->dr_mode == DR_MODE_OTG &&
+ (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
+ return;
+
+ /*
+ * If not driving, we set the GPIO to enable VBUS. We assume
+ * that the pinmux is set up correctly for this.
+ */
+ if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+ fdtdec_setup_gpio(&config->vbus_gpio);
+ gpio_direction_output(config->vbus_gpio.gpio,
+ (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+ 0 : 1);
+ debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
+ (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+ "low" : "high");
}
}
SOBJS += lowlevel_init.o
COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
int tegra_get_chip_type(void)
{
struct apb_misc_gp_ctlr *gp;
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
uint tegra_sku_id, rev;
/*
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
* Tegra30
*/
- gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
tegra_sku_id = readl(&fuse->sku_info) & 0xff;
static void init_pmc_scratch(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 odmdata;
int i;
unsigned int query_sdram_size(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_scratch20);
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA20_UARTA_GPU)
+#elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
uart_ids |= UARTA;
#endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTB
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
uart_ids |= UARTB;
#endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTD
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
uart_ids |= UARTD;
#endif
setup_uarts(uart_ids);
}
break;
+ case PERIPH_ID_NDFLASH:
+ if (config == FUNCMUX_NDFLASH_ATC) {
+ pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
+ pinmux_tristate_disable(PINGRP_ATC);
+ }
+ break;
+
default:
debug("%s: invalid periph_id %d", __func__, id);
return -1;
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
#endif
/*
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
union scratch2_reg scratch2;
union scratch4_reg scratch4;
{
u32 major_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
HIDREV_MAJORPREV_SHIFT;
static int ap20_is_odm_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (!is_failure_analysis_mode(fuse) &&
is_odm_production_mode_fuse_set(fuse))
static int ap20_is_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (get_major_version() == 0)
return 1;
{
u32 chip_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
HIDREV_CHIPID_SHIFT;
void wb_start(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
};
+
+ nand: nand-controller@70008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ };
};
};
/* Few Register Offsets */
-#define FRAME_MODE_SHIFT 1
#define TFTSTN_SHIFT 3
#define DATALINES_SHIFT 8
void *frame_buffer;
};
+#define DSS_HBP(bp) (((bp) - 1) << 20)
+#define DSS_HFP(fp) (((fp) - 1) << 8)
+#define DSS_HSW(sw) ((sw) - 1)
+#define DSS_VBP(bp) ((bp) << 20)
+#define DSS_VFP(fp) ((fp) << 8)
+#define DSS_VSW(sw) ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width);
#define CONTROL_PADCONF_GPIO128 0x0A58
#define CONTROL_PADCONF_GPIO129 0x0A5A
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
+
#define MUX_VAL(OFFSET,VALUE)\
writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-/* Start up the tegra20 SOC */
-void tegra20_start(void);
-
/* This is the main entry into U-Boot, used by the Cortex-A9 */
extern void _start(void);
/* Serial Flash configs */
FUNCMUX_SPI1_GMC_GMD = 0,
+
+ /* NAND flags */
+ FUNCMUX_NDFLASH_ATC = 0,
};
/**
* MA 02111-1307 USA
*/
-#ifndef _TEGRA20_MMC_H_
-#define _TEGRA20_MMC_H_
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
-#endif /* TEGRA20_MMC_H_ */
+#endif /* _TEGRA_MMC_H_ */
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-struct tegra20_sysinfo {
+struct tegra_sysinfo {
char *board_string;
};
void invalidate_dcache(void);
-extern const struct tegra20_sysinfo sysinfo;
+extern const struct tegra_sysinfo sysinfo;
#endif
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
-#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
#define TEGRA_USB1_BASE 0xC5000000
#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE
+#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
};
#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL TEGRA20_PMC_BASE
+#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
#endif /* TEGRA20_H */
#ifndef __TEGRA_MMC_H_
#define __TEGRA_MMC_H_
-#define TEGRA20_SDMMC1_BASE 0xC8000000
-#define TEGRA20_SDMMC2_BASE 0xC8000200
-#define TEGRA20_SDMMC3_BASE 0xC8000400
-#define TEGRA20_SDMMC4_BASE 0xC8000600
+#define TEGRA_SDMMC1_BASE 0xC8000000
+#define TEGRA_SDMMC2_BASE 0xC8000200
+#define TEGRA_SDMMC3_BASE 0xC8000400
+#define TEGRA_SDMMC4_BASE 0xC8000600
#ifndef __ASSEMBLY__
-struct tegra20_mmc {
+struct tegra_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
struct mmc_host {
- struct tegra20_mmc *reg;
+ struct tegra_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_TIMEOUT 1000
-#define TEGRA20_SPI_MAX_FREQ 52000000
+#define TEGRA_SPI_MAX_FREQ 52000000
#endif /* _TEGRA_SPI_H_ */
/* Tegra20 timer functions */
-#ifndef _TEGRA20_TIMER_H
-#define _TEGRA20_TIMER_H
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
fdtdec_check_fdt,
#endif
timer_init, /* initialize timer */
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+ board_postclk_init,
+#endif
#ifdef CONFIG_FSL_ESDHC
get_clocks,
#endif
display_height = 256;
printf("%ld x %ld pixel matrix\n", display_width, display_height);
- /* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */
- csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
- AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+ /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */
+ csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+ AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[2]);
csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
/* NAND flash on D16 */
csa |= AT91_MATRIX_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
writel(csa, &matrix->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
pin_mux_mmc();
/* init dev 0, SD slot, with 4-bit bus */
- tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
return 0;
}
usb@c5004000 {
status = "disabled";
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
};
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra20_mmc_init(0, 4, -1, -1);
+ tegra_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 3, SD slot, with 4-bit bus */
- tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
+ tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
return 0;
}
pin_mux_mmc();
/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
- tegra20_mmc_init(0, 4, -1, GPIO_PP1);
+ tegra_mmc_init(0, 4, -1, GPIO_PP1);
/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
- tegra20_mmc_init(3, 4, -1, -1);
+ tegra_mmc_init(3, 4, -1, -1);
return 0;
}
DECLARE_GLOBAL_DATA_PTR;
-const struct tegra20_sysinfo sysinfo = {
- CONFIG_TEGRA20_BOARD_STRING
+const struct tegra_sysinfo sysinfo = {
+ CONFIG_TEGRA_BOARD_STRING
};
#ifndef CONFIG_SPL_BUILD
static void power_det_init(void)
{
#if defined(CONFIG_TEGRA20)
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
/* turn off power detects */
writel(0, &pmc->pmc_pwr_det_latch);
board_usb_init(gd->fdt_blob);
#endif
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
usb@c5004000 {
status = "disabled";
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
};
0x1f04008a>;
linux,fn-keymap = <0x05040002>;
};
+
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
};
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
debug("board_mmc_init: init SD slot J26\n");
/* init dev 0, SD slot J26, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+ tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
debug("board_mmc_init: init SD slot J5\n");
/* init dev 2, SD slot J5, with 4-bit bus */
- tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+ tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
return 0;
}
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
debug("board_mmc_init: init eMMC\n");
/* init dev 0, eMMC chip, with 4-bit bus */
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
- tegra20_mmc_init(0, 4, -1, -1);
+ tegra_mmc_init(0, 4, -1, -1);
debug("board_mmc_init: init SD slot\n");
/* init dev 1, SD slot, with 4-bit bus */
- tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+ tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
return 0;
}
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../seaboard)
-endif
+$(shell mkdir -p $(obj)../seaboard)
LIB = $(obj)lib$(BOARD).o
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
pin_mux_mmc();
/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
- tegra20_mmc_init(0, 8, -1, -1);
+ tegra_mmc_init(0, 8, -1, -1);
/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
- tegra20_mmc_init(1, 8, -1, -1);
+ tegra_mmc_init(1, 8, -1, -1);
return 0;
}
return 0;
}
-int board_init(void)
+int board_postclk_init(void)
{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ /*
+ * Initialize the serial interface here, because be need a running
+ * timer to set PC9 to high and wait for some time to enable the
+ * level converter of the RS232 interface on the PortuxG20 board.
+ */
- /* Enable the serial interface */
+#ifdef CONFIG_PORTUXG20
at91_set_gpio_output(AT91_PIN_PC9, 1);
+ mdelay(1);
+#endif
at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
stamp9G20_nand_hw_init();
#ifdef CONFIG_MACB
stamp9G20_macb_hw_init();
int misc_init_r(void)
{
+ char *eth_addr;
+
dieid_num_r();
+ eth_addr = getenv("ethaddr");
+ if (eth_addr)
+ return 0;
+
+#ifndef CONFIG_SPL_BUILD
+ TAM3517_READ_MAC_FROM_EEPROM;
+#endif
+
return 0;
}
#include <common.h>
#include <netdev.h>
+#include <malloc.h>
#include <fpga.h>
+#include <video_fb.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clocks.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
+#define BUZZER 140
+#define SPEAKER 141
+
#ifndef CONFIG_FPGA
#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
#endif
#define FPGA_INIT 119
#define FPGA_DONE 154
+#define LCD_PWR 138
+#define LCD_PON_PIN 139
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct {
+ u32 xres;
+ u32 yres;
+} panel_resolution[] = {
+ { 480, 272 },
+ { 800, 480 }
+};
+
+static struct panel_config lcd_cfg[] = {
+ {
+ .timing_h = PANEL_TIMING_H(4, 8, 41),
+ .timing_v = PANEL_TIMING_V(2, 4, 10),
+ .pol_freq = 0x00000000, /* Pol Freq */
+ .divisor = 0x0001000d, /* 33Mhz Pixel Clock */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = 0,
+ },
+ {
+ .timing_h = PANEL_TIMING_H(20, 192, 4),
+ .timing_v = PANEL_TIMING_V(2, 20, 10),
+ .pol_freq = 0x00004000, /* Pol Freq */
+ .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = 0,
+ }
+};
+#endif
+
/* Timing definitions for FPGA */
static const u32 gpmc_fpga[] = {
FPGA_GPMC_CONFIG1,
mt_ventoux_init_fpga();
+ /* GPIO_140: speaker #mute */
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
+ /* GPIO_141: Buzz Hi */
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
+
+ /* Turning off the buzzer */
+ gpio_request(BUZZER, "BUZZER_MUTE");
+ gpio_request(SPEAKER, "SPEAKER");
+ gpio_direction_output(BUZZER, 0);
+ gpio_direction_output(SPEAKER, 0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ char *eth_addr;
+
+ dieid_num_r();
+
+ eth_addr = getenv("ethaddr");
+ if (eth_addr)
+ return 0;
+
+#ifndef CONFIG_SPL_BUILD
+ TAM3517_READ_MAC_FROM_EEPROM;
+#endif
return 0;
}
return omap_mmc_init(0, 0, 0);
}
#endif
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+int board_video_init(void)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ struct panel_config *panel = &lcd_cfg[0];
+ char *s;
+ u32 index = 0;
+
+ void *fb;
+
+ fb = (void *)0x88000000;
+
+ s = getenv("panel");
+ if (s) {
+ index = simple_strtoul(s, NULL, 10);
+ if (index < ARRAY_SIZE(lcd_cfg))
+ panel = &lcd_cfg[index];
+ else
+ return 0;
+ }
+
+ panel->frame_buffer = fb;
+ printf("Panel: %dx%d\n", panel_resolution[index].xres,
+ panel_resolution[index].yres);
+ panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
+ (panel_resolution[index].xres - 1);
+
+ gpio_request(LCD_PWR, "LCD Power");
+ gpio_request(LCD_PON_PIN, "LCD Pon");
+ gpio_direction_output(LCD_PWR, 0);
+ gpio_direction_output(LCD_PON_PIN, 1);
+
+
+ setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+ setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+ omap3_dss_panel_config(panel);
+ omap3_dss_enable();
+
+ return 0;
+}
+#endif
/*GPIO_62: FPGA_RESET */ \
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/ \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
+ /* GPIO_64*/ \
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
/* GPIO_126: CardDetect */\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ /*GPIO_128 */ \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
/* GPIO_138: LCD_ENVD */\
- MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
/* GPIO_139: LCD_PON */\
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
/* GPIO_119: FPGA_INIT */ \
\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- /* GPIO_140: speaker #mute */\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- /* GPIO_141: Buzz Hi */\
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
/*GPIO_152: Ignition Sense */ \
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) \
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
/*GPIO_153: Power Button Sense */ \
MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
/* GPIO_154: FPGA_DONE */ \
/* GPIO_150: USB status 1 */\
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
+ /* gpt9_pwm */\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
+ /* gpt10_pwm */\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
+ /* gpt8_pwm */\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
+ /* gpt11_pwm */\
\
MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
/*GPIO_163 : TS_PENIRQ*/ \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
/* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
+ /* GPIO94 */\
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
/* GPIO95: #Enable Output */\
- MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
/* GPIO 99: #SOM_PWR_OFF */\
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
/* GPIO_100: #power out */\
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
+ /* GPIO_102 */\
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
+ /* gpio_10 */\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
+ /* gpio_24 */\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
+ /* gpio_26 */\
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
+ /* gpio_29 */\
/* Die to Die */\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
a320evb arm arm920t - faraday a320
at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
-eb_cpux9k2 arm arm920t - BuS at91
+eb_cpux9k2 arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2
+eb_cpux9k2_ram arm arm920t eb_cpux9k2 BuS at91 eb_cpux9k2:RAMBOOT
cpuat91 arm arm920t cpuat91 eukrea at91 cpuat91
cpuat91_ram arm arm920t cpuat91 eukrea at91 cpuat91:RAMBOOT
mx1ads arm arm920t - - imx
last = off;
- datbuf = malloc(nand->writesize);
- oobbuf = malloc(nand->oobsize);
+ datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+ oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
if (!datbuf || !oobbuf) {
puts("No memory for page buffer\n");
return 1;
return -1;
}
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) {
+ if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ CONFIG_SYS_MMC_ENV_PART)) {
+ puts("MMC partition switch failed\n");
+ return -1;
+ }
+ }
+#endif
+
return 0;
}
+static void fini_mmc_for_env(struct mmc *mmc)
+{
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num)
+ mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
+ mmc->part_num);
+#endif
+}
+
#ifdef CONFIG_CMD_SAVEENV
static inline int write_env(struct mmc *mmc, unsigned long size,
unsigned long offset, const void *buffer)
char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
+ if (init_mmc_for_env(mmc))
return 1;
+ if (mmc_get_env_addr(mmc, &offset)) {
+ ret = 1;
+ goto fini;
+ }
+
res = (char *)&env_new->data;
len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
if (len < 0) {
error("Cannot export environment: errno = %d\n", errno);
- return 1;
+ ret = 1;
+ goto fini;
}
env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE);
printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV);
if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) {
puts("failed\n");
- return 1;
+ ret = 1;
+ goto fini;
}
puts("done\n");
- return 0;
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+ return ret;
}
#endif /* CONFIG_CMD_SAVEENV */
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
+ int ret;
- if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset))
- return set_default_env(NULL);
+ if (init_mmc_for_env(mmc)) {
+ ret = 1;
+ goto err;
+ }
- if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf))
- return set_default_env(NULL);
+ if (mmc_get_env_addr(mmc, &offset)) {
+ ret = 1;
+ goto fini;
+ }
+
+ if (read_env(mmc, CONFIG_ENV_SIZE, offset, buf)) {
+ ret = 1;
+ goto fini;
+ }
env_import(buf, 1);
+ ret = 0;
+
+fini:
+ fini_mmc_for_env(mmc);
+err:
+ if (ret)
+ set_default_env(NULL);
#endif
}
--- /dev/null
+NAND Flash
+----------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot. There should not be Linux-specific or U-Boot specific binding, just
+a binding that describes this hardware. But agreeing a binding in Linux in
+the absence of a driver may be beyond my powers.)
+
+The device node for a NAND flash device is as follows:
+
+Required properties :
+ - compatible : Should be "manufacturer,device", "nand-flash"
+
+This node should sit inside its controller.
+
+
+Nvidia NAND Controller
+----------------------
+
+The device node for a NAND flash controller is as follows:
+
+Optional properties:
+
+nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
+ phandle, parameter, flags
+nvidia,nand-width : bus width of the NAND device in bits
+
+ - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
+ Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+ TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+
+ MAX_TRP_TREA is:
+ non-EDO mode: Max(tRP, tREA) + 6ns
+ EDO mode: tRP timing
+
+The 'reg' property should provide the chip select used by the flash chip.
+
+
+Example
+-------
+
+nand-controller@0x70008000 {
+ compatible = "nvidia,tegra20-nand";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
+ nvidia,nand-width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+};
#include <asm/gpio.h>
enum {
- TEGRA20_CMD_INFO,
- TEGRA20_CMD_PORT,
- TEGRA20_CMD_OUTPUT,
- TEGRA20_CMD_INPUT,
+ TEGRA_CMD_INFO,
+ TEGRA_CMD_PORT,
+ TEGRA_CMD_OUTPUT,
+ TEGRA_CMD_INPUT,
};
static struct gpio_names {
return error;
}
-static int tegra20_i2c_write_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
- debug("tegra20_i2c_write_data: Error (%d) !!!\n", error);
+ debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
return error;
}
-static int tegra20_i2c_read_data(u32 addr, u8 *data, u32 len)
+static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len)
{
int error;
struct i2c_trans_info trans_info;
error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info);
if (error)
- debug("tegra20_i2c_read_data: Error (%d) !!!\n", error);
+ debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
return error;
}
debug("\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra20_i2c_write_data(chip << 1, buffer, len);
+ rc = tegra_i2c_write_data(chip << 1, buffer, len);
if (rc)
debug("i2c_write_data(): rc=%d\n", rc);
debug("inside i2c_read_data():\n");
/* Shift 7-bit address over for lower-level i2c functions */
- rc = tegra20_i2c_read_data(chip << 1, buffer, len);
+ rc = tegra_i2c_read_data(chip << 1, buffer, len);
if (rc) {
debug("i2c_read_data(): rc=%d\n", rc);
return rc;
LIB := $(obj)libinput.o
COBJS-$(CONFIG_I8042_KBD) += i8042.o
-COBJS-$(CONFIG_TEGRA20_KEYBOARD) += tegra-kbc.o
+COBJS-$(CONFIG_TEGRA_KEYBOARD) += tegra-kbc.o
ifdef CONFIG_PS2KBD
COBJS-y += keyboard.o pc_keyb.o
COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
}
/* store the partition info of emmc */
- if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT)
+ if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+ ext_csd[EXT_CSD_BOOT_MULT])
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
}
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include "tegra_mmc.h"
+#include <asm/arch/tegra_mmc.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
-static void tegra20_get_setup(struct mmc_host *host, int dev_index)
+static void tegra_get_setup(struct mmc_host *host, int dev_index)
{
- debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
+ debug("tegra_get_setup: dev_index = %d\n", dev_index);
switch (dev_index) {
case 1:
- host->base = TEGRA20_SDMMC3_BASE;
+ host->base = TEGRA_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
- host->base = TEGRA20_SDMMC2_BASE;
+ host->base = TEGRA_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
- host->base = TEGRA20_SDMMC1_BASE;
+ host->base = TEGRA_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
- host->base = TEGRA20_SDMMC4_BASE;
+ host->base = TEGRA_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
- host->reg = (struct tegra20_mmc *)host->base;
+ host->reg = (struct tegra_mmc *)host->base;
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
debug(" mmc_change_clock called\n");
/*
- * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
+ * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
* PLLP_OUT0
*/
if (clock == 0)
return 0;
}
-int tegra20_mmc_getcd(struct mmc *mmc)
+int tegra_mmc_getcd(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
- debug("tegra20_mmc_getcd called\n");
+ debug("tegra_mmc_getcd called\n");
if (host->cd_gpio >= 0)
return !gpio_get_value(host->cd_gpio);
return 1;
}
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
- debug(" tegra20_mmc_init: index %d, bus width %d "
+ debug(" tegra_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
- tegra20_get_setup(host, dev_index);
+ tegra_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
mmc = &mmc_dev[dev_index];
- sprintf(mmc->name, "Tegra20 SD/MMC");
+ sprintf(mmc->name, "Tegra SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
- mmc->getcd = tegra20_mmc_getcd;
+ mmc->getcd = tegra_mmc_getcd;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
- * clock and Tegra20 SDMMC divisors.
+ * clock and Tegra SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
+COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
endif
sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
- printk(KERN_INFO "Initialize PMECC params, cap: %d, sector: %d\n",
- cap, sector_size);
+ MTDDEBUG(MTD_DEBUG_LEVEL1,
+ "Initialize PMECC params, cap: %d, sector: %d\n",
+ cap, sector_size);
host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
+#include <common.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/types.h>
-#include <common.h>
#include <malloc.h>
#include <asm/errno.h>
#include <asm/io.h>
struct nand_chip *chip = mtd->priv;
if (!(chip->options & NAND_OWN_BUFFERS))
- chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+ chip->buffers = memalign(ARCH_DMA_MINALIGN,
+ sizeof(*chip->buffers));
if (!chip->buffers)
return -ENOMEM;
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
+#include <asm/errno.h>
+#include <asm-generic/gpio.h>
+#include <fdtdec.h>
+#include "tegra_nand.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NAND_CMD_TIMEOUT_MS 10
+
+#define SKIPPED_SPARE_BYTES 4
+
+/* ECC bytes to be generated for tag data */
+#define TAG_ECC_BYTES 4
+
+/* 64 byte oob block info for large page (== 2KB) device
+ *
+ * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
+ * Skipped bytes(4)
+ * Main area Ecc(36)
+ * Tag data(20)
+ * Tag data Ecc(4)
+ *
+ * Yaffs2 will use 16 tag bytes.
+ */
+static struct nand_ecclayout eccoob = {
+ .eccbytes = 36,
+ .eccpos = {
+ 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30,
+ 31, 32, 33, 34, 35, 36, 37, 38, 39,
+ },
+ .oobavail = 20,
+ .oobfree = {
+ {
+ .offset = 40,
+ .length = 20,
+ },
+ }
+};
+
+enum {
+ ECC_OK,
+ ECC_TAG_ERROR = 1 << 0,
+ ECC_DATA_ERROR = 1 << 1
+};
+
+/* Timing parameters */
+enum {
+ FDT_NAND_MAX_TRP_TREA,
+ FDT_NAND_TWB,
+ FDT_NAND_MAX_TCR_TAR_TRR,
+ FDT_NAND_TWHR,
+ FDT_NAND_MAX_TCS_TCH_TALS_TALH,
+ FDT_NAND_TWH,
+ FDT_NAND_TWP,
+ FDT_NAND_TRH,
+ FDT_NAND_TADL,
+
+ FDT_NAND_TIMING_COUNT
+};
+
+/* Information about an attached NAND chip */
+struct fdt_nand {
+ struct nand_ctlr *reg;
+ int enabled; /* 1 to enable, 0 to disable */
+ struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
+ s32 width; /* bit width, normally 8 */
+ u32 timing[FDT_NAND_TIMING_COUNT];
+};
+
+struct nand_drv {
+ struct nand_ctlr *reg;
+
+ /*
+ * When running in PIO mode to get READ ID bytes from register
+ * RESP_0, we need this variable as an index to know which byte in
+ * register RESP_0 should be read.
+ * Because common code in nand_base.c invokes read_byte function two
+ * times for NAND_CMD_READID.
+ * And our controller returns 4 bytes at once in register RESP_0.
+ */
+ int pio_byte_index;
+ struct fdt_nand config;
+};
+
+static struct nand_drv nand_ctrl;
+static struct mtd_info *our_mtd;
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+#ifdef CONFIG_SYS_DCACHE_OFF
+static inline void dma_prepare(void *start, unsigned long length,
+ int is_writing)
+{
+}
+#else
+/**
+ * Prepare for a DMA transaction
+ *
+ * For a write we flush out our data. For a read we invalidate, since we
+ * need to do this before we read from the buffer after the DMA has
+ * completed, so may as well do it now.
+ *
+ * @param start Start address for DMA buffer (should be cache-aligned)
+ * @param length Length of DMA buffer in bytes
+ * @param is_writing 0 if reading, non-zero if writing
+ */
+static void dma_prepare(void *start, unsigned long length, int is_writing)
+{
+ unsigned long addr = (unsigned long)start;
+
+ length = ALIGN(length, ARCH_DMA_MINALIGN);
+ if (is_writing)
+ flush_dcache_range(addr, addr + length);
+ else
+ invalidate_dcache_range(addr, addr + length);
+}
+#endif
+
+/**
+ * Wait for command completion
+ *
+ * @param reg nand_ctlr structure
+ * @return
+ * 1 - Command completed
+ * 0 - Timeout
+ */
+static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
+{
+ u32 reg_val;
+ int running;
+ int i;
+
+ for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
+ if ((readl(®->command) & CMD_GO) ||
+ !(readl(®->status) & STATUS_RBSY0) ||
+ !(readl(®->isr) & ISR_IS_CMD_DONE)) {
+ udelay(1);
+ continue;
+ }
+ reg_val = readl(®->dma_mst_ctrl);
+ /*
+ * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
+ * is set, that means DMA engine is running.
+ *
+ * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
+ * is cleared, indicating DMA transfer completion.
+ */
+ running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
+ DMA_MST_CTRL_EN_B_ENABLE);
+ if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
+ return 1;
+ udelay(1);
+ }
+ return 0;
+}
+
+/**
+ * Read one byte from the chip
+ *
+ * @param mtd MTD device structure
+ * @return data byte
+ *
+ * Read function for 8bit bus-width
+ */
+static uint8_t read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ u32 dword_read;
+ struct nand_drv *info;
+
+ info = (struct nand_drv *)chip->priv;
+
+ /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
+ if (info->pio_byte_index > 3) {
+ info->pio_byte_index = 0;
+ writel(CMD_GO | CMD_PIO
+ | CMD_RX | CMD_CE0,
+ &info->reg->command);
+ if (!nand_waitfor_cmd_completion(info->reg))
+ printf("Command timeout\n");
+ }
+
+ dword_read = readl(&info->reg->resp);
+ dword_read = dword_read >> (8 * info->pio_byte_index);
+ info->pio_byte_index++;
+ return (uint8_t)dword_read;
+}
+
+/**
+ * Check NAND status to see if it is ready or not
+ *
+ * @param mtd MTD device structure
+ * @return
+ * 1 - ready
+ * 0 - not ready
+ */
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ int reg_val;
+ struct nand_drv *info;
+
+ info = (struct nand_drv *)chip->priv;
+
+ reg_val = readl(&info->reg->status);
+ if (reg_val & STATUS_RBSY0)
+ return 1;
+ else
+ return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ switch (chipnr) {
+ case -1:
+ case 0:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+/**
+ * Clear all interrupt status bits
+ *
+ * @param reg nand_ctlr structure
+ */
+static void nand_clear_interrupt_status(struct nand_ctlr *reg)
+{
+ u32 reg_val;
+
+ /* Clear interrupt status */
+ reg_val = readl(®->isr);
+ writel(reg_val, ®->isr);
+}
+
+/**
+ * Send command to NAND device
+ *
+ * @param mtd MTD device structure
+ * @param command the command to be sent
+ * @param column the column address for this command, -1 if none
+ * @param page_addr the page address for this command, -1 if none
+ */
+static void nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct nand_drv *info;
+
+ info = (struct nand_drv *)chip->priv;
+
+ /*
+ * Write out the command to the device.
+ *
+ * Only command NAND_CMD_RESET or NAND_CMD_READID will come
+ * here before mtd->writesize is initialized.
+ */
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ assert(mtd->writesize != 0);
+ column += mtd->writesize;
+ command = NAND_CMD_READ0;
+ }
+
+ /* Adjust columns for 16 bit bus-width */
+ if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
+ column >>= 1;
+
+ nand_clear_interrupt_status(info->reg);
+
+ /* Stop DMA engine, clear DMA completion status */
+ writel(DMA_MST_CTRL_EN_A_DISABLE
+ | DMA_MST_CTRL_EN_B_DISABLE
+ | DMA_MST_CTRL_IS_DMA_DONE,
+ &info->reg->dma_mst_ctrl);
+
+ /*
+ * Program and erase have their own busy handlers
+ * status and sequential in needs no delay
+ */
+ switch (command) {
+ case NAND_CMD_READID:
+ writel(NAND_CMD_READID, &info->reg->cmd_reg1);
+ writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
+ | CMD_RX |
+ ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
+ | CMD_CE0,
+ &info->reg->command);
+ info->pio_byte_index = 0;
+ break;
+ case NAND_CMD_READ0:
+ writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
+ writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
+ writel((page_addr << 16) | (column & 0xFFFF),
+ &info->reg->addr_reg1);
+ writel(page_addr >> 16, &info->reg->addr_reg2);
+ return;
+ case NAND_CMD_SEQIN:
+ writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
+ writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
+ writel((page_addr << 16) | (column & 0xFFFF),
+ &info->reg->addr_reg1);
+ writel(page_addr >> 16,
+ &info->reg->addr_reg2);
+ return;
+ case NAND_CMD_PAGEPROG:
+ return;
+ case NAND_CMD_ERASE1:
+ writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
+ writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
+ writel(page_addr, &info->reg->addr_reg1);
+ writel(CMD_GO | CMD_CLE | CMD_ALE |
+ CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
+ &info->reg->command);
+ break;
+ case NAND_CMD_ERASE2:
+ return;
+ case NAND_CMD_STATUS:
+ writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
+ writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
+ | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
+ | CMD_CE0,
+ &info->reg->command);
+ info->pio_byte_index = 0;
+ break;
+ case NAND_CMD_RESET:
+ writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
+ writel(CMD_GO | CMD_CLE | CMD_CE0,
+ &info->reg->command);
+ break;
+ case NAND_CMD_RNDOUT:
+ default:
+ printf("%s: Unsupported command %d\n", __func__, command);
+ return;
+ }
+ if (!nand_waitfor_cmd_completion(info->reg))
+ printf("Command 0x%02X timeout\n", command);
+}
+
+/**
+ * Check whether the pointed buffer are all 0xff (blank).
+ *
+ * @param buf data buffer for blank check
+ * @param len length of the buffer in byte
+ * @return
+ * 1 - blank
+ * 0 - non-blank
+ */
+static int blank_check(u8 *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ if (buf[i] != 0xFF)
+ return 0;
+ return 1;
+}
+
+/**
+ * After a DMA transfer for read, we call this function to see whether there
+ * is any uncorrectable error on the pointed data buffer or oob buffer.
+ *
+ * @param reg nand_ctlr structure
+ * @param databuf data buffer
+ * @param a_len data buffer length
+ * @param oobbuf oob buffer
+ * @param b_len oob buffer length
+ * @return
+ * ECC_OK - no ECC error or correctable ECC error
+ * ECC_TAG_ERROR - uncorrectable tag ECC error
+ * ECC_DATA_ERROR - uncorrectable data ECC error
+ * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
+ */
+static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
+ int a_len, u8 *oobbuf, int b_len)
+{
+ int return_val = ECC_OK;
+ u32 reg_val;
+
+ if (!(readl(®->isr) & ISR_IS_ECC_ERR))
+ return ECC_OK;
+
+ /*
+ * Area A is used for the data block (databuf). Area B is used for
+ * the spare block (oobbuf)
+ */
+ reg_val = readl(®->dec_status);
+ if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
+ reg_val = readl(®->bch_dec_status_buf);
+ /*
+ * If uncorrectable error occurs on data area, then see whether
+ * they are all FF. If all are FF, it's a blank page.
+ * Not error.
+ */
+ if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
+ !blank_check(databuf, a_len))
+ return_val |= ECC_DATA_ERROR;
+ }
+
+ if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
+ reg_val = readl(®->bch_dec_status_buf);
+ /*
+ * If uncorrectable error occurs on tag area, then see whether
+ * they are all FF. If all are FF, it's a blank page.
+ * Not error.
+ */
+ if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
+ !blank_check(oobbuf, b_len))
+ return_val |= ECC_TAG_ERROR;
+ }
+
+ return return_val;
+}
+
+/**
+ * Set GO bit to send command to device
+ *
+ * @param reg nand_ctlr structure
+ */
+static void start_command(struct nand_ctlr *reg)
+{
+ u32 reg_val;
+
+ reg_val = readl(®->command);
+ reg_val |= CMD_GO;
+ writel(reg_val, ®->command);
+}
+
+/**
+ * Clear command GO bit, DMA GO bit, and DMA completion status
+ *
+ * @param reg nand_ctlr structure
+ */
+static void stop_command(struct nand_ctlr *reg)
+{
+ /* Stop command */
+ writel(0, ®->command);
+
+ /* Stop DMA engine and clear DMA completion status */
+ writel(DMA_MST_CTRL_GO_DISABLE
+ | DMA_MST_CTRL_IS_DMA_DONE,
+ ®->dma_mst_ctrl);
+}
+
+/**
+ * Set up NAND bus width and page size
+ *
+ * @param info nand_info structure
+ * @param *reg_val address of reg_val
+ * @return 0 if ok, -1 on error
+ */
+static int set_bus_width_page_size(struct fdt_nand *config,
+ u32 *reg_val)
+{
+ if (config->width == 8)
+ *reg_val = CFG_BUS_WIDTH_8BIT;
+ else if (config->width == 16)
+ *reg_val = CFG_BUS_WIDTH_16BIT;
+ else {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config->width);
+ return -1;
+ }
+
+ if (our_mtd->writesize == 512)
+ *reg_val |= CFG_PAGE_SIZE_512;
+ else if (our_mtd->writesize == 2048)
+ *reg_val |= CFG_PAGE_SIZE_2048;
+ else if (our_mtd->writesize == 4096)
+ *reg_val |= CFG_PAGE_SIZE_4096;
+ else {
+ debug("%s: Unsupported page size %d\n", __func__,
+ our_mtd->writesize);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Page read/write function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param buf data buffer
+ * @param page page number
+ * @param with_ecc 1 to enable ECC, 0 to disable ECC
+ * @param is_writing 0 for read, 1 for write
+ * @return 0 when successfully completed
+ * -EIO when command timeout
+ */
+static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page, int with_ecc, int is_writing)
+{
+ u32 reg_val;
+ int tag_size;
+ struct nand_oobfree *free = chip->ecc.layout->oobfree;
+ /* 4*128=512 (byte) is the value that our HW can support. */
+ ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
+ char *tag_ptr;
+ struct nand_drv *info;
+ struct fdt_nand *config;
+
+ if ((uintptr_t)buf & 0x03) {
+ printf("buf %p has to be 4-byte aligned\n", buf);
+ return -EINVAL;
+ }
+
+ info = (struct nand_drv *)chip->priv;
+ config = &info->config;
+ if (set_bus_width_page_size(config, ®_val))
+ return -EINVAL;
+
+ /* Need to be 4-byte aligned */
+ tag_ptr = (char *)tag_buf;
+
+ stop_command(info->reg);
+
+ writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
+ writel(virt_to_phys(buf), &info->reg->data_block_ptr);
+
+ if (with_ecc) {
+ writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
+ if (is_writing)
+ memcpy(tag_ptr, chip->oob_poi + free->offset,
+ chip->ecc.layout->oobavail +
+ TAG_ECC_BYTES);
+ } else {
+ writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
+ }
+
+ /* Set ECC selection, configure ECC settings */
+ if (with_ecc) {
+ tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
+ reg_val |= (CFG_SKIP_SPARE_SEL_4
+ | CFG_SKIP_SPARE_ENABLE
+ | CFG_HW_ECC_CORRECTION_ENABLE
+ | CFG_ECC_EN_TAG_DISABLE
+ | CFG_HW_ECC_SEL_RS
+ | CFG_HW_ECC_ENABLE
+ | CFG_TVAL4
+ | (tag_size - 1));
+
+ if (!is_writing)
+ tag_size += SKIPPED_SPARE_BYTES;
+ dma_prepare(tag_ptr, tag_size, is_writing);
+ } else {
+ tag_size = mtd->oobsize;
+ reg_val |= (CFG_SKIP_SPARE_DISABLE
+ | CFG_HW_ECC_CORRECTION_DISABLE
+ | CFG_ECC_EN_TAG_DISABLE
+ | CFG_HW_ECC_DISABLE
+ | (tag_size - 1));
+ dma_prepare(chip->oob_poi, tag_size, is_writing);
+ }
+ writel(reg_val, &info->reg->config);
+
+ dma_prepare(buf, 1 << chip->page_shift, is_writing);
+
+ writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
+
+ writel(tag_size - 1, &info->reg->dma_cfg_b);
+
+ nand_clear_interrupt_status(info->reg);
+
+ reg_val = CMD_CLE | CMD_ALE
+ | CMD_SEC_CMD
+ | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
+ | CMD_A_VALID
+ | CMD_B_VALID
+ | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
+ | CMD_CE0;
+ if (!is_writing)
+ reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
+ else
+ reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
+ writel(reg_val, &info->reg->command);
+
+ /* Setup DMA engine */
+ reg_val = DMA_MST_CTRL_GO_ENABLE
+ | DMA_MST_CTRL_BURST_8WORDS
+ | DMA_MST_CTRL_EN_A_ENABLE
+ | DMA_MST_CTRL_EN_B_ENABLE;
+
+ if (!is_writing)
+ reg_val |= DMA_MST_CTRL_DIR_READ;
+ else
+ reg_val |= DMA_MST_CTRL_DIR_WRITE;
+
+ writel(reg_val, &info->reg->dma_mst_ctrl);
+
+ start_command(info->reg);
+
+ if (!nand_waitfor_cmd_completion(info->reg)) {
+ if (!is_writing)
+ printf("Read Page 0x%X timeout ", page);
+ else
+ printf("Write Page 0x%X timeout ", page);
+ if (with_ecc)
+ printf("with ECC");
+ else
+ printf("without ECC");
+ printf("\n");
+ return -EIO;
+ }
+
+ if (with_ecc && !is_writing) {
+ memcpy(chip->oob_poi, tag_ptr,
+ SKIPPED_SPARE_BYTES);
+ memcpy(chip->oob_poi + free->offset,
+ tag_ptr + SKIPPED_SPARE_BYTES,
+ chip->ecc.layout->oobavail);
+ reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
+ 1 << chip->page_shift,
+ (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
+ chip->ecc.layout->oobavail);
+ if (reg_val & ECC_TAG_ERROR)
+ printf("Read Page 0x%X tag ECC error\n", page);
+ if (reg_val & ECC_DATA_ERROR)
+ printf("Read Page 0x%X data ECC error\n",
+ page);
+ if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
+ return -EIO;
+ }
+ return 0;
+}
+
+/**
+ * Hardware ecc based page read function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param buf buffer to store read data
+ * @param page page number to read
+ * @return 0 when successfully completed
+ * -EIO when command timeout
+ */
+static int nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int page)
+{
+ return nand_rw_page(mtd, chip, buf, page, 1, 0);
+}
+
+/**
+ * Hardware ecc based page write function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param buf data buffer
+ */
+static void nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ int page;
+ struct nand_drv *info;
+
+ info = (struct nand_drv *)chip->priv;
+
+ page = (readl(&info->reg->addr_reg1) >> 16) |
+ (readl(&info->reg->addr_reg2) << 16);
+
+ nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
+}
+
+
+/**
+ * Read raw page data without ecc
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param buf buffer to store read data
+ * @param page page number to read
+ * @return 0 when successfully completed
+ * -EINVAL when chip->oob_poi is not double-word aligned
+ * -EIO when command timeout
+ */
+static int nand_read_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int page)
+{
+ return nand_rw_page(mtd, chip, buf, page, 0, 0);
+}
+
+/**
+ * Raw page write function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param buf data buffer
+ */
+static void nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf)
+{
+ int page;
+ struct nand_drv *info;
+
+ info = (struct nand_drv *)chip->priv;
+ page = (readl(&info->reg->addr_reg1) >> 16) |
+ (readl(&info->reg->addr_reg2) << 16);
+
+ nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
+}
+
+/**
+ * OOB data read/write function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param page page number to read
+ * @param with_ecc 1 to enable ECC, 0 to disable ECC
+ * @param is_writing 0 for read, 1 for write
+ * @return 0 when successfully completed
+ * -EINVAL when chip->oob_poi is not double-word aligned
+ * -EIO when command timeout
+ */
+static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int with_ecc, int is_writing)
+{
+ u32 reg_val;
+ int tag_size;
+ struct nand_oobfree *free = chip->ecc.layout->oobfree;
+ struct nand_drv *info;
+
+ if (((int)chip->oob_poi) & 0x03)
+ return -EINVAL;
+ info = (struct nand_drv *)chip->priv;
+ if (set_bus_width_page_size(&info->config, ®_val))
+ return -EINVAL;
+
+ stop_command(info->reg);
+
+ writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
+
+ /* Set ECC selection */
+ tag_size = mtd->oobsize;
+ if (with_ecc)
+ reg_val |= CFG_ECC_EN_TAG_ENABLE;
+ else
+ reg_val |= (CFG_ECC_EN_TAG_DISABLE);
+
+ reg_val |= ((tag_size - 1) |
+ CFG_SKIP_SPARE_DISABLE |
+ CFG_HW_ECC_CORRECTION_DISABLE |
+ CFG_HW_ECC_DISABLE);
+ writel(reg_val, &info->reg->config);
+
+ dma_prepare(chip->oob_poi, tag_size, is_writing);
+
+ writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
+
+ if (is_writing && with_ecc)
+ tag_size -= TAG_ECC_BYTES;
+
+ writel(tag_size - 1, &info->reg->dma_cfg_b);
+
+ nand_clear_interrupt_status(info->reg);
+
+ reg_val = CMD_CLE | CMD_ALE
+ | CMD_SEC_CMD
+ | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
+ | CMD_B_VALID
+ | CMD_CE0;
+ if (!is_writing)
+ reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
+ else
+ reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
+ writel(reg_val, &info->reg->command);
+
+ /* Setup DMA engine */
+ reg_val = DMA_MST_CTRL_GO_ENABLE
+ | DMA_MST_CTRL_BURST_8WORDS
+ | DMA_MST_CTRL_EN_B_ENABLE;
+ if (!is_writing)
+ reg_val |= DMA_MST_CTRL_DIR_READ;
+ else
+ reg_val |= DMA_MST_CTRL_DIR_WRITE;
+
+ writel(reg_val, &info->reg->dma_mst_ctrl);
+
+ start_command(info->reg);
+
+ if (!nand_waitfor_cmd_completion(info->reg)) {
+ if (!is_writing)
+ printf("Read OOB of Page 0x%X timeout\n", page);
+ else
+ printf("Write OOB of Page 0x%X timeout\n", page);
+ return -EIO;
+ }
+
+ if (with_ecc && !is_writing) {
+ reg_val = (u32)check_ecc_error(info->reg, 0, 0,
+ (u8 *)(chip->oob_poi + free->offset),
+ chip->ecc.layout->oobavail);
+ if (reg_val & ECC_TAG_ERROR)
+ printf("Read OOB of Page 0x%X tag ECC error\n", page);
+ }
+ return 0;
+}
+
+/**
+ * OOB data read function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param page page number to read
+ * @param sndcmd flag whether to issue read command or not
+ * @return 1 - issue read command next time
+ * 0 - not to issue
+ */
+static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int sndcmd)
+{
+ if (sndcmd) {
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+ sndcmd = 0;
+ }
+ nand_rw_oob(mtd, chip, page, 0, 0);
+ return sndcmd;
+}
+
+/**
+ * OOB data write function
+ *
+ * @param mtd mtd info structure
+ * @param chip nand chip info structure
+ * @param page page number to write
+ * @return 0 when successfully completed
+ * -EINVAL when chip->oob_poi is not double-word aligned
+ * -EIO when command timeout
+ */
+static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ return nand_rw_oob(mtd, chip, page, 0, 1);
+}
+
+/**
+ * Set up NAND memory timings according to the provided parameters
+ *
+ * @param timing Timing parameters
+ * @param reg NAND controller register address
+ */
+static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
+ struct nand_ctlr *reg)
+{
+ u32 reg_val, clk_rate, clk_period, time_val;
+
+ clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
+ CLOCK_ID_PERIPH) / 1000000;
+ clk_period = 1000 / clk_rate;
+ reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
+ TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
+ TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
+ time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
+ if (time_val > 2)
+ reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
+ TIMING_TCR_TAR_TRR_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
+ TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
+ time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
+ if (time_val > 1)
+ reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
+ TIMING_TCS_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
+ TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
+ TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
+ TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
+ reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
+ TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
+ writel(reg_val, ®->timing);
+
+ reg_val = 0;
+ time_val = timing[FDT_NAND_TADL] / clk_period;
+ if (time_val > 2)
+ reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
+ writel(reg_val, ®->timing2);
+}
+
+/**
+ * Decode NAND parameters from the device tree
+ *
+ * @param blob Device tree blob
+ * @param node Node containing "nand-flash" compatble node
+ * @return 0 if ok, -ve on error (FDT_ERR_...)
+ */
+static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
+{
+ int err;
+
+ config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ config->enabled = fdtdec_get_is_enabled(blob, node);
+ config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
+ err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
+ &config->wp_gpio);
+ if (err)
+ return err;
+ err = fdtdec_get_int_array(blob, node, "nvidia,timing",
+ config->timing, FDT_NAND_TIMING_COUNT);
+ if (err < 0)
+ return err;
+
+ /* Now look up the controller and decode that */
+ node = fdt_next_node(blob, node, NULL);
+ if (node < 0)
+ return node;
+
+ return 0;
+}
+
+/**
+ * Board-specific NAND initialization
+ *
+ * @param nand nand chip info structure
+ * @return 0, after initialized, -1 on error
+ */
+int tegra_nand_init(struct nand_chip *nand, int devnum)
+{
+ struct nand_drv *info = &nand_ctrl;
+ struct fdt_nand *config = &info->config;
+ int node, ret;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_NAND);
+ if (node < 0)
+ return -1;
+ if (fdt_decode_nand(gd->fdt_blob, node, config)) {
+ printf("Could not decode nand-flash in device tree\n");
+ return -1;
+ }
+ if (!config->enabled)
+ return -1;
+ info->reg = config->reg;
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.layout = &eccoob;
+
+ nand->options = LP_OPTIONS;
+ nand->cmdfunc = nand_command;
+ nand->read_byte = read_byte;
+ nand->ecc.read_page = nand_read_page_hwecc;
+ nand->ecc.write_page = nand_write_page_hwecc;
+ nand->ecc.read_page_raw = nand_read_page_raw;
+ nand->ecc.write_page_raw = nand_write_page_raw;
+ nand->ecc.read_oob = nand_read_oob;
+ nand->ecc.write_oob = nand_write_oob;
+ nand->select_chip = nand_select_chip;
+ nand->dev_ready = nand_dev_ready;
+ nand->priv = &nand_ctrl;
+
+ /* Adjust controller clock rate */
+ clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
+
+ /* Adjust timing for NAND device */
+ setup_timing(config->timing, info->reg);
+
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+ fdtdec_setup_gpio(&config->wp_gpio);
+ gpio_direction_output(config->wp_gpio.gpio, 1);
+
+ our_mtd = &nand_info[devnum];
+ our_mtd->priv = nand;
+ ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
+ if (ret)
+ return ret;
+
+ nand->ecc.size = our_mtd->writesize;
+ nand->ecc.bytes = our_mtd->oobsize;
+
+ ret = nand_scan_tail(our_mtd);
+ if (ret)
+ return ret;
+
+ ret = nand_register(devnum);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void board_nand_init(void)
+{
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (tegra_nand_init(nand, 0))
+ puts("Tegra NAND init failed\n");
+}
--- /dev/null
+/*
+ * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* register offset */
+#define COMMAND_0 0x00
+#define CMD_GO (1 << 31)
+#define CMD_CLE (1 << 30)
+#define CMD_ALE (1 << 29)
+#define CMD_PIO (1 << 28)
+#define CMD_TX (1 << 27)
+#define CMD_RX (1 << 26)
+#define CMD_SEC_CMD (1 << 25)
+#define CMD_AFT_DAT_MASK (1 << 24)
+#define CMD_AFT_DAT_DISABLE 0
+#define CMD_AFT_DAT_ENABLE (1 << 24)
+#define CMD_TRANS_SIZE_SHIFT 20
+#define CMD_TRANS_SIZE_PAGE 8
+#define CMD_A_VALID (1 << 19)
+#define CMD_B_VALID (1 << 18)
+#define CMD_RD_STATUS_CHK (1 << 17)
+#define CMD_R_BSY_CHK (1 << 16)
+#define CMD_CE7 (1 << 15)
+#define CMD_CE6 (1 << 14)
+#define CMD_CE5 (1 << 13)
+#define CMD_CE4 (1 << 12)
+#define CMD_CE3 (1 << 11)
+#define CMD_CE2 (1 << 10)
+#define CMD_CE1 (1 << 9)
+#define CMD_CE0 (1 << 8)
+#define CMD_CLE_BYTE_SIZE_SHIFT 4
+enum {
+ CMD_CLE_BYTES1 = 0,
+ CMD_CLE_BYTES2,
+ CMD_CLE_BYTES3,
+ CMD_CLE_BYTES4,
+};
+#define CMD_ALE_BYTE_SIZE_SHIFT 0
+enum {
+ CMD_ALE_BYTES1 = 0,
+ CMD_ALE_BYTES2,
+ CMD_ALE_BYTES3,
+ CMD_ALE_BYTES4,
+ CMD_ALE_BYTES5,
+ CMD_ALE_BYTES6,
+ CMD_ALE_BYTES7,
+ CMD_ALE_BYTES8
+};
+
+#define STATUS_0 0x04
+#define STATUS_RBSY0 (1 << 8)
+
+#define ISR_0 0x08
+#define ISR_IS_CMD_DONE (1 << 5)
+#define ISR_IS_ECC_ERR (1 << 4)
+
+#define IER_0 0x0C
+
+#define CFG_0 0x10
+#define CFG_HW_ECC_MASK (1 << 31)
+#define CFG_HW_ECC_DISABLE 0
+#define CFG_HW_ECC_ENABLE (1 << 31)
+#define CFG_HW_ECC_SEL_MASK (1 << 30)
+#define CFG_HW_ECC_SEL_HAMMING 0
+#define CFG_HW_ECC_SEL_RS (1 << 30)
+#define CFG_HW_ECC_CORRECTION_MASK (1 << 29)
+#define CFG_HW_ECC_CORRECTION_DISABLE 0
+#define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29)
+#define CFG_PIPELINE_EN_MASK (1 << 28)
+#define CFG_PIPELINE_EN_DISABLE 0
+#define CFG_PIPELINE_EN_ENABLE (1 << 28)
+#define CFG_ECC_EN_TAG_MASK (1 << 27)
+#define CFG_ECC_EN_TAG_DISABLE 0
+#define CFG_ECC_EN_TAG_ENABLE (1 << 27)
+#define CFG_TVALUE_MASK (3 << 24)
+enum {
+ CFG_TVAL4 = 0 << 24,
+ CFG_TVAL6 = 1 << 24,
+ CFG_TVAL8 = 2 << 24
+};
+#define CFG_SKIP_SPARE_MASK (1 << 23)
+#define CFG_SKIP_SPARE_DISABLE 0
+#define CFG_SKIP_SPARE_ENABLE (1 << 23)
+#define CFG_COM_BSY_MASK (1 << 22)
+#define CFG_COM_BSY_DISABLE 0
+#define CFG_COM_BSY_ENABLE (1 << 22)
+#define CFG_BUS_WIDTH_MASK (1 << 21)
+#define CFG_BUS_WIDTH_8BIT 0
+#define CFG_BUS_WIDTH_16BIT (1 << 21)
+#define CFG_LPDDR1_MODE_MASK (1 << 20)
+#define CFG_LPDDR1_MODE_DISABLE 0
+#define CFG_LPDDR1_MODE_ENABLE (1 << 20)
+#define CFG_EDO_MODE_MASK (1 << 19)
+#define CFG_EDO_MODE_DISABLE 0
+#define CFG_EDO_MODE_ENABLE (1 << 19)
+#define CFG_PAGE_SIZE_SEL_MASK (7 << 16)
+enum {
+ CFG_PAGE_SIZE_256 = 0 << 16,
+ CFG_PAGE_SIZE_512 = 1 << 16,
+ CFG_PAGE_SIZE_1024 = 2 << 16,
+ CFG_PAGE_SIZE_2048 = 3 << 16,
+ CFG_PAGE_SIZE_4096 = 4 << 16
+};
+#define CFG_SKIP_SPARE_SEL_MASK (3 << 14)
+enum {
+ CFG_SKIP_SPARE_SEL_4 = 0 << 14,
+ CFG_SKIP_SPARE_SEL_8 = 1 << 14,
+ CFG_SKIP_SPARE_SEL_12 = 2 << 14,
+ CFG_SKIP_SPARE_SEL_16 = 3 << 14
+};
+#define CFG_TAG_BYTE_SIZE_MASK 0x1FF
+
+#define TIMING_0 0x14
+#define TIMING_TRP_RESP_CNT_SHIFT 28
+#define TIMING_TRP_RESP_CNT_MASK (0xf << TIMING_TRP_RESP_CNT_SHIFT)
+#define TIMING_TWB_CNT_SHIFT 24
+#define TIMING_TWB_CNT_MASK (0xf << TIMING_TWB_CNT_SHIFT)
+#define TIMING_TCR_TAR_TRR_CNT_SHIFT 20
+#define TIMING_TCR_TAR_TRR_CNT_MASK (0xf << TIMING_TCR_TAR_TRR_CNT_SHIFT)
+#define TIMING_TWHR_CNT_SHIFT 16
+#define TIMING_TWHR_CNT_MASK (0xf << TIMING_TWHR_CNT_SHIFT)
+#define TIMING_TCS_CNT_SHIFT 14
+#define TIMING_TCS_CNT_MASK (3 << TIMING_TCS_CNT_SHIFT)
+#define TIMING_TWH_CNT_SHIFT 12
+#define TIMING_TWH_CNT_MASK (3 << TIMING_TWH_CNT_SHIFT)
+#define TIMING_TWP_CNT_SHIFT 8
+#define TIMING_TWP_CNT_MASK (0xf << TIMING_TWP_CNT_SHIFT)
+#define TIMING_TRH_CNT_SHIFT 4
+#define TIMING_TRH_CNT_MASK (3 << TIMING_TRH_CNT_SHIFT)
+#define TIMING_TRP_CNT_SHIFT 0
+#define TIMING_TRP_CNT_MASK (0xf << TIMING_TRP_CNT_SHIFT)
+
+#define RESP_0 0x18
+
+#define TIMING2_0 0x1C
+#define TIMING2_TADL_CNT_SHIFT 0
+#define TIMING2_TADL_CNT_MASK (0xf << TIMING2_TADL_CNT_SHIFT)
+
+#define CMD_REG1_0 0x20
+#define CMD_REG2_0 0x24
+#define ADDR_REG1_0 0x28
+#define ADDR_REG2_0 0x2C
+
+#define DMA_MST_CTRL_0 0x30
+#define DMA_MST_CTRL_GO_MASK (1 << 31)
+#define DMA_MST_CTRL_GO_DISABLE 0
+#define DMA_MST_CTRL_GO_ENABLE (1 << 31)
+#define DMA_MST_CTRL_DIR_MASK (1 << 30)
+#define DMA_MST_CTRL_DIR_READ 0
+#define DMA_MST_CTRL_DIR_WRITE (1 << 30)
+#define DMA_MST_CTRL_PERF_EN_MASK (1 << 29)
+#define DMA_MST_CTRL_PERF_EN_DISABLE 0
+#define DMA_MST_CTRL_PERF_EN_ENABLE (1 << 29)
+#define DMA_MST_CTRL_REUSE_BUFFER_MASK (1 << 27)
+#define DMA_MST_CTRL_REUSE_BUFFER_DISABLE 0
+#define DMA_MST_CTRL_REUSE_BUFFER_ENABLE (1 << 27)
+#define DMA_MST_CTRL_BURST_SIZE_SHIFT 24
+#define DMA_MST_CTRL_BURST_SIZE_MASK (7 << DMA_MST_CTRL_BURST_SIZE_SHIFT)
+enum {
+ DMA_MST_CTRL_BURST_1WORDS = 2 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+ DMA_MST_CTRL_BURST_4WORDS = 3 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+ DMA_MST_CTRL_BURST_8WORDS = 4 << DMA_MST_CTRL_BURST_SIZE_SHIFT,
+ DMA_MST_CTRL_BURST_16WORDS = 5 << DMA_MST_CTRL_BURST_SIZE_SHIFT
+};
+#define DMA_MST_CTRL_IS_DMA_DONE (1 << 20)
+#define DMA_MST_CTRL_EN_A_MASK (1 << 2)
+#define DMA_MST_CTRL_EN_A_DISABLE 0
+#define DMA_MST_CTRL_EN_A_ENABLE (1 << 2)
+#define DMA_MST_CTRL_EN_B_MASK (1 << 1)
+#define DMA_MST_CTRL_EN_B_DISABLE 0
+#define DMA_MST_CTRL_EN_B_ENABLE (1 << 1)
+
+#define DMA_CFG_A_0 0x34
+#define DMA_CFG_B_0 0x38
+#define FIFO_CTRL_0 0x3C
+#define DATA_BLOCK_PTR_0 0x40
+#define TAG_PTR_0 0x44
+#define ECC_PTR_0 0x48
+
+#define DEC_STATUS_0 0x4C
+#define DEC_STATUS_A_ECC_FAIL (1 << 1)
+#define DEC_STATUS_B_ECC_FAIL (1 << 0)
+
+#define BCH_CONFIG_0 0xCC
+#define BCH_CONFIG_BCH_TVALUE_SHIFT 4
+#define BCH_CONFIG_BCH_TVALUE_MASK (3 << BCH_CONFIG_BCH_TVALUE_SHIFT)
+enum {
+ BCH_CONFIG_BCH_TVAL4 = 0 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+ BCH_CONFIG_BCH_TVAL8 = 1 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+ BCH_CONFIG_BCH_TVAL14 = 2 << BCH_CONFIG_BCH_TVALUE_SHIFT,
+ BCH_CONFIG_BCH_TVAL16 = 3 << BCH_CONFIG_BCH_TVALUE_SHIFT
+};
+#define BCH_CONFIG_BCH_ECC_MASK (1 << 0)
+#define BCH_CONFIG_BCH_ECC_DISABLE 0
+#define BCH_CONFIG_BCH_ECC_ENABLE (1 << 0)
+
+#define BCH_DEC_RESULT_0 0xD0
+#define BCH_DEC_RESULT_CORRFAIL_ERR_MASK (1 << 8)
+#define BCH_DEC_RESULT_PAGE_COUNT_MASK 0xFF
+
+#define BCH_DEC_STATUS_BUF_0 0xD4
+#define BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK 0xFF000000
+#define BCH_DEC_STATUS_CORR_SEC_FLAG_MASK 0x00FF0000
+#define BCH_DEC_STATUS_FAIL_TAG_MASK (1 << 14)
+#define BCH_DEC_STATUS_CORR_TAG_MASK (1 << 13)
+#define BCH_DEC_STATUS_MAX_CORR_CNT_MASK (0x1f << 8)
+#define BCH_DEC_STATUS_PAGE_NUMBER_MASK 0xFF
+
+#define LP_OPTIONS (NAND_NO_READRDY | NAND_NO_AUTOINCR)
+
+struct nand_ctlr {
+ u32 command; /* offset 00h */
+ u32 status; /* offset 04h */
+ u32 isr; /* offset 08h */
+ u32 ier; /* offset 0Ch */
+ u32 config; /* offset 10h */
+ u32 timing; /* offset 14h */
+ u32 resp; /* offset 18h */
+ u32 timing2; /* offset 1Ch */
+ u32 cmd_reg1; /* offset 20h */
+ u32 cmd_reg2; /* offset 24h */
+ u32 addr_reg1; /* offset 28h */
+ u32 addr_reg2; /* offset 2Ch */
+ u32 dma_mst_ctrl; /* offset 30h */
+ u32 dma_cfg_a; /* offset 34h */
+ u32 dma_cfg_b; /* offset 38h */
+ u32 fifo_ctrl; /* offset 3Ch */
+ u32 data_block_ptr; /* offset 40h */
+ u32 tag_ptr; /* offset 44h */
+ u32 resv1; /* offset 48h */
+ u32 dec_status; /* offset 4Ch */
+ u32 hwstatus_cmd; /* offset 50h */
+ u32 hwstatus_mask; /* offset 54h */
+ u32 resv2[29];
+ u32 bch_config; /* offset CCh */
+ u32 bch_dec_result; /* offset D0h */
+ u32 bch_dec_status_buf;
+ /* offset D4h */
+};
.nr_sectors = 32,
.name = "AT45DB642D",
},
+ {
+ .idcode1 = 0x47,
+ .l2_page_size = 8,
+ .pages_per_block = 16,
+ .blocks_per_sector = 16,
+ .nr_sectors = 64,
+ .name = "AT25DF321",
+ },
};
static int at45_wait_ready(struct spi_flash *flash, unsigned long timeout)
asf->flash.erase = dataflash_erase_p2;
}
+ asf->flash.page_size = page_size;
+ asf->flash.sector_size = page_size;
break;
case DF_FAMILY_AT26F:
case DF_FAMILY_AT26DF:
asf->flash.read = spi_flash_cmd_read_fast;
+ asf->flash.write = spi_flash_cmd_write_multi;
+ asf->flash.erase = spi_flash_cmd_erase;
+ asf->flash.page_size = page_size;
+ asf->flash.sector_size = 4096;
+ /* clear SPRL# bit for locked flash */
+ spi_flash_cmd_write_status(&asf->flash, 0);
break;
default:
goto err;
}
- asf->flash.sector_size = page_size;
asf->flash.size = page_size * params->pages_per_block
* params->blocks_per_sector
* params->nr_sectors;
return NULL;
}
- if (max_hz > TEGRA20_SPI_MAX_FREQ) {
+ if (max_hz > TEGRA_SPI_MAX_FREQ) {
printf("SPI error: unsupported frequency %d Hz. Max frequency"
- " is %d Hz\n", max_hz, TEGRA20_SPI_MAX_FREQ);
+ " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
return NULL;
}
spi->slave.bus = bus;
spi->slave.cs = cs;
spi->freq = max_hz;
- spi->regs = (struct spi_tegra *)TEGRA20_SPI_BASE;
+ spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
spi->mode = mode;
return &spi->slave;
writel(panel_cfg->pol_freq, &dispc->pol_freq);
writel(panel_cfg->divisor, &dispc->divisor);
writel(panel_cfg->lcd_size, &dispc->size_lcd);
- writel(panel_cfg->load_mode << FRAME_MODE_SHIFT, &dispc->config);
+ writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
writel(panel_cfg->panel_type << TFTSTN_SHIFT |
panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control);
writel(panel_cfg->panel_color, &dispc->default_color0);
if (!panel_cfg->frame_buffer)
return;
- writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes);
writel(1, &dispc->gfx_row_inc);
writel(1, &dispc->gfx_pixel_inc);
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE 0x21f00000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_OF_LIBFDT
+
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define MACH_TYPE_EB_CPUX9K2 1977
#define CONFIG_MACH_TYPE MACH_TYPE_EB_CPUX9K2
/*--------------------------------------------------------------------------*/
-#define CONFIG_SYS_TEXT_BASE 0x00000000
+#ifndef CONFIG_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x21f00000
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Harmony) # "
-#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Harmony"
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
/* UARTA: debug board UART */
#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
-/* Environment not stored */
-#define CONFIG_ENV_IS_NOWHERE
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
+
+/* Environment in NAND (which is 512M), aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Common ARM Integrator configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define CONFIG_INTEGRATOR
+
+#define CONFIG_SYS_TEXT_BASE 0x01000000
+#define CONFIG_SYS_MEMTEST_START 0x100000
+#define CONFIG_SYS_MEMTEST_END 0x10000000
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
+#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */
+
+/*
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ */
+#include "armcoremodule.h"
+
+/*
+ * Initialize and remap the core module, use SPD to detect memory size
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+ */
+#define CONFIG_CM_INIT
+#define CONFIG_CM_REMAP
+#define CONFIG_CM_SPD_DETECT
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+ */
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+ */
+/* #define SKIP_CONFIG_RELOCATE_UBOOT */
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_INTEGRATOR
+#include "integrator-common.h"
+
+/* Integrator/AP-specific configuration */
#define CONFIG_ARCH_INTEGRATOR
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE 0x01000000
-#define CONFIG_SYS_MEMTEST_START 0x100000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
-#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_CM_INIT 1
-#define CONFIG_CM_REMAP 1
-#define CONFIG_CM_SPD_DETECT
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* PL010 Configuration
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_FLASH_BASE 0x24000000
#ifndef __CONFIG_H
#define __CONFIG_H
-/* Integrator-specific configuration */
-#define CONFIG_INTEGRATOR
-#define CONFIG_ARCH_CINTEGRATOR
-#define CONFIG_CM_INIT
-#define CONFIG_CM_REMAP
-#define CONFIG_CM_SPD_DETECT
+#include "integrator-common.h"
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_TEXT_BASE 0x01000000
-#define CONFIG_SYS_MEMTEST_START 0x100000
-#define CONFIG_SYS_MEMTEST_END 0x10000000
-#define CONFIG_SYS_HZ 1000
+/* Integrator CP-specific configuration */
+#define CONFIG_ARCH_CINTEGRATOR
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */
-#define CONFIG_SYS_TIMERBASE 0x13000100
-
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
-/*
- * NS16550 Configuration
- */
+/* PL011 configuration */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 14745600
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_SYS_SERIAL0 0x16000000
#define CONFIG_SYS_SERIAL1 0x17000000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
/*
* Command line configuration.
*/
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
-#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
+/*
* FLASH and environment organization
-
* Top varies according to amount fitted
* Reserve top 4 blocks of flash
* - ARM Boot Monitor
* - U-Boot environment
*
* Base is always 0x24000000
-
*/
#define CONFIG_SYS_FLASH_BASE 0x24000000
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CONFIG_ENV_SIZE 8192 /* 8KB */
-/*
- * The ARM boot monitor initializes the board.
- * However, the default U-Boot code also performs the initialization.
- * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
- * - see documentation supplied with board for details of how to choose the
- * image to run at reset/power up
- * e.g. whether the ARM Boot Monitor runs before U-Boot
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
- */
-
-/*
- * The ARM boot monitor does not relocate U-Boot.
- * However, the default U-Boot code performs the relocation check,
- * and may relocate the code if the memory map is changed.
- * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
-
-#define SKIP_CONFIG_RELOCATE_UBOOT
-
- */
-/*-----------------------------------------------------------------------
- * There are various dependencies on the core module (CM) fitted
- * Users should refer to their CM user guide
- * - when porting adjust u-boot/Makefile accordingly
- * to define the necessary CONFIG_ s for the CM involved
- * see e.g. cp_926ejs_config
- */
-
-#include "armcoremodule.h"
-
-/*
- * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
- * the core module has a CM_INIT register
- * then the U-Boot initialisation code will
- * e.g. ARM Boot Monitor or pre-loader is repeated once
- * (to re-initialise any existing CM_INIT settings to safe values).
- *
- * This is usually not the desired behaviour since the platform
- * will either reboot into the ARM monitor (or pre-loader)
- * or continuously cycle thru it without U-Boot running,
- * depending upon the setting of Integrator/CP switch S2-4.
- *
- * However it may be needed if Integrator/CP switch S2-1
- * is set OFF to boot direct into U-Boot.
- * In that case comment out the line below.
-#undef CONFIG_CM_INIT
- */
-
#endif /* __CONFIG_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Medcom) # "
-#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Medcom"
+#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
+ *
+ * Configuration settings for the Teejet mt_ventoux board.
+ *
* Copyright (C) 2009 TechNexion Ltd.
*
* This program is free software; you can redistribute it and/or modify
#include "tam3517-common.h"
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
+ 6 * 1024 * 1024)
+
#define MACH_TYPE_AM3517_MT_VENTOUX 3832
#define CONFIG_MACH_TYPE MACH_TYPE_AM3517_MT_VENTOUX
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_AUTO_COMPLETE
+#define CONFIG_OMAP3_GPIO_4
#define CONFIG_HOSTNAME mt_ventoux
/*
#define CONFIG_FPGA_DELAY() udelay(1)
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_OMAP3 /* DSS Support */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \
"bootcmd=run net_nfs\0"
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Paz00) MOD # "
-#define CONFIG_TEGRA20_BOARD_STRING "Compal Paz00"
+#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
+#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Plutux) # "
-#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Plutux"
+#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#include <asm/sizes.h>
/* LP0 suspend / resume */
-#define CONFIG_TEGRA20_LP0
+#define CONFIG_TEGRA_LP0
#define CONFIG_AES
#define CONFIG_TEGRA_PMU
#define CONFIG_TPS6586X_POWER
/* High-level configuration options */
#define V_PROMPT "Tegra20 (SeaBoard) # "
-#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Seaboard"
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_CMD_DHCP
/* Enable keyboard */
-#define CONFIG_TEGRA20_KEYBOARD
+#define CONFIG_TEGRA_KEYBOARD
#define CONFIG_KEYBOARD
-#undef TEGRA20_DEVICE_SETTINGS
-#define TEGRA20_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
+#undef TEGRA_DEVICE_SETTINGS
+#define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* Somewhat oddly, the NAND base address must be a config option */
+#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
#endif /* __CONFIG_H */
#define CONFIG_INITRD_TAG /* pass initrd param to kernel */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_BOARD_EARLY_INIT_f /* call board_early_init_f() */
+#define CONFIG_BOARD_POSTCLK_INIT /* call board_postclk_init() */
#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */
/* setting board specific options */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
#undef CONFIG_CMD_IMLS
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_DRIVER_OMAP34XX_I2C
"fi;" \
"else echo U-Boot not downloaded..exiting;fi\0" \
+
+/*
+ * this is common code for all TAM3517 boards.
+ * MAC address is stored from manufacturer in
+ * I2C EEPROM
+ */
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+
+/*
+ * The I2C EEPROM on the TAM3517 contains
+ * mac address and production data
+ */
+struct tam3517_module_info {
+ char customer[48];
+ char product[48];
+
+ /*
+ * bit 0~47 : sequence number
+ * bit 48~55 : week of year, from 0.
+ * bit 56~63 : year
+ */
+ unsigned long long sequence_number;
+
+ /*
+ * bit 0~7 : revision fixed
+ * bit 8~15 : revision major
+ * bit 16~31 : TNxxx
+ */
+ unsigned int revision;
+ unsigned char eth_addr[4][8];
+ unsigned char _rev[100];
+};
+
+#define TAM3517_READ_MAC_FROM_EEPROM \
+do { \
+ struct tam3517_module_info info;\
+ char buf[80], ethname[20]; \
+ int i; \
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
+ (void *)&info, sizeof(info))) \
+ break; \
+ memset(buf, 0, sizeof(buf)); \
+ for (i = 0 ; i < ARRAY_SIZE(info.eth_addr); i++) { \
+ sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
+ info.eth_addr[i][5], \
+ info.eth_addr[i][4], \
+ info.eth_addr[i][3], \
+ info.eth_addr[i][2], \
+ info.eth_addr[i][1], \
+ info.eth_addr[i][0]); \
+ \
+ if (i) \
+ sprintf(ethname, "eth%daddr", i); \
+ else \
+ sprintf(ethname, "ethaddr"); \
+ printf("Setting %s from EEPROM with %s\n", ethname, buf);\
+ setenv(ethname, buf); \
+ } \
+} while (0)
+#endif
+
#endif /* __TAM3517_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TEC) # "
-#define CONFIG_TEGRA20_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
+#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD /* UARTD: debug UART */
+#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ENV_IS_NOWHERE
-
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NV_PA_NAND_BASE
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
+
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
* MA 02111-1307 USA
*/
-#ifndef __TEGRA20_COMMON_POST_H
-#define __TEGRA20_COMMON_POST_H
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
#ifdef CONFIG_BOOTCOMMAND
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
- TEGRA20_DEVICE_SETTINGS \
+ TEGRA_DEVICE_SETTINGS \
"fdt_load=0x01000000\0" \
"fdt_high=01100000\0" \
BOOTCMDS_COMMON
#ifdef CONFIG_GENERIC_MMC
#undef CONFIG_GENERIC_MMC
#endif
-#ifdef CONFIG_TEGRA20_MMC
-#undef CONFIG_TEGRA20_MMC
+#ifdef CONFIG_TEGRA_MMC
+#undef CONFIG_TEGRA_MMC
#endif
#ifdef CONFIG_CMD_MMC
#undef CONFIG_CMD_MMC
#endif /* CONFIG_SPL_BUILD */
-#endif /* __TEGRA20_COMMON_POST_H */
+#endif /* __TEGRA_COMMON_POST_H */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
/* Environment information, boards can override if required */
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define TEGRA20_DEVICE_SETTINGS "stdin=serial\0" \
- "stdout=serial\0" \
- "stderr=serial\0"
+#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0"
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-#define CONFIG_SYS_MEMTEST_START (TEGRA20_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
+#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_TEXT_BASE 0x0010c000
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
+#define CONFIG_SYS_NAND_SELF_INIT
+
#endif /* __TEGRA20_COMMON_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TrimSlice) # "
-#define CONFIG_TEGRA20_BOARD_STRING "Compulab Trimslice"
+#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_GPU
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Ventana) # "
-#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Ventana"
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTD
+#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* High-level configuration options */
#define V_PROMPT "Tegra20 (Whistler) # "
-#define CONFIG_TEGRA20_BOARD_STRING "NVIDIA Whistler"
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_TEGRA20_ENABLE_UARTA
-#define CONFIG_TEGRA20_UARTA_UAA_UAB
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER
* particular card is standard practice as far as I know.
*/
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
-#include "tegra20-common-post.h"
+#include "tegra-common-post.h"
#endif /* __CONFIG_H */
COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */
COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */
+ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_COUNT,
};
* consecutive order.
*/
struct nand_buffers {
- uint8_t ecccalc[NAND_MAX_OOBSIZE];
- uint8_t ecccode[NAND_MAX_OOBSIZE];
- uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+ uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+ uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+ ARCH_DMA_MINALIGN)];
};
/**
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
+#define EXT_CSD_BOOT_MULT 226 /* RO */
/*
* EXT_CSD field definitions
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
+ COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
projects / kernel / u-boot.git / commitdiff