if (reloc_override)
inst.reloc.type = reloc_override;
+ else if (thumb_mode)
+ inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
else
inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
return SUCCESS;
static void
do_iwmmxt_wldstbh (void)
{
+ int reloc;
inst.instruction |= inst.operands[0].reg << 12;
inst.reloc.exp.X_add_number *= 4;
- encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
+ if (thumb_mode)
+ reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
+ else
+ reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+ encode_arm_cp_address (1, TRUE, FALSE, reloc);
}
static void
if (thumb_mode)
{
+ unsigned long variant;
+
+ variant = cpu_variant;
+ /* Only allow coprocessor instructions on Thumb-2 capable devices. */
+ if ((variant & ARM_EXT_V6T2) == 0)
+ variant &= ARM_ANY;
/* Check that this instruction is supported for this CPU. */
- if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0)
+ if (thumb_mode == 1 && (opcode->tvariant & variant) == 0)
{
as_bad (_("selected processor does not support `%s'"), str);
return;
#define C3(mnem, op, nops, ops, ae) \
{ #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
+#define cCE(mnem, op, nops, ops, ae) \
+ { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
+
+#define cC3(mnem, op, nops, ops, ae) \
+ { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
+
#define xCM_(m1, m2, m3, op, nops, ops, ae) \
{ #m1 #m2 #m3, OPS##nops ops, \
sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
- CE(wfs, e200110, 1, (RR), rd),
- CE(rfs, e300110, 1, (RR), rd),
- CE(wfc, e400110, 1, (RR), rd),
- CE(rfc, e500110, 1, (RR), rd),
-
- C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
- C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
- C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
- C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
-
- C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
- C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
- C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
- C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
-
- C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
- C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
- C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
- C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
- C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
- C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
- C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
- C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
- C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
- C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
- C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
- C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
-
- C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
- C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
- C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
- C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
- C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
- C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
- C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
- C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
- C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
- C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
- C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
- C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
-
- C3(abss, e208100, 2, (RF, RF_IF), rd_rm),
- C3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
- C3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
- C3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
- C3(absd, e208180, 2, (RF, RF_IF), rd_rm),
- C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
- C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
- C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
- C3(abse, e288100, 2, (RF, RF_IF), rd_rm),
- C3(absep, e288120, 2, (RF, RF_IF), rd_rm),
- C3(absem, e288140, 2, (RF, RF_IF), rd_rm),
- C3(absez, e288160, 2, (RF, RF_IF), rd_rm),
-
- C3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
- C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
- C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
- C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
- C3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
- C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
- C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
- C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
- C3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
- C3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
- C3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
- C3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
-
- C3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
- C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
- C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
- C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
- C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
- C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
- C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
- C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
- C3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
- C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
- C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
- C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
-
- C3(logs, e508100, 2, (RF, RF_IF), rd_rm),
- C3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
- C3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
- C3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
- C3(logd, e508180, 2, (RF, RF_IF), rd_rm),
- C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
- C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
- C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
- C3(loge, e588100, 2, (RF, RF_IF), rd_rm),
- C3(logep, e588120, 2, (RF, RF_IF), rd_rm),
- C3(logem, e588140, 2, (RF, RF_IF), rd_rm),
- C3(logez, e588160, 2, (RF, RF_IF), rd_rm),
-
- C3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
- C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
- C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
- C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
- C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
- C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
- C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
- C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
- C3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
- C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
- C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
- C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
-
- C3(exps, e708100, 2, (RF, RF_IF), rd_rm),
- C3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
- C3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
- C3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
- C3(expd, e708180, 2, (RF, RF_IF), rd_rm),
- C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
- C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
- C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
- C3(expe, e788100, 2, (RF, RF_IF), rd_rm),
- C3(expep, e788120, 2, (RF, RF_IF), rd_rm),
- C3(expem, e788140, 2, (RF, RF_IF), rd_rm),
- C3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
-
- C3(sins, e808100, 2, (RF, RF_IF), rd_rm),
- C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
- C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
- C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
- C3(sind, e808180, 2, (RF, RF_IF), rd_rm),
- C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
- C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
- C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
- C3(sine, e888100, 2, (RF, RF_IF), rd_rm),
- C3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
- C3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
- C3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
-
- C3(coss, e908100, 2, (RF, RF_IF), rd_rm),
- C3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
- C3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
- C3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
- C3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
- C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
- C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
- C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
- C3(cose, e988100, 2, (RF, RF_IF), rd_rm),
- C3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
- C3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
- C3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
-
- C3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
- C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
- C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
- C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
- C3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
- C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
- C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
- C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
- C3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
- C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
- C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
- C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
-
- C3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
- C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
- C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
- C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
- C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
- C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
- C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
- C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
- C3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
- C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
- C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
- C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
-
- C3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
- C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
- C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
- C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
- C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
- C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
- C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
- C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
- C3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
- C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
- C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
- C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
-
- C3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
- C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
- C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
- C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
- C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
- C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
- C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
- C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
- C3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
- C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
- C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
- C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
-
- C3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
- C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
- C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
- C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
- C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
- C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
- C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
- C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
- C3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
- C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
- C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
- C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
-
- C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
- C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
- C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
- C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
- C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
- C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
- C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
- C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
- C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
- C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
- C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
- C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
-
- C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
- C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
-
- CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
+ cCE(wfs, e200110, 1, (RR), rd),
+ cCE(rfs, e300110, 1, (RR), rd),
+ cCE(wfc, e400110, 1, (RR), rd),
+ cCE(rfc, e500110, 1, (RR), rd),
+
+ cC3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
+
+ cC3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
+ cC3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
+
+ cC3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
+ cC3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
+ cC3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(abss, e208100, 2, (RF, RF_IF), rd_rm),
+ cC3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
+ cC3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
+ cC3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
+ cC3(absd, e208180, 2, (RF, RF_IF), rd_rm),
+ cC3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(abse, e288100, 2, (RF, RF_IF), rd_rm),
+ cC3(absep, e288120, 2, (RF, RF_IF), rd_rm),
+ cC3(absem, e288140, 2, (RF, RF_IF), rd_rm),
+ cC3(absez, e288160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
+ cC3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
+ cC3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
+ cC3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
+ cC3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
+ cC3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
+ cC3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
+ cC3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
+ cC3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
+ cC3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(logs, e508100, 2, (RF, RF_IF), rd_rm),
+ cC3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
+ cC3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
+ cC3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
+ cC3(logd, e508180, 2, (RF, RF_IF), rd_rm),
+ cC3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(loge, e588100, 2, (RF, RF_IF), rd_rm),
+ cC3(logep, e588120, 2, (RF, RF_IF), rd_rm),
+ cC3(logem, e588140, 2, (RF, RF_IF), rd_rm),
+ cC3(logez, e588160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
+ cC3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
+ cC3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(exps, e708100, 2, (RF, RF_IF), rd_rm),
+ cC3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
+ cC3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
+ cC3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
+ cC3(expd, e708180, 2, (RF, RF_IF), rd_rm),
+ cC3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(expe, e788100, 2, (RF, RF_IF), rd_rm),
+ cC3(expep, e788120, 2, (RF, RF_IF), rd_rm),
+ cC3(expem, e788140, 2, (RF, RF_IF), rd_rm),
+ cC3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(sins, e808100, 2, (RF, RF_IF), rd_rm),
+ cC3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
+ cC3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
+ cC3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
+ cC3(sind, e808180, 2, (RF, RF_IF), rd_rm),
+ cC3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(sine, e888100, 2, (RF, RF_IF), rd_rm),
+ cC3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
+ cC3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
+ cC3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(coss, e908100, 2, (RF, RF_IF), rd_rm),
+ cC3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
+ cC3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
+ cC3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
+ cC3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
+ cC3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(cose, e988100, 2, (RF, RF_IF), rd_rm),
+ cC3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
+ cC3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
+ cC3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
+ cC3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
+ cC3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
+ cC3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
+ cC3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
+ cC3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
+ cC3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
+ cC3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
+ cC3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
+ cC3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
+ cC3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
+ cC3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
+ cC3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
+ cC3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
+ cC3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
+ cC3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
+ cC3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
+ cC3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
+ cC3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
+ cC3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
+ cC3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
+ cC3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
+ cC3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
+ cC3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
+ cC3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
+ cC3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
+ cC3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
+ cC3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
+ cC3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
+ cC3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
+ cC3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
+ cC3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
+ cC3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
+ cC3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
+ cC3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
+ cC3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
+ cC3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
+ cC3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
+ cC3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
+ cC3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
+ cC3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
+ cC3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
+ cC3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
+
+ cC3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cC3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cC3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
- CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
+ cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
- C3(flts, e000110, 2, (RF, RR), rn_rd),
- C3(fltsp, e000130, 2, (RF, RR), rn_rd),
- C3(fltsm, e000150, 2, (RF, RR), rn_rd),
- C3(fltsz, e000170, 2, (RF, RR), rn_rd),
- C3(fltd, e000190, 2, (RF, RR), rn_rd),
- C3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
- C3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
- C3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
- C3(flte, e080110, 2, (RF, RR), rn_rd),
- C3(fltep, e080130, 2, (RF, RR), rn_rd),
- C3(fltem, e080150, 2, (RF, RR), rn_rd),
- C3(fltez, e080170, 2, (RF, RR), rn_rd),
+ cC3(flts, e000110, 2, (RF, RR), rn_rd),
+ cC3(fltsp, e000130, 2, (RF, RR), rn_rd),
+ cC3(fltsm, e000150, 2, (RF, RR), rn_rd),
+ cC3(fltsz, e000170, 2, (RF, RR), rn_rd),
+ cC3(fltd, e000190, 2, (RF, RR), rn_rd),
+ cC3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
+ cC3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
+ cC3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
+ cC3(flte, e080110, 2, (RF, RR), rn_rd),
+ cC3(fltep, e080130, 2, (RF, RR), rn_rd),
+ cC3(fltem, e080150, 2, (RF, RR), rn_rd),
+ cC3(fltez, e080170, 2, (RF, RR), rn_rd),
/* The implementation of the FIX instruction is broken on some
assemblers, in that it accepts a precision specifier as well as a
rounding specifier, despite the fact that this is meaningless.
To be more compatible, we accept it as well, though of course it
does not set any bits. */
- CE(fix, e100110, 2, (RR, RF), rd_rm),
- C3(fixp, e100130, 2, (RR, RF), rd_rm),
- C3(fixm, e100150, 2, (RR, RF), rd_rm),
- C3(fixz, e100170, 2, (RR, RF), rd_rm),
- C3(fixsp, e100130, 2, (RR, RF), rd_rm),
- C3(fixsm, e100150, 2, (RR, RF), rd_rm),
- C3(fixsz, e100170, 2, (RR, RF), rd_rm),
- C3(fixdp, e100130, 2, (RR, RF), rd_rm),
- C3(fixdm, e100150, 2, (RR, RF), rd_rm),
- C3(fixdz, e100170, 2, (RR, RF), rd_rm),
- C3(fixep, e100130, 2, (RR, RF), rd_rm),
- C3(fixem, e100150, 2, (RR, RF), rd_rm),
- C3(fixez, e100170, 2, (RR, RF), rd_rm),
+ cCE(fix, e100110, 2, (RR, RF), rd_rm),
+ cC3(fixp, e100130, 2, (RR, RF), rd_rm),
+ cC3(fixm, e100150, 2, (RR, RF), rd_rm),
+ cC3(fixz, e100170, 2, (RR, RF), rd_rm),
+ cC3(fixsp, e100130, 2, (RR, RF), rd_rm),
+ cC3(fixsm, e100150, 2, (RR, RF), rd_rm),
+ cC3(fixsz, e100170, 2, (RR, RF), rd_rm),
+ cC3(fixdp, e100130, 2, (RR, RF), rd_rm),
+ cC3(fixdm, e100150, 2, (RR, RF), rd_rm),
+ cC3(fixdz, e100170, 2, (RR, RF), rd_rm),
+ cC3(fixep, e100130, 2, (RR, RF), rd_rm),
+ cC3(fixem, e100150, 2, (RR, RF), rd_rm),
+ cC3(fixez, e100170, 2, (RR, RF), rd_rm),
/* Instructions that were new with the real FPA, call them V2. */
#undef ARM_VARIANT
#define ARM_VARIANT FPU_FPA_EXT_V2
- CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
- C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cC3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cC3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cC3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cC3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
/* Moves and type conversions. */
- CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
- CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
- CE(fmstat, ef1fa10, 0, (), noargs),
- CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
- CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
+ cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
+ cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
+ cCE(fmstat, ef1fa10, 0, (), noargs),
+ cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
+ cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
/* Memory operations. */
- CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
- CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
- CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
- CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
- CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
- CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
- CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
+ cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
+ cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
+ cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
+ cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
+ cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
/* Monadic operations. */
- CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
/* Dyadic operations. */
- CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
- CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
+ cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
/* Comparisons. */
- CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
- CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
- CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
+ cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
+ cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
+ cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
/* Moves and type conversions. */
- CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
- CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
- CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
- CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
- CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
- CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
- CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
- CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
+ cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
+ cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
+ cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
+ cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
+ cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
+ cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
+ cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
/* Memory operations. */
- CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
- CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
- CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
- CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
- CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
+ cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
+ cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
+ cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
/* Monadic operations. */
- CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
- CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
- CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
+ cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
+ cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
+ cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
/* Dyadic operations. */
- CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
- CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
+ cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
/* Comparisons. */
- CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
- CE(fcmpzd, eb50b40, 1, (RVD), rd),
- CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
- CE(fcmpezd, eb50bc0, 1, (RVD), rd),
+ cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
+ cCE(fcmpzd, eb50b40, 1, (RVD), rd),
+ cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
+ cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
#undef ARM_VARIANT
#define ARM_VARIANT FPU_VFP_EXT_V2
- CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
- CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
- CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
- CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
+ cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
+ cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
+ cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
+ cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
- CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
- CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
- CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
+ cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
+ cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
- CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
- CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
- CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
- CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
- CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
- CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
- CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
- CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
- CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
- CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
- CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
- CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
- CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
- CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
- CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
- CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
- CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
- CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
- CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
- CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
- CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
- CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
- CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
- CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
- CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
- CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
- CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
- CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
- CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
- CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
- CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
- CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
- CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
- CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
- CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
- CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
- CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
+ cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
+ cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
+ cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
+ cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
+ cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
+ cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
+ cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
+ cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
+ cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
+ cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
+ cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
+ cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
+ cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
+ cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
+ cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
+ cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
+ cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
+ cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
+ cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
+ cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
+ cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
+ cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
+ cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
+ cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
+ cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
+ cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
+ cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
+ cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
+ cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
+ cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
+ cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
+ cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
+ cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
#undef ARM_VARIANT
#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
- CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
- CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
- CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
- CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
- CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
- CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
- CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
- CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
- CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
- CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
- CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
- CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
- CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
- CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
- CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
- CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
- CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
- CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
- CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
- CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
- CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
- CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
- CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
- CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
- CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
- CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
- CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
- CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
- CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
- CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
- CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
- CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
- CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
- CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
- CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
- CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
- CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
- CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
- CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
- CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
- CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
- CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
- CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
- CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
- CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
- CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
- CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
- CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
- CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
- CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
- CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
- CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
- CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
- CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
- CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
- CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
- CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
- CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
- CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
- CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
- CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
- CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
- CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
- CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
- CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
- CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
- CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
- CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
- CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
- CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
+ cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
+ cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
+ cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
+ cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
+ cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
+ cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
+ cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
+ cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
+ cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
+ cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
+ cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
+ cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
+ cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
+ cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
+ cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
+ cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
+ cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
+ cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
+ cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
+ cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
+ cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
+ cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
+ cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
+ cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
+ cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
+ cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
+ cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
+ cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
+ cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
+ cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
+ cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
+ cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
+ cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
+ cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
+ cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
+ cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
+ cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
+ cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
+ cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
+ cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
+ cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
+ cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
+ cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
+ cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
+ cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
+ cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
+ cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
+ cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
+ cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
+ cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
+ cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
+ cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
+ cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
+ cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
+ cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
+ cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
+ cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
+ cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
+ cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
+ cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
+ cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
+ cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
+ cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
+ cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
+ cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
+ cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
#undef TUE
#undef TUF
#undef TCC
+#undef cCE
+#undef cC3
#undef CE
#undef CM
#undef UE
case BFD_RELOC_ARM_THUMB_OFFSET:
case BFD_RELOC_ARM_T32_OFFSET_IMM:
case BFD_RELOC_ARM_T32_ADD_PC12:
+ case BFD_RELOC_ARM_T32_CP_OFF_IMM:
return (base + 4) & ~3;
/* Thumb branches are simply offset by +4. */
return value;
}
+/* Read a 32-bit thumb instruction from buf. */
+static unsigned long
+get_thumb32_insn (char * buf)
+{
+ unsigned long insn;
+ insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
+ insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+
+ return insn;
+}
+
+/* Write a 32-bit thumb instruction to buf. */
+static void
+put_thumb32_insn (char * buf, unsigned long insn)
+{
+ md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
+ md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
+}
+
void
md_apply_fix (fixS * fixP,
valueT * valP,
#endif
case BFD_RELOC_ARM_CP_OFF_IMM:
+ case BFD_RELOC_ARM_T32_CP_OFF_IMM:
if (value < -1023 || value > 1023 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
sign = value >= 0;
if (value < 0)
value = -value;
- newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
+ if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
+ || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
+ newval = md_chars_to_number (buf, INSN_SIZE);
+ else
+ newval = get_thumb32_insn (buf);
+ newval &= 0xff7fff00;
newval |= (value >> 2) | (sign ? INDEX_UP : 0);
if (value == 0)
newval &= ~WRITE_BACK;
- md_number_to_chars (buf, newval, INSN_SIZE);
+ if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
+ || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
+ md_number_to_chars (buf, newval, INSN_SIZE);
+ else
+ put_thumb32_insn (buf, newval);
break;
case BFD_RELOC_ARM_CP_OFF_IMM_S2:
+ case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
if (value < -255 || value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("co-processor offset out of range"));
case BFD_RELOC_ARM_SWI: type = "SWI"; break;
case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
+ case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
const char *assembler; /* How to disassemble this insn. */
};
-/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
- ordered: they must be searched linearly from the top to obtain a correct
- match. */
-
-/* print_insn_arm recognizes the following format control codes:
+/* print_insn_coprocessor recognizes the following format control codes:
%% %
- %a print address for ldr/str instruction
- %s print address for ldr/str halfword/signextend instruction
- %b print branch destination
%c print condition code (always bits 28-31)
- %m print register mask for ldm/stm instruction
- %o print operand2 (immediate or register + shift)
- %p print 'p' iff bits 12-15 are 15
- %t print 't' iff bit 21 set and bit 24 clear
%A print address for ldc/stc/ldf/stf instruction
- %B print arm BLX(1) destination
%I print cirrus signed shift immediate: bits 0..3|4..6
- %C print the PSR sub type.
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
- %<bitfield>W print the bitfield plus one in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>f print a floating point constant if >7 else a
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
- %l like 'A' except use byte offsets for 'B' & 'H' versions.
+ %l like 'A' except use byte offsets for 'B' & 'H'
+ versions. */
- %e print arm SMI operand (bits 0..7,8..19).
- %E print the LSB and WIDTH fields of a BFI or BFC instruction.
- %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
+/* Common coprocessor opcodes shared between Arm and Thumb-2. */
-static const struct opcode32 arm_opcodes[] =
+static const struct opcode32 coprocessor_opcodes[] =
{
- /* ARM instructions. */
- {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
- {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
- {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
-
- /* ARM V6T2 instructions. */
- {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
- {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
- {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
- {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
- {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
- {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
- {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
-
- /* ARM V6Z instructions. */
- {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
-
- /* ARM V6K instructions. */
- {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
- {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
-
- /* ARM V6K NOP hints. */
- {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
- {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
- {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
- {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
- {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
-
- /* ARM V6 instructions. */
- {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
- {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
- {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
- {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
- {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
- {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
- {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
- {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
- {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
- {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
- {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
- {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
- {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
- {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
- {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
- {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
- {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
- {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
- {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
- {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
- {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
- {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
- {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
-
- /* V5J instruction. */
- {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
-
/* XScale instructions. */
{ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
{ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
- /* V5 Instructions. */
- {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
- {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
- {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
- {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
- {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
-
- /* V5E "El Segundo" Instructions. */
- {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
- {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
- {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
- {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
-
- {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
-
- {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
-
- /* ARM Instructions. */
- {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
- {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
- {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
- {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
- {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
- {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
- {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
- {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
- {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
- {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
- {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
- {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
- {ARM_EXT_V1, 0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
-
- /* Floating point coprocessor (FPA) instructions */
- {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
- {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
- {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
- {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
- {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
- {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* Floating point coprocessor (FPA) instructions */
+ {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
+ {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
+ {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
+ {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
+ {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
+ {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
+ {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
+ {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
+ {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
+ {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
+ {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
/* Floating point coprocessor (VFP) instructions */
{FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"},
{ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
{ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
- /* The rest. */
- {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
- {0, 0x00000000, 0x00000000, 0}
+ /* V6 coprocessor instructions */
+ {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+ {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+
+ /* V5 coprocessor instructions */
+ {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
+ {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
+ {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+ {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+
};
-/* print_insn_thumb16 recognizes the following format control codes:
+/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
+ ordered: they must be searched linearly from the top to obtain a correct
+ match. */
+
+/* print_insn_arm recognizes the following format control codes:
+
+ %% %
+
+ %a print address for ldr/str instruction
+ %s print address for ldr/str halfword/signextend instruction
+ %b print branch destination
+ %c print condition code (always bits 28-31)
+ %m print register mask for ldm/stm instruction
+ %o print operand2 (immediate or register + shift)
+ %p print 'p' iff bits 12-15 are 15
+ %t print 't' iff bit 21 set and bit 24 clear
+ %B print arm BLX(1) destination
+ %C print the PSR sub type.
+
+ %<bitfield>r print as an ARM register
+ %<bitfield>d print the bitfield in decimal
+ %<bitfield>W print the bitfield plus one in decimal
+ %<bitfield>x print the bitfield in hex
+ %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
- %S print Thumb register (bits 3..5 as high number if bit 6 set)
- %D print Thumb register (bits 0..2 as high number if bit 7 set)
- %<bitfield>I print bitfield as a signed decimal
- (top bit of range being the sign bit)
- %N print Thumb register mask (with LR)
- %O print Thumb register mask (with PC)
- %M print Thumb register mask
- %b print CZB's 6-bit unsigned branch destination
- %s print Thumb right-shift immediate (6..10; 0 == 32).
- %<bitfield>r print bitfield as an ARM register
- %<bitfield>d print bitfield as a decimal
- %<bitfield>H print (bitfield * 2) as a decimal
- %<bitfield>W print (bitfield * 4) as a decimal
- %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
- %<bitfield>B print Thumb branch destination (signed displacement)
- %<bitfield>c print bitfield as a condition code
%<bitnum>'c print specified char iff bit is one
- %<bitnum>?ab print a if bit is one else print b. */
+ %<bitnum>`c print specified char iff bit is zero
+ %<bitnum>?ab print a if bit is one else print b
-static const struct opcode16 thumb_opcodes[] =
-{
- /* Thumb instructions. */
+ %e print arm SMI operand (bits 0..7,8..19).
+ %E print the LSB and WIDTH fields of a BFI or BFC instruction.
+ %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
- /* ARM V6K no-argument instructions. */
- {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
- {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
- {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
- {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
- {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
- {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"},
+static const struct opcode32 arm_opcodes[] =
+{
+ /* ARM instructions. */
+ {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
+ {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
+ {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
+ {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
/* ARM V6T2 instructions. */
- {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b"},
- {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b"},
- {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"},
- {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"},
+ {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
+ {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
+ {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
+ {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
+ {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
+ {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
+ {ARM_EXT_V6T2, 0x03ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
+ {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
- /* ARM V6. */
- {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
- {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
- {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble"},
- {ARM_EXT_V6, 0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},
+ /* ARM V6Z instructions. */
+ {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smi%c\t%e"},
- /* ARM V5 ISA extends Thumb. */
- {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"},
- /* This is BLX(2). BLX(1) is a 32-bit instruction. */
- {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
- /* ARM V4T ISA (Thumb v1). */
- {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
- /* Format 4. */
- {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"},
- /* format 13 */
- {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"},
- {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"},
- /* format 5 */
- {ARM_EXT_V4T, 0x4700, 0xFF80, "bx\t%S"},
- {ARM_EXT_V4T, 0x4400, 0xFF00, "add\t%D, %S"},
- {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp\t%D, %S"},
- {ARM_EXT_V4T, 0x4600, 0xFF00, "mov\t%D, %S"},
- /* format 14 */
- {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"},
- {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
- /* format 2 */
- {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
- {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
- {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
- {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
- /* format 8 */
- {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
- /* format 7 */
- {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
- /* format 1 */
- {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"},
- {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"},
- {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"},
- /* format 3 */
- {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"},
- /* format 6 */
- {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
- /* format 9 */
- {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
- {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
- {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
- {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
- /* format 10 */
- {ARM_EXT_V4T, 0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
- {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
- /* format 11 */
- {ARM_EXT_V4T, 0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
- {ARM_EXT_V4T, 0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
- /* format 12 */
- {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
- {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
- /* format 15 */
- {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"},
- {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"},
- /* format 17 */
- {ARM_EXT_V4T, 0xDF00, 0xFF00, "swi\t%0-7d"},
- /* format 16 */
- {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"},
- /* format 18 */
- {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"},
+ /* ARM V6K instructions. */
+ {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
+ {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
+ {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
+ {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
+ {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
+ {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
+ {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
- /* The E800 .. FFFF range is unconditionally redirected to the
- 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
- are processed via that table. Thus, we can never encounter a
- bare "second half of BL/BLX(1)" instruction here. */
- {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
- {0, 0, 0, 0}
-};
+ /* ARM V6K NOP hints. */
+ {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
+ {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
+ {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
+ {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
+ {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
-/* Thumb32 opcodes use the same table structure as the ARM opcodes.
- We adopt the convention that hw1 is the high 16 bits of .value and
- .mask, hw2 the low 16 bits.
+ /* ARM V6 instructions. */
+ {ARM_EXT_V6, 0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
+ {ARM_EXT_V6, 0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
+ {ARM_EXT_V6, 0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
+ {ARM_EXT_V6, 0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
+ {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
+ {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
+ {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
+ {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
+ {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
+ {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
+ {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
+ {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
+ {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
+ {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
+ {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
+ {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
+ {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
+ {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
+ {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
+ {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
+ {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
+ {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
+ {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
+ {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
- print_insn_thumb32 recognizes the following format control codes:
+ /* V5J instruction. */
+ {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
- %% %
+ /* V5 Instructions. */
+ {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
+ {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
+ {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
- %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
- %M print a modified 12-bit immediate (same location)
- %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
- %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
- %S print a possibly-shifted Rm
+ /* V5E "El Segundo" Instructions. */
+ {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
+ {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
+ {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
+ {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- %a print the address of a plain load/store
- %A print the address of a coprocessor load/store
- %w print the width and signedness of a core load/store
- %m print register mask for ldm/stm
+ {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- %E print the lsb and width fields of a bfc/bfi instruction
- %F print the lsb and width fields of a sbfx/ubfx instruction
- %b print a conditional branch offset
- %B print an unconditional branch offset
- %s print the shift field of an SSAT instruction
- %R print the rotation field of an SXT instruction
+ {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- %<bitfield>d print bitfield in decimal
- %<bitfield>W print bitfield*4 in decimal
- %<bitfield>r print bitfield as an ARM register
- %<bitfield>c print bitfield as a condition code
+ {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
- %<bitnum>'c print "c" iff bit is one
- %<bitnum>`c print "c" iff bit is zero
- %<bitnum>?ab print "a" if bit is one, else "b"
+ {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
+ {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
- With one exception at the bottom (done because BL and BLX(1) need
- to come dead last), this table was machine-sorted first in
- decreasing order of number of bits set in the mask, then in
- increasing numeric order of mask, then in increasing numeric order
- of opcode. This order is not the clearest for a human reader, but
- is guaranteed never to catch a special-case bit pattern with a more
- general mask, which is important, because this instruction encoding
- makes heavy use of special-case bit patterns. */
-static const struct opcode32 thumb32_opcodes[] =
-{
- /* Instructions defined in the basic V6T2 set. */
- {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"},
- {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield.w"},
- {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe.w"},
- {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi.w"},
- {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev.w"},
- {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop.w\t{%0-7d}"},
+ {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
+ {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
+ {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
+ {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex"},
- {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f"},
- {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f"},
- {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj\t%16-19r"},
- {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb\t%16-19r%21'!"},
- {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia\t%16-19r%21'!"},
- {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff0ff, "mrs\t%8-11r, %20?CSPSR"},
- {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d"},
- {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb\t[%16-19r, %0-3r]"},
- {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh\t[%16-19r, %0-3r, lsl #1]"},
- {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d"},
- {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d"},
+ /* ARM Instructions. */
+ {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
+ {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
+ {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
+ {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
+ {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
+ {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
+ {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
+ {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
+ {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
+ {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
+ {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
+ {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
+ {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
+ {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
+ {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
+ {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
+ {ARM_EXT_V1, 0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
+
+ /* The rest. */
+ {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
+ {0, 0x00000000, 0x00000000, 0}
+};
+
+/* print_insn_thumb16 recognizes the following format control codes:
+
+ %S print Thumb register (bits 3..5 as high number if bit 6 set)
+ %D print Thumb register (bits 0..2 as high number if bit 7 set)
+ %<bitfield>I print bitfield as a signed decimal
+ (top bit of range being the sign bit)
+ %N print Thumb register mask (with LR)
+ %O print Thumb register mask (with PC)
+ %M print Thumb register mask
+ %b print CZB's 6-bit unsigned branch destination
+ %s print Thumb right-shift immediate (6..10; 0 == 32).
+ %<bitfield>r print bitfield as an ARM register
+ %<bitfield>d print bitfield as a decimal
+ %<bitfield>H print (bitfield * 2) as a decimal
+ %<bitfield>W print (bitfield * 4) as a decimal
+ %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
+ %<bitfield>B print Thumb branch destination (signed displacement)
+ %<bitfield>c print bitfield as a condition code
+ %<bitnum>'c print specified char iff bit is one
+ %<bitnum>?ab print a if bit is one else print b. */
+
+static const struct opcode16 thumb_opcodes[] =
+{
+ /* Thumb instructions. */
+
+ /* ARM V6K no-argument instructions. */
+ {ARM_EXT_V6K, 0xbf00, 0xffff, "nop"},
+ {ARM_EXT_V6K, 0xbf10, 0xffff, "yield"},
+ {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe"},
+ {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi"},
+ {ARM_EXT_V6K, 0xbf40, 0xffff, "sev"},
+ {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop\t{%4-7d}"},
+
+ /* ARM V6T2 instructions. */
+ {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b"},
+ {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b"},
+ {ARM_EXT_V6T2, 0xbf08, 0xff0f, "it\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf14, 0xff17, "it%3?te\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf04, 0xff17, "it%3?et\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf12, 0xff13, "it%3?te%2?te\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf02, 0xff13, "it%3?et%2?et\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf11, 0xff11, "it%3?te%2?te%1?te\t%4-7c"},
+ {ARM_EXT_V6T2, 0xbf01, 0xff11, "it%3?et%2?et%1?et\t%4-7c"},
+
+ /* ARM V6. */
+ {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
+ {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
+ {ARM_EXT_V6, 0x4600, 0xffc0, "mov\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble"},
+ {ARM_EXT_V6, 0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},
+ {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},
+
+ /* ARM V5 ISA extends Thumb. */
+ {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"},
+ /* This is BLX(2). BLX(1) is a 32-bit instruction. */
+ {ARM_EXT_V5T, 0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
+ /* ARM V4T ISA (Thumb v1). */
+ {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
+ /* Format 4. */
+ {ARM_EXT_V4T, 0x4000, 0xFFC0, "ands\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4040, 0xFFC0, "eors\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsls\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsrs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4100, 0xFFC0, "asrs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4140, 0xFFC0, "adcs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbcs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x41C0, 0xFFC0, "rors\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4240, 0xFFC0, "negs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4300, 0xFFC0, "orrs\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4340, 0xFFC0, "muls\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x4380, 0xFFC0, "bics\t%0-2r, %3-5r"},
+ {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvns\t%0-2r, %3-5r"},
+ /* format 13 */
+ {ARM_EXT_V4T, 0xB000, 0xFF80, "add\tsp, #%0-6W"},
+ {ARM_EXT_V4T, 0xB080, 0xFF80, "sub\tsp, #%0-6W"},
+ /* format 5 */
+ {ARM_EXT_V4T, 0x4700, 0xFF80, "bx\t%S"},
+ {ARM_EXT_V4T, 0x4400, 0xFF00, "add\t%D, %S"},
+ {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp\t%D, %S"},
+ {ARM_EXT_V4T, 0x4600, 0xFF00, "mov\t%D, %S"},
+ /* format 14 */
+ {ARM_EXT_V4T, 0xB400, 0xFE00, "push\t%N"},
+ {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
+ /* format 2 */
+ {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
+ {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
+ {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
+ {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
+ /* format 8 */
+ {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
+ {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
+ {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
+ /* format 7 */
+ {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
+ {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
+ /* format 1 */
+ {ARM_EXT_V4T, 0x0000, 0xF800, "lsls\t%0-2r, %3-5r, #%6-10d"},
+ {ARM_EXT_V4T, 0x0800, 0xF800, "lsrs\t%0-2r, %3-5r, %s"},
+ {ARM_EXT_V4T, 0x1000, 0xF800, "asrs\t%0-2r, %3-5r, %s"},
+ /* format 3 */
+ {ARM_EXT_V4T, 0x2000, 0xF800, "movs\t%8-10r, #%0-7d"},
+ {ARM_EXT_V4T, 0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
+ {ARM_EXT_V4T, 0x3000, 0xF800, "adds\t%8-10r, #%0-7d"},
+ {ARM_EXT_V4T, 0x3800, 0xF800, "subs\t%8-10r, #%0-7d"},
+ /* format 6 */
+ {ARM_EXT_V4T, 0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
+ /* format 9 */
+ {ARM_EXT_V4T, 0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
+ {ARM_EXT_V4T, 0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
+ {ARM_EXT_V4T, 0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
+ {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
+ /* format 10 */
+ {ARM_EXT_V4T, 0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
+ {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
+ /* format 11 */
+ {ARM_EXT_V4T, 0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
+ {ARM_EXT_V4T, 0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
+ /* format 12 */
+ {ARM_EXT_V4T, 0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
+ {ARM_EXT_V4T, 0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
+ /* format 15 */
+ {ARM_EXT_V4T, 0xC000, 0xF800, "stmia\t%8-10r!, %M"},
+ {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia\t%8-10r!, %M"},
+ /* format 17 */
+ {ARM_EXT_V4T, 0xDF00, 0xFF00, "swi\t%0-7d"},
+ /* format 16 */
+ {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B"},
+ /* format 18 */
+ {ARM_EXT_V4T, 0xE000, 0xF800, "b.n\t%0-10B"},
+
+ /* The E800 .. FFFF range is unconditionally redirected to the
+ 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
+ are processed via that table. Thus, we can never encounter a
+ bare "second half of BL/BLX(1)" instruction here. */
+ {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
+ {0, 0, 0, 0}
+};
+
+/* Thumb32 opcodes use the same table structure as the ARM opcodes.
+ We adopt the convention that hw1 is the high 16 bits of .value and
+ .mask, hw2 the low 16 bits.
+
+ print_insn_thumb32 recognizes the following format control codes:
+
+ %% %
+
+ %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
+ %M print a modified 12-bit immediate (same location)
+ %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
+ %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
+ %S print a possibly-shifted Rm
+
+ %a print the address of a plain load/store
+ %w print the width and signedness of a core load/store
+ %m print register mask for ldm/stm
+
+ %E print the lsb and width fields of a bfc/bfi instruction
+ %F print the lsb and width fields of a sbfx/ubfx instruction
+ %b print a conditional branch offset
+ %B print an unconditional branch offset
+ %s print the shift field of an SSAT instruction
+ %R print the rotation field of an SXT instruction
+
+ %<bitfield>d print bitfield in decimal
+ %<bitfield>W print bitfield*4 in decimal
+ %<bitfield>r print bitfield as an ARM register
+ %<bitfield>c print bitfield as a condition code
+
+ %<bitnum>'c print "c" iff bit is one
+ %<bitnum>`c print "c" iff bit is zero
+ %<bitnum>?ab print "a" if bit is one, else "b"
+
+ With one exception at the bottom (done because BL and BLX(1) need
+ to come dead last), this table was machine-sorted first in
+ decreasing order of number of bits set in the mask, then in
+ increasing numeric order of mask, then in increasing numeric order
+ of opcode. This order is not the clearest for a human reader, but
+ is guaranteed never to catch a special-case bit pattern with a more
+ general mask, which is important, because this instruction encoding
+ makes heavy use of special-case bit patterns. */
+static const struct opcode32 thumb32_opcodes[] =
+{
+ /* Instructions defined in the basic V6T2 set. */
+ {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop.w"},
+ {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield.w"},
+ {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe.w"},
+ {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi.w"},
+ {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev.w"},
+ {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop.w\t{%0-7d}"},
+
+ {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex"},
+ {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f"},
+ {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f"},
+ {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj\t%16-19r"},
+ {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb\t%16-19r%21'!"},
+ {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia\t%16-19r%21'!"},
+ {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff0ff, "mrs\t%8-11r, %20?CSPSR"},
+ {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d"},
+ {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb\t[%16-19r, %0-3r]"},
+ {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh\t[%16-19r, %0-3r, lsl #1]"},
+ {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d"},
+ {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d"},
{ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs\tpc, lr, #%0-7d"},
{ARM_EXT_V6T2, 0xf3808000, 0xffe0f0ff, "msr\t%20?CSPSR_%8'c%9'x%10's%11'f, %16-19r"},
{ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex\t%12-15r, [%16-19r]"},
{ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt\t%12-15r, %a"},
{ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat\t%8-11r, #%0-4d, %16-19r%s"},
{ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat\t%8-11r, #%0-4d, %16-19r%s"},
- {ARM_EXT_V6T2, 0xee000010, 0xef1000f0, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"},
- {ARM_EXT_V6T2, 0xee100010, 0xef1000f0, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d"},
{ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw\t%8-11r, %16-19r, %I"},
{ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw\t%8-11r, %J"},
{ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw\t%8-11r, %16-19r, %I"},
{ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's.w\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's\t%8-11r, %16-19r, %S"},
{ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
- {ARM_EXT_V6T2, 0xee000000, 0xef0000f0, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d"},
- {ARM_EXT_V6T2, 0xec400000, 0xeff00000, "mcrr%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V6T2, 0xec500000, 0xeff00000, "mrrc%28'2\tp%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's.w\t%8-11r, %16-19r, %M"},
{ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd\t%12-15r, %8-11r, [%16-19r]"},
{ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
{ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
- {ARM_EXT_V6T2, 0xee000010, 0xef100010, "mcr%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"},
- {ARM_EXT_V6T2, 0xee100010, 0xef100010, "mrc%28'2\tp%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, %5-7d"},
{ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w.w\t%12-15r, %a"},
{ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w.w\t%12-15r, %a"},
- {ARM_EXT_V6T2, 0xec000000, 0xee100000, "stc%28'2%22'l\tp%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V6T2, 0xec100000, 0xee100000, "ldc%28'2%22'l\tp%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V6T2, 0xee000000, 0xef000010, "cdp%28'2\tp%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, %5-7d"},
/* Filter out Bcc with cond=E or F, which are used for other instructions. */
{ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
{ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b"},
{ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b.w\t%B"},
- /* These have been 32-bit since the invention of Thumb. */
- {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx\t%B"},
- {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl\t%B"},
+ /* These have been 32-bit since the invention of Thumb. */
+ {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx\t%B"},
+ {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl\t%B"},
+
+ /* Fallback. */
+ {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
+ {0, 0, 0, 0}
+};
+
+static const char *const arm_conditional[] =
+{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
+ "hi", "ls", "ge", "lt", "gt", "le", "", "<und>"};
+
+static const char *const arm_fp_const[] =
+{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
+
+static const char *const arm_shift[] =
+{"lsl", "lsr", "asr", "ror"};
+
+typedef struct
+{
+ const char *name;
+ const char *description;
+ const char *reg_names[16];
+}
+arm_regname;
+
+static const arm_regname regnames[] =
+{
+ { "raw" , "Select raw register names",
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
+ { "gcc", "Select register names used by GCC",
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
+ { "std", "Select register names used in ARM's ISA documentation",
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
+ { "apcs", "Select register names used in the APCS",
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
+ { "atpcs", "Select register names used in the ATPCS",
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
+ { "special-atpcs", "Select special register names used in the ATPCS",
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
+};
+
+static const char *const iwmmxt_wwnames[] =
+{"b", "h", "w", "d"};
+
+static const char *const iwmmxt_wwssnames[] =
+{"b", "bus", "b", "bss",
+ "h", "hus", "h", "hss",
+ "w", "wus", "w", "wss",
+ "d", "dus", "d", "dss"
+};
+
+static const char *const iwmmxt_regnames[] =
+{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
+ "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
+};
+
+static const char *const iwmmxt_cregnames[] =
+{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
+ "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
+};
+
+/* Default to GCC register name set. */
+static unsigned int regname_selected = 1;
+
+#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
+#define arm_regnames regnames[regname_selected].reg_names
+
+static bfd_boolean force_thumb = FALSE;
+
+\f
+/* Functions. */
+int
+get_arm_regname_num_options (void)
+{
+ return NUM_ARM_REGNAMES;
+}
+
+int
+set_arm_regname_option (int option)
+{
+ int old = regname_selected;
+ regname_selected = option;
+ return old;
+}
+
+int
+get_arm_regnames (int option, const char **setname, const char **setdescription,
+ const char *const **register_names)
+{
+ *setname = regnames[option].name;
+ *setdescription = regnames[option].description;
+ *register_names = regnames[option].reg_names;
+ return 16;
+}
+
+static void
+arm_decode_shift (long given, fprintf_ftype func, void *stream)
+{
+ func (stream, "%s", arm_regnames[given & 0xf]);
+
+ if ((given & 0xff0) != 0)
+ {
+ if ((given & 0x10) == 0)
+ {
+ int amount = (given & 0xf80) >> 7;
+ int shift = (given & 0x60) >> 5;
+
+ if (amount == 0)
+ {
+ if (shift == 3)
+ {
+ func (stream, ", rrx");
+ return;
+ }
+
+ amount = 32;
+ }
+
+ func (stream, ", %s #%d", arm_shift[shift], amount);
+ }
+ else
+ func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
+ arm_regnames[(given & 0xf00) >> 8]);
+ }
+}
+
+/* Print one coprocessor instruction on INFO->STREAM.
+ Return TRUE if the instuction matched, FALSE if this is not a
+ recognised coprocessor instruction. */
+
+static bfd_boolean
+print_insn_coprocessor (struct disassemble_info *info, long given,
+ bfd_boolean thumb)
+{
+ const struct opcode32 *insn;
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+ unsigned long mask;
+ unsigned long value;
+
+ for (insn = coprocessor_opcodes; insn->assembler; insn++)
+ {
+ if (insn->value == FIRST_IWMMXT_INSN
+ && info->mach != bfd_mach_arm_XScale
+ && info->mach != bfd_mach_arm_iWMMXt)
+ insn = insn + IWMMXT_INSN_COUNT;
+
+ mask = insn->mask;
+ value = insn->value;
+ if (thumb)
+ {
+ /* The high 4 bits are 0xe for Arm conditional instructions, and
+ 0xe for arm unconditional instructions. The rest of the
+ encoding is the same. */
+ mask |= 0xf0000000;
+ value |= 0xe0000000;
+ }
+ else
+ {
+ /* Only match unconditional instuctions against unconditional
+ patterns. */
+ if ((given & 0xf0000000) == 0xf0000000)
+ mask |= 0xf0000000;
+ }
+ if ((given & mask) == value)
+ {
+ const char *c;
+
+ for (c = insn->assembler; *c; c++)
+ {
+ if (*c == '%')
+ {
+ switch (*++c)
+ {
+ case '%':
+ func (stream, "%%");
+ break;
+
+ case 'A':
+ func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+
+ if ((given & (1 << 24)) != 0)
+ {
+ int offset = given & 0xff;
+
+ if (offset)
+ func (stream, ", #%s%d]%s",
+ ((given & 0x00800000) == 0 ? "-" : ""),
+ offset * 4,
+ ((given & 0x00200000) != 0 ? "!" : ""));
+ else
+ func (stream, "]");
+ }
+ else
+ {
+ int offset = given & 0xff;
+
+ func (stream, "]");
+
+ if (given & (1 << 21))
+ {
+ if (offset)
+ func (stream, ", #%s%d",
+ ((given & 0x00800000) == 0 ? "-" : ""),
+ offset * 4);
+ }
+ else
+ func (stream, ", {%d}", offset);
+ }
+ break;
+
+ case 'c':
+ func (stream, "%s",
+ arm_conditional [(given >> 28) & 0xf]);
+ break;
+
+ case 'I':
+ /* Print a Cirrus/DSP shift immediate. */
+ /* Immediates are 7bit signed ints with bits 0..3 in
+ bits 0..3 of opcode and bits 4..6 in bits 5..7
+ of opcode. */
+ {
+ int imm;
+
+ imm = (given & 0xf) | ((given & 0xe0) >> 1);
+
+ /* Is ``imm'' a negative number? */
+ if (imm & 0x40)
+ imm |= (-1 << 7);
+
+ func (stream, "%d", imm);
+ }
+
+ break;
+
+ case 'F':
+ switch (given & 0x00408000)
+ {
+ case 0:
+ func (stream, "4");
+ break;
+ case 0x8000:
+ func (stream, "1");
+ break;
+ case 0x00400000:
+ func (stream, "2");
+ break;
+ default:
+ func (stream, "3");
+ }
+ break;
+
+ case 'P':
+ switch (given & 0x00080080)
+ {
+ case 0:
+ func (stream, "s");
+ break;
+ case 0x80:
+ func (stream, "d");
+ break;
+ case 0x00080000:
+ func (stream, "e");
+ break;
+ default:
+ func (stream, _("<illegal precision>"));
+ break;
+ }
+ break;
+ case 'Q':
+ switch (given & 0x00408000)
+ {
+ case 0:
+ func (stream, "s");
+ break;
+ case 0x8000:
+ func (stream, "d");
+ break;
+ case 0x00400000:
+ func (stream, "e");
+ break;
+ default:
+ func (stream, "p");
+ break;
+ }
+ break;
+ case 'R':
+ switch (given & 0x60)
+ {
+ case 0:
+ break;
+ case 0x20:
+ func (stream, "p");
+ break;
+ case 0x40:
+ func (stream, "m");
+ break;
+ default:
+ func (stream, "z");
+ break;
+ }
+ break;
+
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ {
+ int bitstart = *c++ - '0';
+ int bitend = 0;
+ while (*c >= '0' && *c <= '9')
+ bitstart = (bitstart * 10) + *c++ - '0';
+
+ switch (*c)
+ {
+ case '-':
+ c++;
+
+ while (*c >= '0' && *c <= '9')
+ bitend = (bitend * 10) + *c++ - '0';
+
+ if (!bitend)
+ abort ();
+
+ switch (*c)
+ {
+ case 'r':
+ {
+ long reg;
+
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+
+ func (stream, "%s", arm_regnames[reg]);
+ }
+ break;
+ case 'd':
+ {
+ long reg;
+
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+
+ func (stream, "%ld", reg);
+ }
+ break;
+ case 'f':
+ {
+ long reg;
+
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+
+ if (reg > 7)
+ func (stream, "#%s",
+ arm_fp_const[reg & 7]);
+ else
+ func (stream, "f%ld", reg);
+ }
+ break;
+
+ case 'w':
+ {
+ long reg;
+
+ if (bitstart != bitend)
+ {
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+ if (bitend - bitstart == 1)
+ func (stream, "%s", iwmmxt_wwnames[reg]);
+ else
+ func (stream, "%s", iwmmxt_wwssnames[reg]);
+ }
+ else
+ {
+ reg = (((given >> 8) & 0x1) |
+ ((given >> 22) & 0x1));
+ func (stream, "%s", iwmmxt_wwnames[reg]);
+ }
+ }
+ break;
+
+ case 'g':
+ {
+ long reg;
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+ func (stream, "%s", iwmmxt_regnames[reg]);
+ }
+ break;
+
+ case 'G':
+ {
+ long reg;
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+ func (stream, "%s", iwmmxt_cregnames[reg]);
+ }
+ break;
+
+ default:
+ abort ();
+ }
+ break;
+
+ case 'y':
+ case 'z':
+ {
+ int single = *c == 'y';
+ int regno;
+
+ switch (bitstart)
+ {
+ case 4: /* Sm pair */
+ func (stream, "{");
+ /* Fall through. */
+ case 0: /* Sm, Dm */
+ regno = given & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 5) & 1;
+ }
+ break;
+
+ case 1: /* Sd, Dd */
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ break;
- /* Fallback. */
- {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
- {0, 0, 0, 0}
-};
-
-static const char *const arm_conditional[] =
-{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
- "hi", "ls", "ge", "lt", "gt", "le", "", "<und>"};
+ case 2: /* Sn, Dn */
+ regno = (given >> 16) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 7) & 1;
+ }
+ break;
-static const char *const arm_fp_const[] =
-{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
+ case 3: /* List */
+ func (stream, "{");
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ break;
-static const char *const arm_shift[] =
-{"lsl", "lsr", "asr", "ror"};
-typedef struct
-{
- const char *name;
- const char *description;
- const char *reg_names[16];
-}
-arm_regname;
+ default:
+ abort ();
+ }
-static const arm_regname regnames[] =
-{
- { "raw" , "Select raw register names",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
- { "gcc", "Select register names used by GCC",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "std", "Select register names used in ARM's ISA documentation",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
- { "apcs", "Select register names used in the APCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "atpcs", "Select register names used in the ATPCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
- { "special-atpcs", "Select special register names used in the ATPCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
-};
+ func (stream, "%c%d", single ? 's' : 'd', regno);
-static const char *const iwmmxt_wwnames[] =
-{"b", "h", "w", "d"};
+ if (bitstart == 3)
+ {
+ int count = given & 0xff;
-static const char *const iwmmxt_wwssnames[] =
-{"b", "bus", "b", "bss",
- "h", "hus", "h", "hss",
- "w", "wus", "w", "wss",
- "d", "dus", "d", "dss"
-};
+ if (single == 0)
+ count >>= 1;
-static const char *const iwmmxt_regnames[] =
-{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
- "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
-};
+ if (--count)
+ {
+ func (stream, "-%c%d",
+ single ? 's' : 'd',
+ regno + count);
+ }
-static const char *const iwmmxt_cregnames[] =
-{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
- "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
-};
+ func (stream, "}");
+ }
+ else if (bitstart == 4)
+ func (stream, ", %c%d}", single ? 's' : 'd',
+ regno + 1);
-/* Default to GCC register name set. */
-static unsigned int regname_selected = 1;
+ break;
+ }
-#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
-#define arm_regnames regnames[regname_selected].reg_names
+ break;
-static bfd_boolean force_thumb = FALSE;
+ case '`':
+ c++;
+ if ((given & (1 << bitstart)) == 0)
+ func (stream, "%c", *c);
+ break;
+ case '\'':
+ c++;
+ if ((given & (1 << bitstart)) != 0)
+ func (stream, "%c", *c);
+ break;
+ case '?':
+ ++c;
+ if ((given & (1 << bitstart)) != 0)
+ func (stream, "%c", *c++);
+ else
+ func (stream, "%c", *++c);
+ break;
+ default:
+ abort ();
+ }
+ break;
-\f
-/* Functions. */
-int
-get_arm_regname_num_options (void)
-{
- return NUM_ARM_REGNAMES;
-}
+ case 'L':
+ switch (given & 0x00400100)
+ {
+ case 0x00000000: func (stream, "b"); break;
+ case 0x00400000: func (stream, "h"); break;
+ case 0x00000100: func (stream, "w"); break;
+ case 0x00400100: func (stream, "d"); break;
+ default:
+ break;
+ }
+ break;
-int
-set_arm_regname_option (int option)
-{
- int old = regname_selected;
- regname_selected = option;
- return old;
-}
+ case 'Z':
+ {
+ int value;
+ /* given (20, 23) | given (0, 3) */
+ value = ((given >> 16) & 0xf0) | (given & 0xf);
+ func (stream, "%d", value);
+ }
+ break;
-int
-get_arm_regnames (int option, const char **setname, const char **setdescription,
- const char *const **register_names)
-{
- *setname = regnames[option].name;
- *setdescription = regnames[option].description;
- *register_names = regnames[option].reg_names;
- return 16;
-}
+ case 'l':
+ /* This is like the 'A' operator, except that if
+ the width field "M" is zero, then the offset is
+ *not* multiplied by four. */
+ {
+ int offset = given & 0xff;
+ int multiplier = (given & 0x00000100) ? 4 : 1;
-static void
-arm_decode_shift (long given, fprintf_ftype func, void *stream)
-{
- func (stream, "%s", arm_regnames[given & 0xf]);
+ func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
- if ((given & 0xff0) != 0)
- {
- if ((given & 0x10) == 0)
- {
- int amount = (given & 0xf80) >> 7;
- int shift = (given & 0x60) >> 5;
+ if (offset)
+ {
+ if ((given & 0x01000000) != 0)
+ func (stream, ", #%s%d]%s",
+ ((given & 0x00800000) == 0 ? "-" : ""),
+ offset * multiplier,
+ ((given & 0x00200000) != 0 ? "!" : ""));
+ else
+ func (stream, "], #%s%d",
+ ((given & 0x00800000) == 0 ? "-" : ""),
+ offset * multiplier);
+ }
+ else
+ func (stream, "]");
+ }
+ break;
- if (amount == 0)
- {
- if (shift == 3)
- {
- func (stream, ", rrx");
- return;
+ default:
+ abort ();
+ }
+ }
}
-
- amount = 32;
+ else
+ func (stream, "%c", *c);
}
-
- func (stream, ", %s #%d", arm_shift[shift], amount);
+ return TRUE;
}
- else
- func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
- arm_regnames[(given & 0xf00) >> 8]);
}
+ return FALSE;
}
/* Print one ARM instruction from PC on INFO->STREAM. */
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
+ if (print_insn_coprocessor (info, given, FALSE))
+ return;
+
for (insn = arm_opcodes; insn->assembler; insn++)
{
if (insn->value == FIRST_IWMMXT_INSN
address = offset + pc + 8;
if (given & 0x01000000)
- /* H bit allows addressing to 2-byte boundaries. */
- address += 2;
-
- info->print_address_func (address, info);
- }
- break;
-
- case 'I':
- /* Print a Cirrus/DSP shift immediate. */
- /* Immediates are 7bit signed ints with bits 0..3 in
- bits 0..3 of opcode and bits 4..6 in bits 5..7
- of opcode. */
- {
- int imm;
-
- imm = (given & 0xf) | ((given & 0xe0) >> 1);
-
- /* Is ``imm'' a negative number? */
- if (imm & 0x40)
- imm |= (-1 << 7);
+ /* H bit allows addressing to 2-byte boundaries. */
+ address += 2;
- func (stream, "%d", imm);
+ info->print_address_func (address, info);
}
-
break;
case 'C':
func (stream, "c");
break;
- case 'F':
- switch (given & 0x00408000)
- {
- case 0:
- func (stream, "4");
- break;
- case 0x8000:
- func (stream, "1");
- break;
- case 0x00400000:
- func (stream, "2");
- break;
- default:
- func (stream, "3");
- }
- break;
-
- case 'P':
- switch (given & 0x00080080)
- {
- case 0:
- func (stream, "s");
- break;
- case 0x80:
- func (stream, "d");
- break;
- case 0x00080000:
- func (stream, "e");
- break;
- default:
- func (stream, _("<illegal precision>"));
- break;
- }
- break;
- case 'Q':
- switch (given & 0x00408000)
- {
- case 0:
- func (stream, "s");
- break;
- case 0x8000:
- func (stream, "d");
- break;
- case 0x00400000:
- func (stream, "e");
- break;
- default:
- func (stream, "p");
- break;
- }
- break;
- case 'R':
- switch (given & 0x60)
- {
- case 0:
- break;
- case 0x20:
- func (stream, "p");
- break;
- case 0x40:
- func (stream, "m");
- break;
- default:
- func (stream, "z");
- break;
- }
- break;
-
case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
{
func (stream, "%01lx", reg & 0xf);
}
break;
- case 'f':
- {
- long reg;
-
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
-
- if (reg > 7)
- func (stream, "#%s",
- arm_fp_const[reg & 7]);
- else
- func (stream, "f%ld", reg);
- }
- break;
-
- case 'w':
- {
- long reg;
-
- if (bitstart != bitend)
- {
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- if (bitend - bitstart == 1)
- func (stream, "%s", iwmmxt_wwnames[reg]);
- else
- func (stream, "%s", iwmmxt_wwssnames[reg]);
- }
- else
- {
- reg = (((given >> 8) & 0x1) |
- ((given >> 22) & 0x1));
- func (stream, "%s", iwmmxt_wwnames[reg]);
- }
- }
- break;
-
- case 'g':
- {
- long reg;
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%s", iwmmxt_regnames[reg]);
- }
- break;
-
- case 'G':
- {
- long reg;
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%s", iwmmxt_cregnames[reg]);
- }
- break;
-
default:
abort ();
}
break;
- case 'y':
- case 'z':
- {
- int single = *c == 'y';
- int regno;
-
- switch (bitstart)
- {
- case 4: /* Sm pair */
- func (stream, "{");
- /* Fall through. */
- case 0: /* Sm, Dm */
- regno = given & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 5) & 1;
- }
- break;
-
- case 1: /* Sd, Dd */
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- break;
-
- case 2: /* Sn, Dn */
- regno = (given >> 16) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 7) & 1;
- }
- break;
-
- case 3: /* List */
- func (stream, "{");
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- break;
-
-
- default:
- abort ();
- }
-
- func (stream, "%c%d", single ? 's' : 'd', regno);
-
- if (bitstart == 3)
- {
- int count = given & 0xff;
-
- if (single == 0)
- count >>= 1;
-
- if (--count)
- {
- func (stream, "-%c%d",
- single ? 's' : 'd',
- regno + count);
- }
-
- func (stream, "}");
- }
- else if (bitstart == 4)
- func (stream, ", %c%d}", single ? 's' : 'd',
- regno + 1);
-
- break;
- }
-
case '`':
c++;
if ((given & (1 << bitstart)) == 0)
}
break;
- case 'L':
- switch (given & 0x00400100)
- {
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
- default:
- break;
- }
- break;
-
- case 'Z':
- {
- int value;
- /* given (20, 23) | given (0, 3) */
- value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", value);
- }
- break;
-
- case 'l':
- /* This is like the 'A' operator, except that if
- the width field "M" is zero, then the offset is
- *not* multiplied by four. */
- {
- int offset = given & 0xff;
- int multiplier = (given & 0x00000100) ? 4 : 1;
-
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
-
- if (offset)
- {
- if ((given & 0x01000000) != 0)
- func (stream, ", #%s%d]%s",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * multiplier,
- ((given & 0x00200000) != 0 ? "!" : ""));
- else
- func (stream, "], #%s%d",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * multiplier);
- }
- else
- func (stream, "]");
- }
- break;
-
case 'e':
{
int imm;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
+ if (print_insn_coprocessor (info, given, TRUE))
+ return;
+
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
projects / external / binutils.git / commitdiff