if (cpu.architecture() >= 7) {
if (FLAG_enable_armv7) supported_ |= 1u << ARMv7;
+ if (FLAG_enable_armv8 && cpu.architecture() >= 8) {
+ supported_ |= 1u << ARMv8;
+ }
if (FLAG_enable_unaligned_accesses) supported_ |= 1u << UNALIGNED_ACCESSES;
// Use movw/movt for QUALCOMM ARMv7 cores.
if (FLAG_enable_movw_movt && cpu.implementer() == base::CPU::QUALCOMM) {
#else
#define ENABLE_ARMV7_DEFAULT false
#endif
+#if (defined CAN_USE_ARMV8_INSTRUCTIONS) || !(defined ARM_TEST_NO_FEATURE_PROBE)
+#define ENABLE_ARMV8_DEFAULT true
+#else
+#define ENABLE_ARMV8_DEFAULT false
+#endif
#if (defined CAN_USE_VFP32DREGS) || !(defined ARM_TEST_NO_FEATURE_PROBE)
#define ENABLE_32DREGS_DEFAULT true
#else
"enable use of VFP3 instructions if available")
DEFINE_BOOL(enable_armv7, ENABLE_ARMV7_DEFAULT,
"enable use of ARMv7 instructions if available (ARM only)")
+DEFINE_BOOL(enable_armv8, ENABLE_ARMV8_DEFAULT,
+ "enable use of ARMv8 instructions if available (ARM 32-bit only)")
DEFINE_BOOL(enable_neon, ENABLE_NEON_DEFAULT,
"enable use of NEON instructions if available (ARM only)")
DEFINE_BOOL(enable_sudiv, true,
// CPU feature flags.
enum CpuFeature {
- // x86
- SSE4_1,
- SSE3,
- SAHF,
- // ARM
- VFP3,
- ARMv7,
- SUDIV,
- MLS,
- UNALIGNED_ACCESSES,
- MOVW_MOVT_IMMEDIATE_LOADS,
- VFP32DREGS,
- NEON,
- // MIPS, MIPS64
- FPU,
- FP64FPU,
- MIPSr1,
- MIPSr2,
- MIPSr6,
- // ARM64
- ALWAYS_ALIGN_CSP,
- NUMBER_OF_CPU_FEATURES
+ // x86
+ SSE4_1,
+ SSE3,
+ SAHF,
+ // ARM
+ VFP3,
+ ARMv7,
+ ARMv8,
+ SUDIV,
+ MLS,
+ UNALIGNED_ACCESSES,
+ MOVW_MOVT_IMMEDIATE_LOADS,
+ VFP32DREGS,
+ NEON,
+ // MIPS, MIPS64
+ FPU,
+ FP64FPU,
+ MIPSr1,
+ MIPSr2,
+ MIPSr6,
+ // ARM64
+ ALWAYS_ALIGN_CSP,
+ NUMBER_OF_CPU_FEATURES
};