arm64/esr: Document ISS for ZT0 being disabled

SME2 defines a new ISS code for use when trapping acesses to ZT0, add a
definition for it.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-5-f2fa0aef982f@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 15b34fb..5f3271e 100644 (file)
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -341,6 +341,7 @@
 #define ESR_ELx_SME_ISS_ILL            1
 #define ESR_ELx_SME_ISS_SM_DISABLED    2
 #define ESR_ELx_SME_ISS_ZA_DISABLED    3
+#define ESR_ELx_SME_ISS_ZT_DISABLED    4
 
 #ifndef __ASSEMBLY__
 #include <asm/types.h>