Update the pixel shader of subpic function for BDW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

diff --git a/src/i965_render.c b/src/i965_render.c
index 36eca9d..c386721 100644 (file)
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -162,9 +162,9 @@ static const uint32_t ps_kernel_static_gen8[][4] = {
 };
 
 static const uint32_t ps_subpic_kernel_static_gen8[][4] = {
-#include "shaders/render/exa_wm_src_affine.g7b"
-#include "shaders/render/exa_wm_src_sample_argb.g7b"
-#include "shaders/render/exa_wm_write.g7b"
+#include "shaders/render/exa_wm_src_affine.g8b"
+#include "shaders/render/exa_wm_src_sample_argb.g8b"
+#include "shaders/render/exa_wm_write.g8b"
 };
 
 

diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am
index 47d5a6b..33aa367 100644 (file)
--- a/src/shaders/render/Makefile.am
+++ b/src/shaders/render/Makefile.am
@@ -88,6 +88,7 @@ INTEL_G7B_HASWELL = \
 INTEL_G8A =                            \
        exa_wm_src_affine.g8a           \
        exa_wm_src_sample_planar.g8a    \
+       exa_wm_src_sample_argb.g8a      \
        exa_wm_write.g8a                \
        exa_wm_yuv_rgb.g8a
 
@@ -96,6 +97,7 @@ INTEL_G8S = $(INTEL_G8A:%.g8a=%.g8s)
 INTEL_G8B =                            \
        exa_wm_src_affine.g8b           \
        exa_wm_src_sample_planar.g8b    \
+       exa_wm_src_sample_argb.g8b      \
        exa_wm_yuv_rgb.g8b              \
        exa_wm_write.g8b 
 

diff --git a/src/shaders/render/exa_wm_src_sample_argb.g8a b/src/shaders/render/exa_wm_src_sample_argb.g8a
new file mode 100644 (file)
index 0000000..662ef22
--- /dev/null
+++ b/src/shaders/render/exa_wm_src_sample_argb.g8a
@@ -0,0 +1,59 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Wang Zhenyu <zhenyu.z.wang@intel.com>
+ *    Keith Packard <keithp@keithp.com>
+ */
+
+/* Sample the src surface */
+
+include(`exa_wm.g4i')
+
+/* Ivybridge uses GRFs in SEND instruction */
+define(`src_msg_gen8',   `g65')
+define(`src_msg_ind_gen8',`65')
+
+/* subpicture global alpha */
+define(`global_alpha',     `r6.0<0,1,0>f')
+
+/* prepare sampler read back gX register, which would be written back to output */
+
+/* use simd16 sampler, param 0 is u, param 1 is v. */
+/* 'payload' loading, assuming tex coord start from g4 */
+
+/* load argb */
+mov (1) g0.8<1>UD               0x00000000UD { align1 mask_disable };
+mov (8) src_msg_gen8<1>UD       g0<8,8,1>UD  { align1 mask_disable };
+
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+send (16) src_msg_ind_gen8     /* msg reg index */
+       src_sample_base<1>UW    /* readback */
+       null
+       sampler (1,0,F)         /* sampler message description, (binding_table,sampler_index,datatype)
+                               /* here(src->dst) we should use src_sampler and src_surface */
+       mlen 5 rlen 8 { align1 };   /* required message len 5, readback len 8 */
+
+mul (8) src_sample_a_01<1>f src_sample_a_01<1>f global_alpha { align1 mask_disable };
+mul (8) src_sample_a_23<1>f src_sample_a_23<1>f global_alpha { align1 mask_disable };
+

diff --git a/src/shaders/render/exa_wm_src_sample_argb.g8b b/src/shaders/render/exa_wm_src_sample_argb.g8b
new file mode 100644 (file)
index 0000000..3c86fb8
--- /dev/null
+++ b/src/shaders/render/exa_wm_src_sample_argb.g8b
@@ -0,0 +1,5 @@
+   { 0x00000001, 0x2008060c, 0x00000000, 0x00000000 },
+   { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 },
+   { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a8c0001 },
+   { 0x00600041, 0x22803aec, 0x3a200280, 0x000000c0 },
+   { 0x00600041, 0x22a03aec, 0x3a2002a0, 0x000000c0 },