i965_drv_video: rendere I420/YV12 surface on SandyBridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/i965_drv_video/i965_defines.h b/i965_drv_video/i965_defines.h
index 3285b79..678d348 100644 (file)
--- a/i965_drv_video/i965_defines.h
+++ b/i965_drv_video/i965_defines.h
@@ -125,6 +125,11 @@
 #define GEN6_3DSTATE_CONSTANT_GS               CMD(3, 0, 0x16)
 #define GEN6_3DSTATE_CONSTANT_PS               CMD(3, 0, 0x17)
 
+# define GEN6_3DSTATE_CONSTANT_BUFFER_3_ENABLE  (1 << 15)
+# define GEN6_3DSTATE_CONSTANT_BUFFER_2_ENABLE  (1 << 14)
+# define GEN6_3DSTATE_CONSTANT_BUFFER_1_ENABLE  (1 << 13)
+# define GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE  (1 << 12)
+
 #define GEN6_3DSTATE_SAMPLE_MASK               CMD(3, 0, 0x18)
 
 #define GEN6_3DSTATE_MULTISAMPLE               CMD(3, 1, 0x0d)

diff --git a/i965_drv_video/i965_render.c b/i965_drv_video/i965_render.c
index 7f94a2b..3092195 100644 (file)
--- a/i965_drv_video/i965_render.c
+++ b/i965_drv_video/i965_render.c
@@ -1596,6 +1596,7 @@ gen6_render_setup_states(VADriverContextP ctx,
     gen6_render_color_calc_state(ctx);
     gen6_render_blend_state(ctx);
     gen6_render_depth_stencil_state(ctx);
+    i965_render_upload_constants(ctx);
     i965_render_upload_vertex(ctx, surface,
                               srcx, srcy, srcw, srch,
                               destx, desty, destw, desth);
@@ -1798,9 +1799,16 @@ gen6_emit_sf_state(VADriverContextP ctx)
 static void 
 gen6_emit_wm_state(VADriverContextP ctx, int kernel)
 {
-    /* disable WM constant buffer */
-    OUT_BATCH(ctx, GEN6_3DSTATE_CONSTANT_PS | (5 - 2));
-    OUT_BATCH(ctx, 0);
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct i965_render_state *render_state = &i965->render_state;
+
+    OUT_BATCH(ctx, GEN6_3DSTATE_CONSTANT_PS |
+              GEN6_3DSTATE_CONSTANT_BUFFER_0_ENABLE |
+              (5 - 2));
+    OUT_RELOC(ctx, 
+              render_state->curbe.bo,
+              I915_GEM_DOMAIN_INSTRUCTION, 0,
+              0);
     OUT_BATCH(ctx, 0);
     OUT_BATCH(ctx, 0);
     OUT_BATCH(ctx, 0);

diff --git a/i965_drv_video/shaders/render/exa_wm_src_affine.g6a b/i965_drv_video/shaders/render/exa_wm_src_affine.g6a
index 08195a4..568aef3 100644 (file)
--- a/i965_drv_video/shaders/render/exa_wm_src_affine.g6a
+++ b/i965_drv_video/shaders/render/exa_wm_src_affine.g6a
@@ -35,8 +35,8 @@ define(`vh',    `m5')
 define(`bl',    `g2.0<8,8,1>F')
 define(`bh',    `g4.0<8,8,1>F')
 
-define(`a0_a_x',`g6.0<0,1,0>F')
-define(`a0_a_y',`g6.16<0,1,0>F')
+define(`a0_a_x',`g7.0<0,1,0>F')
+define(`a0_a_y',`g7.16<0,1,0>F')
 
 /* U */
 pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */

diff --git a/i965_drv_video/shaders/render/exa_wm_src_affine.g6b b/i965_drv_video/shaders/render/exa_wm_src_affine.g6b
index 7035e6a..5d0ffcc 100644 (file)
--- a/i965_drv_video/shaders/render/exa_wm_src_affine.g6b
+++ b/i965_drv_video/shaders/render/exa_wm_src_affine.g6b
@@ -1,4 +1,4 @@
-   { 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 },
-   { 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 },
-   { 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 },
-   { 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 },
+   { 0x0060005a, 0x204077be, 0x000000e0, 0x008d0040 },
+   { 0x0060005a, 0x206077be, 0x000000e0, 0x008d0080 },
+   { 0x0060005a, 0x208077be, 0x000000f0, 0x008d0040 },
+   { 0x0060005a, 0x20a077be, 0x000000f0, 0x008d0080 },

diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a
index 1f78629..9f907fc 100644 (file)
--- a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a
+++ b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6a
@@ -28,23 +28,57 @@
 /* Sample the src surface in planar format */
 
 include(`exa_wm.g4i')
+/* UV flag */
+define(`nv12', `g6.0<0,1,0>UW')
 
 /* prepare sampler read back gX register, which would be written back to output */
 
 /* use simd16 sampler, param 0 is u, param 1 is v. */
 /* 'payload' loading, assuming tex coord start from g4 */
+cmp.g.f0.0 (1) null nv12 0x0UW {align1};
+(f0.0) jmpi INTERLEAVED_UV;
 
-mov (1) g0.8<1>UD      0x0000c000UD { align1 mask_disable };
+/* load r */
+mov (1) g0.8<1>UD      0x0000e000UD { align1 mask_disable };
 mov (8) src_msg<1>UD   g0<8,8,1>UD  { align1 mask_disable };
 
-/* sample UV (CrCb) */
+/* src_msg will be copied with g0, as it contains send desc */
+/* emit sampler 'send' cmd */
+
+/* sample U (Cr) */
 send (16) src_msg_ind          /* msg reg index */
        src_sample_g<1>UW       /* readback */
-       null       
+       null
        sampler (3,2,F)         /* sampler message description, (binding_table,sampler_index,datatype)
                                /* here(src->dst) we should use src_sampler and src_surface */
-       mlen 5 rlen 4 { align1 };   /* required message len 5, readback len 8 */
+       mlen 5 rlen 2 { align1 };   /* required message len 5, readback len 8 */
+
+/* sample V (Cb) */
+mov (1) g0.8<1>UD      0x0000e000UD { align1 mask_disable };
+mov (8) src_msg<1>UD   g0<8,8,1>UD  { align1 mask_disable };
+
+send (16) src_msg_ind          /* msg reg index */
+       src_sample_b<1>UW       /* readback */
+       null
+       sampler (5,4,F)         /* sampler message description, (binding_table,sampler_index,datatype)
+                               /* here(src->dst) we should use src_sampler and src_surface */
+       mlen 5 rlen 2 { align1 };   /* required message len 5, readback len 8 */
+
+jmpi SAMPLE_Y;
+
+INTERLEAVED_UV:
+mov (1) g0.8<1>UD       0x0000c000UD { align1 mask_disable };
+mov (8) src_msg<1>UD    g0<8,8,1>UD  { align1 mask_disable };
+
+/* sample UV (CrCb) */
+send (16) src_msg_ind           /* msg reg index */
+        src_sample_g<1>UW       /* readback */                                                                                                                         
+        null
+        sampler (3,2,F)         /* sampler message description, (binding_table,sampler_index,datatype)
+                                /* here(src->dst) we should use src_sampler and src_surface */
+        mlen 5 rlen 4 { align1 };   /* required message len 5, readback len 8 */
 
+SAMPLE_Y:
 mov (1) g0.8<1>UD      0x0000e000UD { align1 mask_disable };
 mov (8) src_msg<1>UD   g0<8,8,1>UD  { align1 mask_disable };
 

diff --git a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b
index ef45022..e9368b6 100644 (file)
--- a/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b
+++ b/i965_drv_video/shaders/render/exa_wm_src_sample_planar.g6b
@@ -1,3 +1,12 @@
+   { 0x03000010, 0x20002d3c, 0x000000c0, 0x00000000 },
+   { 0x00010020, 0x34001c00, 0x00001400, 0x0000000e },
+   { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+   { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 },
+   { 0x02800031, 0x22001cc9, 0x00000020, 0x0a2a0203 },
+   { 0x00000201, 0x20080061, 0x00000000, 0x0000e000 },
+   { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 },
+   { 0x02800031, 0x22401cc9, 0x00000020, 0x0a2a0405 },
+   { 0x00000020, 0x34001c00, 0x00001400, 0x00000006 },
    { 0x00000201, 0x20080061, 0x00000000, 0x0000c000 },
    { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 },
    { 0x02800031, 0x22001cc9, 0x00000020, 0x0a4a0203 },