%mul = mul i32 %sel, %y
ret i32 %mul
}
+
+; fold mul(abs(x),abs(x)) -> mul(x,x)
+define i31 @combine_mul_abs_i31(i31 %0) {
+; CHECK-LABEL: @combine_mul_abs_i31(
+; CHECK-NEXT: [[C:%.*]] = icmp slt i31 [[TMP0:%.*]], 0
+; CHECK-NEXT: [[S:%.*]] = sub nsw i31 0, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i31 [[S]], i31 [[TMP0]]
+; CHECK-NEXT: [[M:%.*]] = mul i31 [[R]], [[R]]
+; CHECK-NEXT: ret i31 [[M]]
+;
+ %c = icmp slt i31 %0, 0
+ %s = sub nsw i31 0, %0
+ %r = select i1 %c, i31 %s, i31 %0
+ %m = mul i31 %r, %r
+ ret i31 %m
+}
+
+define i32 @combine_mul_abs_i32(i32 %0) {
+; CHECK-LABEL: @combine_mul_abs_i32(
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP0:%.*]], 0
+; CHECK-NEXT: [[S:%.*]] = sub nsw i32 0, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[S]], i32 [[TMP0]]
+; CHECK-NEXT: [[M:%.*]] = mul i32 [[R]], [[R]]
+; CHECK-NEXT: ret i32 [[M]]
+;
+ %c = icmp slt i32 %0, 0
+ %s = sub nsw i32 0, %0
+ %r = select i1 %c, i32 %s, i32 %0
+ %m = mul i32 %r, %r
+ ret i32 %m
+}
+
+define <4 x i32> @combine_mul_abs_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: @combine_mul_abs_v4i32(
+; CHECK-NEXT: [[C:%.*]] = icmp slt <4 x i32> [[TMP0:%.*]], zeroinitializer
+; CHECK-NEXT: [[S:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> [[S]], <4 x i32> [[TMP0]]
+; CHECK-NEXT: [[M:%.*]] = mul <4 x i32> [[R]], [[R]]
+; CHECK-NEXT: ret <4 x i32> [[M]]
+;
+ %c = icmp slt <4 x i32> %0, zeroinitializer
+ %s = sub nsw <4 x i32> zeroinitializer, %0
+ %r = select <4 x i1> %c, <4 x i32> %s, <4 x i32> %0
+ %m = mul <4 x i32> %r, %r
+ ret <4 x i32> %m
+}
+
+; fold mul(nabs(x),nabs(x)) -> mul(x,x)
+define i31 @combine_mul_nabs_i31(i31 %0) {
+; CHECK-LABEL: @combine_mul_nabs_i31(
+; CHECK-NEXT: [[C:%.*]] = icmp slt i31 [[TMP0:%.*]], 0
+; CHECK-NEXT: [[S:%.*]] = sub nsw i31 0, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i31 [[TMP0]], i31 [[S]]
+; CHECK-NEXT: [[M:%.*]] = mul i31 [[R]], [[R]]
+; CHECK-NEXT: ret i31 [[M]]
+;
+ %c = icmp slt i31 %0, 0
+ %s = sub nsw i31 0, %0
+ %r = select i1 %c, i31 %0, i31 %s
+ %m = mul i31 %r, %r
+ ret i31 %m
+}
+
+define i32 @combine_mul_nabs_i32(i32 %0) {
+; CHECK-LABEL: @combine_mul_nabs_i32(
+; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP0:%.*]], 0
+; CHECK-NEXT: [[S:%.*]] = sub nsw i32 0, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP0]], i32 [[S]]
+; CHECK-NEXT: [[M:%.*]] = mul i32 [[R]], [[R]]
+; CHECK-NEXT: ret i32 [[M]]
+;
+ %c = icmp slt i32 %0, 0
+ %s = sub nsw i32 0, %0
+ %r = select i1 %c, i32 %0, i32 %s
+ %m = mul i32 %r, %r
+ ret i32 %m
+}
+
+define <4 x i32> @combine_mul_nabs_v4i32(<4 x i32> %0) {
+; CHECK-LABEL: @combine_mul_nabs_v4i32(
+; CHECK-NEXT: [[C:%.*]] = icmp slt <4 x i32> [[TMP0:%.*]], zeroinitializer
+; CHECK-NEXT: [[S:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP0]]
+; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i32> [[TMP0]], <4 x i32> [[S]]
+; CHECK-NEXT: [[M:%.*]] = mul <4 x i32> [[R]], [[R]]
+; CHECK-NEXT: ret <4 x i32> [[M]]
+;
+ %c = icmp slt <4 x i32> %0, zeroinitializer
+ %s = sub nsw <4 x i32> zeroinitializer, %0
+ %r = select <4 x i1> %c, <4 x i32> %0, <4 x i32> %s
+ %m = mul <4 x i32> %r, %r
+ ret <4 x i32> %m
+}