lib: sbi_hart: clear mip csr during hart init

If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes
spurious external interrupts. This breaks the boot up of HiFive Unmatched
board. Hence it is required to bring the mip CSR to a known state during
hart init and avoid spurious interrupts.

Fixes: d9e7368 ("firmware: Not to clear all the MIP")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index ceef44f26b1bafe75ca22b4b1b322a6c83b1fb24..5a3e89485a814d9258e23b2ea1197334c47ed904 100644 (file)
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -430,13 +430,6 @@ _start_warm:
 
        /* Disable all interrupts */
        csrw    CSR_MIE, zero
-       /*
-        * Only clear the MIP_SSIP and MIP_STIP. For the platform like QEMU,
-        * If we clear other interrupts like MIP_SEIP and the pendings of
-        * PLIC still exist, the QEMU may not set it back immediately.
-        */
-       li      t0, (MIP_SSIP | MIP_STIP)
-       csrc    CSR_MIP, t0
 
        /* Find HART count and HART stack size */
        lla     a4, platform

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5e06918c7a40f109973381abbfce5e8fa964c4d1..6e52cbd76d89f6921025e18e7ea7c8bb083de0d5 100644 (file)
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -733,6 +733,12 @@ int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
 {
        int rc;
 
+       /*
+        * Clear mip CSR before proceeding with init to avoid any spurious
+        * external interrupts in S-mode.
+        */
+       csr_write(CSR_MIP, 0);
+
        if (cold_boot) {
                if (misa_extension('H'))
                        sbi_hart_expected_trap = &__sbi_expected_trap_hext;