pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 473 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a1617d24af2b9b3224ce84c0ada535565009fdda.1649865241.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c
index b573da6..4c543ec 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77950.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77950.c
@@ -4701,23 +4701,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
 #define F_(x, y)       FN_##y
 #define FM(x)          FN_##x
-       { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
+       { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
+                            GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP0_31_16 RESERVED */
                GP_0_15_FN,     GPSR0_15,
                GP_0_14_FN,     GPSR0_14,
                GP_0_13_FN,     GPSR0_13,
@@ -4769,24 +4757,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_1_1_FN,      GPSR1_1,
                GP_1_0_FN,      GPSR1_0, ))
        },
-       { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
+       { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
+                            GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1),
+                            GROUP(
+               /* GP2_31_15 RESERVED */
                GP_2_14_FN,     GPSR2_14,
                GP_2_13_FN,     GPSR2_13,
                GP_2_12_FN,     GPSR2_12,
@@ -4803,23 +4778,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_2_1_FN,      GPSR2_1,
                GP_2_0_FN,      GPSR2_0, ))
        },
-       { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
+       { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
+                            GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP3_31_16 RESERVED */
                GP_3_15_FN,     GPSR3_15,
                GP_3_14_FN,     GPSR3_14,
                GP_3_13_FN,     GPSR3_13,
@@ -4837,21 +4800,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_3_1_FN,      GPSR3_1,
                GP_3_0_FN,      GPSR3_0, ))
        },
-       { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
+       { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
+                            GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                  1, 1, 1, 1, 1, 1, 1),
+                            GROUP(
+               /* GP4_31_18 RESERVED */
                GP_4_17_FN,     GPSR4_17,
                GP_4_16_FN,     GPSR4_16,
                GP_4_15_FN,     GPSR4_15,
@@ -4939,35 +4892,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                GP_6_1_FN,      GPSR6_1,
                GP_6_0_FN,      GPSR6_0, ))
        },
-       { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
-               0, 0,
+       { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
+                            GROUP(-28, 1, 1, 1, 1),
+                            GROUP(
+               /* GP7_31_4 RESERVED */
                GP_7_3_FN, GPSR7_3,
                GP_7_2_FN, GPSR7_2,
                GP_7_1_FN, GPSR7_1,
@@ -5148,13 +5076,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                IP16_7_4
                IP16_3_0 ))
        },
-       { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
-               /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-               /* IP17_11_8  */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+       { PINMUX_CFG_REG_VAR("IPSR17", 0xe6060244, 32,
+                            GROUP(-24, 4, 4),
+                            GROUP(
+               /* IP17_31_8 RESERVED */
                IP17_7_4
                IP17_3_0 ))
        },