drm/amd/display: Define couple extra DCN registers

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index f091d87..df3203a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -147,6 +147,7 @@
        SR(DCCG_GATE_DISABLE_CNTL2), \
        SR(DCFCLK_CNTL),\
        SR(DCFCLK_CNTL), \
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
        /* todo:  get these from GVM instead of reading registers ourselves */\
        MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
        MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 2a97cdb..d8ef30b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -42,6 +42,7 @@
 #define LE_DCN_COMMON_REG_LIST(id) \
        SRI(DIG_BE_CNTL, DIG, id), \
        SRI(DIG_BE_EN_CNTL, DIG, id), \
+       SRI(TMDS_CTL_BITS, DIG, id), \
        SRI(DP_CONFIG, DP, id), \
        SRI(DP_DPHY_CNTL, DP, id), \
        SRI(DP_DPHY_PRBS_CNTL, DP, id), \
@@ -64,6 +65,7 @@
        SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
        SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
 
+
 #define LE_DCN10_REG_LIST(id)\
        LE_DCN_COMMON_REG_LIST(id)
 
@@ -100,6 +102,7 @@ struct dcn10_link_enc_registers {
        uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
        uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
        uint32_t DP_SEC_CNTL1;
+       uint32_t TMDS_CTL_BITS;
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -110,6 +113,7 @@ struct dcn10_link_enc_registers {
        LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
        LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
        LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
+       LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
        LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
@@ -198,10 +202,11 @@ struct dcn10_link_enc_registers {
        type DP_MSE_SAT_SLOT_COUNT3;\
        type DP_MSE_SAT_UPDATE;\
        type DP_MSE_16_MTP_KEEPOUT;\
+       type DC_HPD_EN;\
+       type TMDS_CTL0;\
        type AUX_HPD_SEL;\
        type AUX_LS_READ_EN;\
-       type AUX_RX_RECEIVE_WINDOW;\
-       type DC_HPD_EN
+       type AUX_RX_RECEIVE_WINDOW
 
 struct dcn10_link_enc_shift {
        DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);