clk: exynos4: Add missing mout_sata on Exynos4210

This patch adds missing mout_sata that is a parent of div_sata clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7e875a462d899d240101768578cb559bc069c9be..e572f62ec4232edfdb0ccc87b40177613c574b0e 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -360,6 +360,7 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
        MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
        MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
        MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+       MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
        MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
        MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
        MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),