control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
- if (gpu->sec_mode == ETNA_SEC_KERNEL) {
+ if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) {
gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
VIVS_MMUv2_AHB_CONTROL_RESET);
} else {
gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
}
- if (gpu->sec_mode == ETNA_SEC_KERNEL) {
+ if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) {
u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
* On cores with security features supported, we claim control over the
* security states.
*/
- if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
+ if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) ||
(gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
gpu->sec_mode = ETNA_SEC_KERNEL;