Merge drm/drm-next into drm-misc-next

Backmerging drm/drm-next to get the latest changes in the xlnx driver.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index df6fd6d6a82c75be7328438941a257d5f435af91,69e105fa41f68461e58e91c1444fdd9246977449..59cf64216fbb662b54ec0dd6eef34597c730d7af
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@@ -139,10 -116,21 +139,17 @@@ static int amdgpu_vm_sdma_commit(struc
                                   DMA_RESV_USAGE_BOOKKEEP);
        }
  
-       if (fence && !p->immediate)
+       if (fence && !p->immediate) {
+               /*
+                * Most hw generations now have a separate queue for page table
+                * updates, but when the queue is shared with userspace we need
+                * the extra CPU round trip to correctly flush the TLB.
+                */
+               set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
                swap(*fence, f);
+       }
        dma_fence_put(f);
        return 0;
 -
 -error:
 -      amdgpu_job_free(p->job);
 -      return r;
  }
  
  /**

diff --cc drivers/gpu/drm/scheduler/sched_entity.c
Simple merge

diff --cc include/drm/gpu_scheduler.h
index e40baefadc3aacdb2218569045c5492a1cbcaf6a,ca11716d084a7bbea1326fc3fd00988fcc546d05..cec147f7c50bf1af0d1c5ed372ddc1db4b1eb32e
--- 1/include/drm/gpu_scheduler.h
--- 2/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@@ -32,8 -32,15 +32,17 @@@
  
  #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
  
+ /**
+  * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining
+  *
+  * Setting this flag on a scheduler fence prevents pipelining of jobs depending
+  * on this fence. In other words we always insert a full CPU round trip before
+  * dependen jobs are pushed to the hw queue.
+  */
+ #define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS
+ 
 +enum dma_resv_usage;
 +struct dma_resv;
  struct drm_gem_object;
  
  struct drm_gpu_scheduler;