riscv: dts: thead: convert isa detection to new properties

Convert the th1520 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231022154135.3746-1-jszhang@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 0804f3bec9e9a3e9f3b5431ac9a11417041bc4c2)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I98e3bc7c2f3629ea986b5b3c731289994642f2d4

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ff364709a6dfafd8393d3ff12dcaac2081700868..ba4d2c673ac8d33e229765bfdcff674aaf40f93c 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -20,6 +20,9 @@
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <0>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -41,6 +44,9 @@
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <1>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -62,6 +68,9 @@
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <2>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
@@ -83,6 +92,9 @@
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <3>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;