#define CONFIG_OMAP3_SPI
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __OMAP3_EVM_COMMON_H */
#define CONFIG_OMAP3_SPI
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
* - rest for filesystem
*/
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#endif
+#define CONFIG_SYS_CACHELINE_SIZE 32
/* Defines for SDRAM init */
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS