drm/amdgpu: renovate sdma fw struct

Add sdma firmware struct version 2 to support new SDMA v6 and forward
firmware version.

v2: squash in fix

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 3125499..ddef798 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -244,6 +244,17 @@ void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
                                container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
                        DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
                }
+       } else if (version_major == 2) {
+               const struct sdma_firmware_header_v2_0 *sdma_hdr =
+                       container_of(hdr, struct sdma_firmware_header_v2_0, header);
+
+               DRM_DEBUG("ucode_feature_version: %u\n",
+                         le32_to_cpu(sdma_hdr->ucode_feature_version));
+               DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
+               DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
+               DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
+               DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
+               DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
        } else {
                DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
                          version_major, version_minor);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 4439e01..f510b6a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -281,6 +281,19 @@ struct sdma_firmware_header_v1_1 {
        uint32_t digest_size;
 };
 
+/* version_major=2, version_minor=0 */
+struct sdma_firmware_header_v2_0 {
+       struct common_firmware_header header;
+       uint32_t ucode_feature_version;
+       uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
+       uint32_t ctx_jt_offset; /* context thread jt location */
+       uint32_t ctx_jt_size; /* context thread size of jt */
+       uint32_t ctl_ucode_offset;
+       uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
+       uint32_t ctl_jt_offset; /* control thread jt location */
+       uint32_t ctl_jt_size; /* control thread size of jt */
+};
+
 /* gpu info payload */
 struct gpu_info_firmware_v1_0 {
        uint32_t gc_num_se;
@@ -364,6 +377,7 @@ union amdgpu_firmware_header {
        struct rlc_firmware_header_v2_3 rlc_v2_3;
        struct sdma_firmware_header_v1_0 sdma;
        struct sdma_firmware_header_v1_1 sdma_v1_1;
+       struct sdma_firmware_header_v2_0 sdma_v2_0;
        struct gpu_info_firmware_header_v1_0 gpu_info;
        struct dmcu_firmware_header_v1_0 dmcu;
        struct dmcub_firmware_header_v1_0 dmcub;