recovery: code clean up (don't use the DOS file format)

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/recovery/board/samsung/universal/gpio.c b/recovery/board/samsung/universal/gpio.c
index 09e5c8d..82ea215 100644 (file)
--- a/recovery/board/samsung/universal/gpio.c
+++ b/recovery/board/samsung/universal/gpio.c
@@ -1,168 +1,168 @@
-/*\r
- * (C) Copyright 2009 Samsung Electronics\r
- * Minkyu Kang <mk7.kang@samsung.com>\r
- *\r
- * This program is free software; you can redistribute it and/or\r
- * modify it under the terms of the GNU General Public License as\r
- * published by the Free Software Foundation; either version 2 of\r
- * the License, or (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
- * MA 02111-1307 USA\r
- */\r
-\r
-#include <common.h>\r
-#include <asm/io.h>\r
-#include <asm/arch/gpio.h>\r
-\r
-#define CON_MASK(x)            (0xf << ((x) << 2))\r
-#define CON_SFR(x, v)          ((v) << ((x) << 2))\r
-\r
-#define DAT_MASK(x)            (0x1 << (x))\r
-#define DAT_SET(x)             (0x1 << (x))\r
-\r
-#define PULL_MASK(x)           (0x3 << ((x) << 1))\r
-#define PULL_MODE(x, v)                ((v) << ((x) << 1))\r
-\r
-#define DRV_MASK(x)            (0x3 << ((x) << 1))\r
-#define DRV_SET(x, m)          ((m) << ((x) << 1))\r
-#define RATE_MASK(x)           (0x1 << (x + 16))\r
-#define RATE_SET(x)            (0x1 << (x + 16))\r
-\r
-void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->con);\r
-       value &= ~CON_MASK(gpio);\r
-       value |= CON_SFR(gpio, cfg);\r
-       writel(value, &bank->con);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->con);\r
-}\r
-\r
-void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)\r
-{\r
-       unsigned int value;\r
-\r
-       gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);\r
-\r
-       value = readl(&bank->dat);\r
-       value &= ~DAT_MASK(gpio);\r
-       if (en)\r
-               value |= DAT_SET(gpio);\r
-       writel(value, &bank->dat);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->dat);\r
-}\r
-\r
-void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)\r
-{\r
-       gpio_cfg_pin(bank, gpio, GPIO_INPUT);\r
-}\r
-\r
-void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->dat);\r
-       value &= ~DAT_MASK(gpio);\r
-       if (en)\r
-               value |= DAT_SET(gpio);\r
-       writel(value, &bank->dat);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->dat);\r
-}\r
-\r
-unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->dat);\r
-       return !!(value & DAT_MASK(gpio));\r
-}\r
-\r
-void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->pull);\r
-       value &= ~PULL_MASK(gpio);\r
-\r
-       switch (mode) {\r
-       case GPIO_PULL_DOWN:\r
-       case GPIO_PULL_UP:\r
-               value |= PULL_MODE(gpio, mode);\r
-               break;\r
-       default:\r
-               break;\r
-       }\r
-\r
-       writel(value, &bank->pull);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->pull);\r
-}\r
-\r
-void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->drv);\r
-       value &= ~DRV_MASK(gpio);\r
-\r
-       switch (mode) {\r
-       case GPIO_DRV_1X:\r
-       case GPIO_DRV_2X:\r
-       case GPIO_DRV_3X:\r
-       case GPIO_DRV_4X:\r
-               value |= DRV_SET(gpio, mode);\r
-               break;\r
-       default:\r
-               return;\r
-       }\r
-\r
-       writel(value, &bank->drv);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->drv);\r
-}\r
-\r
-void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)\r
-{\r
-       unsigned int value;\r
-\r
-       value = readl(&bank->drv);\r
-       value &= ~RATE_MASK(gpio);\r
-\r
-       switch (mode) {\r
-       case GPIO_DRV_FAST:\r
-       case GPIO_DRV_SLOW:\r
-               value |= RATE_SET(gpio);\r
-               break;\r
-       default:\r
-               return;\r
-       }\r
-\r
-       writel(value, &bank->drv);\r
-#if 0\r
-       if (s5pc1xx_get_cpu_rev() == 0)\r
-#endif\r
-               value = readl(&bank->drv);\r
-}\r
-\r
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+#define CON_MASK(x)            (0xf << ((x) << 2))
+#define CON_SFR(x, v)          ((v) << ((x) << 2))
+
+#define DAT_MASK(x)            (0x1 << (x))
+#define DAT_SET(x)             (0x1 << (x))
+
+#define PULL_MASK(x)           (0x3 << ((x) << 1))
+#define PULL_MODE(x, v)                ((v) << ((x) << 1))
+
+#define DRV_MASK(x)            (0x3 << ((x) << 1))
+#define DRV_SET(x, m)          ((m) << ((x) << 1))
+#define RATE_MASK(x)           (0x1 << (x + 16))
+#define RATE_SET(x)            (0x1 << (x + 16))
+
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
+{
+       unsigned int value;
+
+       value = readl(&bank->con);
+       value &= ~CON_MASK(gpio);
+       value |= CON_SFR(gpio, cfg);
+       writel(value, &bank->con);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->con);
+}
+
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+       unsigned int value;
+
+       gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+
+       value = readl(&bank->dat);
+       value &= ~DAT_MASK(gpio);
+       if (en)
+               value |= DAT_SET(gpio);
+       writel(value, &bank->dat);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->dat);
+}
+
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+       gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+}
+
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+       unsigned int value;
+
+       value = readl(&bank->dat);
+       value &= ~DAT_MASK(gpio);
+       if (en)
+               value |= DAT_SET(gpio);
+       writel(value, &bank->dat);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->dat);
+}
+
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+       unsigned int value;
+
+       value = readl(&bank->dat);
+       return !!(value & DAT_MASK(gpio));
+}
+
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->pull);
+       value &= ~PULL_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_PULL_DOWN:
+       case GPIO_PULL_UP:
+               value |= PULL_MODE(gpio, mode);
+               break;
+       default:
+               break;
+       }
+
+       writel(value, &bank->pull);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->pull);
+}
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~DRV_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_1X:
+       case GPIO_DRV_2X:
+       case GPIO_DRV_3X:
+       case GPIO_DRV_4X:
+               value |= DRV_SET(gpio, mode);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, &bank->drv);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~RATE_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_FAST:
+       case GPIO_DRV_SLOW:
+               value |= RATE_SET(gpio);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, &bank->drv);
+#if 0
+       if (s5pc1xx_get_cpu_rev() == 0)
+#endif
+               value = readl(&bank->drv);
+}
+