ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB
authorMadalin Bucur <madalin.bucur@oss.nxp.com>
Thu, 23 Apr 2020 13:25:15 +0000 (16:25 +0300)
committerPriyanka Jain <priyanka.jain@nxp.com>
Wed, 29 Apr 2020 05:40:54 +0000 (11:10 +0530)
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/dts/fsl-ls1046a-rdb.dts
arch/arm/dts/fsl-ls1046a.dtsi

index 83e34ab..cac65a7 100644 (file)
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright 2016, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
 &i2c3 {
        status = "okay";
 };
+
+#include "fsl-ls1046-post.dtsi"
+
+&fman0 {
+       ethernet@e4000 {
+               phy-handle = <&rgmii_phy1>;
+               phy-connection-type = "rgmii-id";
+               status = "okay";
+       };
+
+       ethernet@e6000 {
+               phy-handle = <&rgmii_phy2>;
+               phy-connection-type = "rgmii-id";
+               status = "okay";
+       };
+
+       ethernet@e8000 {
+               phy-handle = <&sgmii_phy1>;
+               phy-connection-type = "sgmii";
+               status = "okay";
+       };
+
+       ethernet@ea000 {
+               phy-handle = <&sgmii_phy2>;
+               phy-connection-type = "sgmii";
+               status = "okay";
+       };
+
+       ethernet@f0000 { /* 10GEC1 */
+               phy-handle = <&aqr106_phy>;
+               phy-connection-type = "xgmii";
+               status = "okay";
+       };
+
+       ethernet@f2000 { /* 10GEC2 */
+               fixed-link = <0 1 1000 0 0>;
+               phy-connection-type = "xgmii";
+               status = "okay";
+       };
+
+       mdio@fc000 {
+               rgmii_phy1: ethernet-phy@1 {
+                       reg = <0x1>;
+               };
+
+               rgmii_phy2: ethernet-phy@2 {
+                       reg = <0x2>;
+               };
+
+               sgmii_phy1: ethernet-phy@3 {
+                       reg = <0x3>;
+               };
+
+               sgmii_phy2: ethernet-phy@4 {
+                       reg = <0x4>;
+               };
+       };
+
+       mdio@fd000 {
+               aqr106_phy: ethernet-phy@0 {
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       interrupts = <0 131 4>;
+                       reg = <0x0>;
+               };
+       };
+};
index fdf93fd..4e91d5c 100644 (file)
@@ -31,7 +31,7 @@
                interrupts = <1 9 0xf08>;
        };
 
-       soc {
+       soc: soc {
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;