PCI: tegra: Fix argument order in tegra_pcie_phy_disable()

The tegra_pcie_phy_disable() path called pads_writel() with arguments in
the wrong order.  Swap them to be the "value, offset" order expected by
pads_writel().

Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs")
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
CC: stable@vger.kernel.org	# v4.7+

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index e2a8e4c..6df5ed0 100644 (file)
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -859,7 +859,7 @@ static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
        /* override IDDQ */
        value = pads_readl(pcie, PADS_CTL);
        value |= PADS_CTL_IDDQ_1L;
-       pads_writel(pcie, PADS_CTL, value);
+       pads_writel(pcie, value, PADS_CTL);
 
        /* reset PLL */
        value = pads_readl(pcie, soc->pads_pll_ctl);