[ARM] Regenerate pr36577.ll test checks

diff --git a/llvm/test/CodeGen/ARM/pr36577.ll b/llvm/test/CodeGen/ARM/pr36577.ll
index 11805cb..c910ba9 100644 (file)
--- a/llvm/test/CodeGen/ARM/pr36577.ll
+++ b/llvm/test/CodeGen/ARM/pr36577.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
 ; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
@@ -7,14 +8,26 @@
 
 @a = common dso_local local_unnamed_addr global i16 0, align 2
 
-; CHECK-LABEL: pr36577
-; CHECK: ldrh r0, [r0]
-; CHECK: mvn   r0, r0, lsr #7
-; CHECK: orr r0, r1, r0, lsl #2
-; CHECK-T2: ldrh r0, [r0]
-; CHECK-T2: mvn.w      r0, r0, lsr #7
-; CHECK-T2: orr.w      r0, r1, r0, lsl #2
 define dso_local arm_aapcscc i32** @pr36577() {
+; CHECK-LABEL: pr36577:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    movw r0, :lower16:a
+; CHECK-NEXT:    mvn r1, #7
+; CHECK-NEXT:    movt r0, :upper16:a
+; CHECK-NEXT:    ldrh r0, [r0]
+; CHECK-NEXT:    mvn r0, r0, lsr #7
+; CHECK-NEXT:    orr r0, r1, r0, lsl #2
+; CHECK-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: pr36577:
+; CHECK-T2:       @ %bb.0: @ %entry
+; CHECK-T2-NEXT:    movw r0, :lower16:a
+; CHECK-T2-NEXT:    mvn r1, #7
+; CHECK-T2-NEXT:    movt r0, :upper16:a
+; CHECK-T2-NEXT:    ldrh r0, [r0]
+; CHECK-T2-NEXT:    mvn.w r0, r0, lsr #7
+; CHECK-T2-NEXT:    orr.w r0, r1, r0, lsl #2
+; CHECK-T2-NEXT:    bx lr
 entry:
   %0 = load i16, i16* @a, align 2
   %1 = lshr i16 %0, 7